WO2007135158A1 - Image sensor circuit - Google Patents
Image sensor circuit Download PDFInfo
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- WO2007135158A1 WO2007135158A1 PCT/EP2007/054968 EP2007054968W WO2007135158A1 WO 2007135158 A1 WO2007135158 A1 WO 2007135158A1 EP 2007054968 W EP2007054968 W EP 2007054968W WO 2007135158 A1 WO2007135158 A1 WO 2007135158A1
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- Prior art keywords
- image sensor
- column lines
- column
- lines
- busbars
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- 239000004020 conductor Substances 0.000 claims description 33
- 239000003990 capacitor Substances 0.000 claims description 30
- 230000003071 parasitic effect Effects 0.000 description 10
- 239000000872 buffer Substances 0.000 description 8
- 230000003321 amplification Effects 0.000 description 6
- 238000003199 nucleic acid amplification method Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000006880 cross-coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
- H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
- H04N25/677—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/767—Horizontal readout lines, multiplexers or registers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
Definitions
- the present invention relates to image sensor circuits, in particular to CMOS image sensor circuits.
- Such circuits usually comprise a pixel cell array having a plurality of pixel cells arranged along a plurality of column lines, and readout circuitry connected to said column lines and comprising one or more analogue-to-digital converters for converting analogue output signal voltages representative of an amount of light received by one of said pixel cells into digital data.
- EP 1 150 494 Bl discloses an image sensor circuit of this type, in which the readout circuitry comprises a multiplexer for selectively applying an output signal from one of the column lines to a common buffer amplifier. For converting the output signal from this buffer amplifier, a single analogue-to-digital converter (ADC) is required. Since there is only one ADC, it can be placed quite freely on a semiconductor substrate, and the size and shape of the area it occupies on the substrate is not subject to severe restrictions.
- ADC analogue-to-digital converter
- WO 99/46851 discloses an image sensor circuit which comprises a pixel cell array having a plurality of pixel cells arranged along a plurality of column lines, and a plurality of readout circuits, each of which is connected to two of said column lines and comprises an analogue-to-digital converter and a multiplexer for selectively applying an output signal of one of said two column lines to the converter.
- the ADCs may be much slower than the ADC according to the first-mentioned document, but instead there is a problem in that due to scattering of the characteristics of the readout circuits, an image obtained form this sensor circuit may present strip-shaped defects, and the space available for each readout circuit is limited.
- the object of the present invention is to provide an image sensor circuit which combines the advantages of the above mentioned prior art designs while avoiding their drawbacks .
- an image sensor circuit comprising a pixel cell array having a plurality of pixel cells arranged along a plurality of column lines, a plurality of readout circuits connected to said column lines, each of which comprises an analogue-to-digital converter and a multiplexer for selectively applying an output signal of one of said column lines to said analogue-to-digital converter, the circuit being characterized in that between two of said column lines connected to a first one of said readout circuits located at a first side of said pixel cell array, there is a column line which is connected to a second one of said readout circuits located at a second side of said pixel cell ar- ray opposite to said first side.
- each readout circuit comprises a plurality of bus bars, each bus bar having a subset of said column lines associated to it by switches located at intersections of the bus bar and of said associated column lines for selectively opening and closing an electrical connection between one of said associated column lines and said bus bar, wherein no two adjacent column lines are associated to a same bus bar.
- the readout circuit further preferably comprises a plurality of amplifiers having an input connected to an associated one of said bus bars, and a multiplexer having inputs connected to outputs of said amplifiers.
- the amplifiers can be placed far apart from the pixel cell array, so that heat dissipated by the amplifiers does substantially not reach the pixel cell array. By keeping the pixel cell array cool, noise is reduced, and the image quality is improved.
- the number of bus bars is n, it is preferred that among any n adjacent inputs of one of said readout circuits, there is one connected to each of said n bus bars. In this way, the column lines associated to a given bus bar are distributed all over the pixel cell array.
- Each column line preferably extends across all of said bus bars in order to make the parasitic capacitance resulting from these crossings the same for all column lines and all bus bars.
- each amplifier is con- nected to its associated bus bar by a line extending across all of said bus bars.
- each column line has associated to it two storage capacitors and a switch for selec- tively connecting one of said two capacitors to said column line, and each bus bar comprises a first line for connecting to the first capacitor and a second line for connecting to the second capacitor.
- each column line is formed of a planar conductor defining a first plane and is shielded by at least one grounded conductor which extends along said planar conductor in said first plane or in a second plane parallel to that first plane.
- each bus bar may comprise a planar conductor defining a second plane and may be shielded by at least one grounded conductor which extends along said planar conductor in said second plane or in a plane parallel to said second plane.
- Fig. 1 is a schematic diagram illustrating the localization of components of an image sensor circuit according to the present invention on a circuit substrate.
- Fig. 2 illustrates a detail of the circuit layout of
- Fig. 3 illustrates the overall structure of the bus bars of the circuit of Fig. 1 ;
- Fig. 4A, B are diagrams of bus bar fields
- Fig. 4C illustrates the structure of a switch in the bus bar fields of Fig. 4a, b;
- Fig. 5 is a schematic perspective view of an intersection of conductors in the bus bar field of Fig. 4A; and Fig. 6 is a view analogous to that of Fig. 5 of an intersection of conductors in the bus bar field of Fig. 4B.
- Fig. 1 schematically illustrates the layout of an image sensor circuit according to the present invention.
- a pixel array 1 comprising a large number of sensor pixels arranged in a pattern of rows and columns.
- the sensor pixels may be of any known type. They may e.g. be formed of conventional three-transistor circuits, which means that the sensor pixel itself has no storage capability.
- the architecture is not limited to this kind of pixels. It can be extended to pixels with larger numbers of transistors, which have storage associated to them and/or are capable of performing a global shutter operation.
- the size of the pixel array 1 is very large for HDTV applications, e. g. 1920 x 1080 pixels, which results in about 2 million pix- els in total. This means that the pixel array diagonal on the chip is easily reaching 10 mm or more, depending on the size of the individual pixels. This makes inter-pixel matching or alignment a major issue for imager design.
- a vertical scanning circuit 2 provides signals for selecting pixels of array 1 for reset or readout row by row. All pixels in a same row of the array 1 have their outputs connected to a same column line. There are odd- numbered column lines 4o and even-numbered column lines 4e. According to the invention the circuitry for reading out the pixel array 1 has been divided into two blocks. One block is provided for reading out the even column lines 4e, the other block is provided for reading out the odd column lines 4o. Both readout blocks are identical, one is placed in the layout on top of the pixel array 1, the other, at the bottom of it.
- Readout blocks include: column readout circuits 3o, 3e comprising a sampling storage block, bus bars and a bus bar multiplexer, an amplification/offset compensation block 6o, 6e comprising a plurality of amplifiers, an ADC multiplexer and a buffer, and an ADC 7.
- Fig. 2 illustrates in more detail a section of the pixel array 1 and of the readout circuitry.
- the readout circuitry is illustrated for even-numbered column lines only, the readout circuitry for the odd-numbered lines is a specular image of that for the even-numbered lines and need not be specifically described.
- Fig. 2 shows twelve pixels 8 of pixel array 1 arranged in two rows and six columns. The pixels 8 have their outputs connected to odd column lines 4 X , 4 3 , ..., 4 2m -i and even column lines 4 2 , 4 4 , ..., 4 2m , respectively, 2m being the total number of column lines in pixel array 1.
- Two storage capacitors 9d, 9b are connected to the end of each column line by a switch 10 near the border of pixel array 1.
- the output voltage levels of dark pixels and of illuminated pixels alternate all the column lines.
- the switch 10 By means of the switch 10, an output voltage from a dark pixel is sampled and stored in storage capacitor 9d, whereas that of an illuminated pixel in an adjacent row is stored in capacitor 9b.
- n parallel bus bars Hi, H2, •••, H n are provided for ex ⁇ tracting the signals stored in the capacitors 9d, 9b.
- Each bus bar comprises two lines 12d, 12b.
- bus bar line 12d is connected to the storage capacitors 9d of column lines 42], 4 2 (n+:), 4 2 (4n+:), ..., 4 2 ((r-i)n+:) by associated switches 13d 2: , 13d 2( n+:), 13d 2 (2n+ : ), ..., 13d 2 ( (r -i)n+:) •
- the assembly of switches 13 is referred to as a bus bar multiplexer 14
- the amplification/offset compensation block 6e is the first active circuitry in the readout path.
- the passive structure formed of bus bar multiplexer 14 and bus bars 11 has a drawback in that the amplitude of the output signals from the pixels is reduced due to charge distribution effects in the bus bars 11.
- C_storage is the capacity of a storage capacitor 9b, 9d
- C_parasitic is the parasitic capacity due to conductors such as busbar lines 12d, 12b and to busbar multiplexer switches 13, and
- C_ampin is the input capacitance of amplifier 16 : . It is desirable to make C_storage as large aas possible and C_parasitic as small as possible. Since the readout circuitry at each side of the pixel array 1 is only connected to one of every two column lines, sufficient space for the storage capacitors is available. Therefore, the capacity of the storage capacitors 9b, 9d can be made large with respect to the parasitic capacitance of the bus bar H 1 to which they are connected, of the multiplexer switches 12 and the input capacitance of switch capacitor amplifiers 15 : . C_storage is practically limited only by the driving capacity of each pixel 8 and by the time available for charging and discharging the storage capacitors, i.e. by the frame rate.
- each bus bar 12- can be as long as the x axis dimension of the pixel array 1, special care has to be taken to minimize the parasitic capacitance of each bus bar 12-,, of conductor lines 17 extending between the storage capacitors 9b, 9d and bus bars 11 and of conductor lines 18 extending form the bus bars 12-, to the ampli- fication/offset compensation block 6e .
- One way to minimize this parasitic capacitance is to enlarge the pitch of the bus bar lines 12b, 12d. Other measures will be discussed in detail later referring to Fig. 3 and 6.
- the block 6e has three main tasks, namely to amplify the pixel signals such that they optimally fit into the ADC 7 input range, secondly to drive the ADC input load with sufficient bandwidth to resolve sharp image contrasts, and, thirdly to avoid ADC kickback noise and contribute as little as possible to noise.
- the block 6e is divided into stages as described above.
- the parallel amplifiers 16 may have rather low bandwidth and can therefore achieve low noise levels. They provide the required amplification.
- the buffer 20 in front of the ADC 7 is responsible for the high speed demands. It is essential that the matching of the parallel amplifiers 16 : be perfect. This is why switch capacitor amplifiers with automatic offset compensation are preferably used as amplifiers 16 : .
- An offset of the buffer 20 is not included in the switch capacitor offset compensation. But this is not a problem, because it can be compensated by calibration on external pins or filtered out in digital signal processing, because there are only two buffers 20, one associated to the odd column lines 4o, the other associated to the even column lines 4e, which have to be adjusted to each other.
- the fast multiplexer 19 is responsible for combining the parallel outputs from the amplifiers 16 : into a single input signal for the ADC 7.
- FIG. 2 shows only one ADC 7 associated to the even column lines, it is obvious that two or more ADCs 7 (and multiplexers 19, buffers 20) may be provided, each of which handles part of the output signals from the amplifiers 15 ] .
- the multiplex transition from one amplifier output to the next is preferably as fast as the clocking speed of the ADC.
- bus bar fields There are two different kinds of bus bar fields, a regular one 21 in which conductor lines 17 coming from the storage capacitors intersect the bus bars 11, and a readout bus bar field 22, which comprises conductor lines 18 extending from the bus bar to the amplification/offset compensation block 6e .
- the readout bus bar field 22 is preferably located in the middle of the bus bars, because this results in lowest time constants and lowest time constant mismatches .
- Fig. 4A shows a regular bus bar field 21, Fig. 4B the readout bus bar field 22, and Fig. 4C illustrates the structure of an intersection between a bus bar 11 and conductor lines 17, 18.
- "sw” denotes a pair of multiplexer switches 13d : , 13b : , as illustrated in Fig. 4C, for establishing contact between bus bar lines 12b, 12d and conductor lines 17 or 18.
- the notation "d” and “b” means dark and bright and corresponds to the two storage capacitors 9d, 9b per column line 4e (4o) .
- the conductor lines 17 from the storage capacitors 9b, 9d are routed in the metal-1 layer surrounded by grounded metal-1 wires 23 to avoid horizontal cross coupling. Vertical cross coupling is avoided by shielding the conductor lines 17 by a grounded metal-2 conductor 24 on top of lines 17.
- the metal-3 layer is reserved for lines 12d, 12b of the bus bars 11.
- Each bus bar line 12b, 12d is surrounded by grounded metal-3 layer wires, not shown, to avoid cross coupling.
- Fig. 6 shows the layout of the readout bus bar field 22. It is identical to the regular bus bar field 21 in the metal layers 1 to 3.
- the conductor lines 18 are realized in metal-4 layer.
- the output signals are shielded by grounded metal-4-layer wires. It is important that the conductor lines 16 from the storage capacitors 9b, 9d provide exactly the same coupling in the regular bus bar field 21 as in readout bus bar field 22.
- the shielding by metal-2-layer conductors 24 is completely blocking the coupling of the conductor lines 17 to the output conductor lines 18 in the metal-4-layer.
- the width of the metal-2 shielding conductors 24 is optimized to avoid this coupling and to be as thin as possible to minimize parasitic capacitance.
- the parasitic capacitances of conductor lines 17 are essentially the same for all columns and will therefore not produce a mismatch.
- the above described architecture allows for designing an imager with high frame rates, high S/N ratio, high image quality, low power, using of the shelf IP components, in particular for the ADCs 7.
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Abstract
An image sensor circuit comprises a pixel cell array (1) having a plurality of pixel cells (8) arranged along a plurality of column lines (4o, 4e), a plurality of readout circuits (3e, 6e, 7; 3o, 6o, 7) connected to said column lines (4o, 4e), each of which comprises an analog-to-digital converter (7) and a multi- plexer (14; 19) for selectively applying an output signal of one of said column lines (4o, 4e) to said analog-to- digital converter (7). Between two of said column lines (41, 43,...) which are connected to a first one of said readout circuits (3o, 6o, 7) located at a first side of said pixel cell array (1), there is a column line (42, 44,...) which is connected to a second one (3e, 6e, 7) of said readout circuits located at a second side of said pixel cell array (1) opposite to said first side.
Description
Image Sensor Circuit
The present invention relates to image sensor circuits, in particular to CMOS image sensor circuits. Such circuits usually comprise a pixel cell array having a plurality of pixel cells arranged along a plurality of column lines, and readout circuitry connected to said column lines and comprising one or more analogue-to-digital converters for converting analogue output signal voltages representative of an amount of light received by one of said pixel cells into digital data.
EP 1 150 494 Bl discloses an image sensor circuit of this type, in which the readout circuitry comprises a multiplexer for selectively applying an output signal from one of the column lines to a common buffer amplifier. For converting the output signal from this buffer amplifier, a single analogue-to-digital converter (ADC) is required. Since there is only one ADC, it can be placed quite freely on a semiconductor substrate, and the size and shape of the area it occupies on the substrate is not subject to severe restrictions. When designing an image sensor circuit according to EP 1 150 494 Bl, development costs can be reduced by buying the ADC design off-the shelf from an IP provider. However, the ADC must have a very high bandwidth and therefore tends to be expensive.
On the other hand, WO 99/46851 discloses an image sensor circuit which comprises a pixel cell array having a plurality of pixel cells arranged along a plurality of column lines, and a plurality of readout circuits, each of
which is connected to two of said column lines and comprises an analogue-to-digital converter and a multiplexer for selectively applying an output signal of one of said two column lines to the converter. In this circuit, the ADCs may be much slower than the ADC according to the first-mentioned document, but instead there is a problem in that due to scattering of the characteristics of the readout circuits, an image obtained form this sensor circuit may present strip-shaped defects, and the space available for each readout circuit is limited. Specifically, since all readout circuits have to fit along an edge of the pixel cell array, the substrate space occupied by each of these tends to be rather long and narrow. Although the ADCs are simpler and, hence, cheaper in manufacture than that of EP 1 150 494 Bl, development costs are high, because an ADC which will fit into the available substrate space cannot be bought off-the-shelf and has to be designed specifically.
The object of the present invention is to provide an image sensor circuit which combines the advantages of the above mentioned prior art designs while avoiding their drawbacks .
This object is achieved by an image sensor circuit comprising a pixel cell array having a plurality of pixel cells arranged along a plurality of column lines, a plurality of readout circuits connected to said column lines, each of which comprises an analogue-to-digital converter and a multiplexer for selectively applying an output signal of one of said column lines to said analogue-to-digital converter, the circuit being characterized in that between two of said column lines connected
to a first one of said readout circuits located at a first side of said pixel cell array, there is a column line which is connected to a second one of said readout circuits located at a second side of said pixel cell ar- ray opposite to said first side. By splitting the readout circuitry in this way, space constraints are relieved.
If between any two columns connected to two adjacent inputs of said first readout circuit there is a column line connected to the second readout circuit, i.e. if column lines are associated alternately to the two readout circuits, the space available for the readout circuitry components associated to any given column line is practically doubled.
Preferably, each readout circuit comprises a plurality of bus bars, each bus bar having a subset of said column lines associated to it by switches located at intersections of the bus bar and of said associated column lines for selectively opening and closing an electrical connection between one of said associated column lines and said bus bar, wherein no two adjacent column lines are associated to a same bus bar.
The readout circuit further preferably comprises a plurality of amplifiers having an input connected to an associated one of said bus bars, and a multiplexer having inputs connected to outputs of said amplifiers. Using said bus bars, the amplifiers can be placed far apart from the pixel cell array, so that heat dissipated by the amplifiers does substantially not reach the pixel cell array. By keeping the pixel cell array cool, noise is reduced, and the image quality is improved.
In an such an image sensor, if the number of bus bars is n, it is preferred that among any n adjacent inputs of one of said readout circuits, there is one connected to each of said n bus bars. In this way, the column lines associated to a given bus bar are distributed all over the pixel cell array.
Each column line preferably extends across all of said bus bars in order to make the parasitic capacitance resulting from these crossings the same for all column lines and all bus bars.
Similarly, it is preferred that each amplifier is con- nected to its associated bus bar by a line extending across all of said bus bars.
It is further preferred that each column line has associated to it two storage capacitors and a switch for selec- tively connecting one of said two capacitors to said column line, and each bus bar comprises a first line for connecting to the first capacitor and a second line for connecting to the second capacitor.
By connecting the first and second lines of each bus bar to inputs of a differential amplifier, a difference between sampled voltages and said two capacitors can be formed prior to AD conversion, whereby the amount of samples to be AD converted is reduced.
In order to reduce parasitic capacities, in said readout circuit each column line is formed of a planar conductor defining a first plane and is shielded by at least one
grounded conductor which extends along said planar conductor in said first plane or in a second plane parallel to that first plane.
Similarly, each bus bar may comprise a planar conductor defining a second plane and may be shielded by at least one grounded conductor which extends along said planar conductor in said second plane or in a plane parallel to said second plane.
Further features and advantages of the invention will become apparent from the subsequent description of embodiments thereof referring to the appended drawings.
Fig. 1 is a schematic diagram illustrating the localization of components of an image sensor circuit according to the present invention on a circuit substrate.
Fig. 2 illustrates a detail of the circuit layout of
Fig. 1;
Fig. 3 illustrates the overall structure of the bus bars of the circuit of Fig. 1 ;
Fig. 4A, B are diagrams of bus bar fields;
Fig. 4C illustrates the structure of a switch in the bus bar fields of Fig. 4a, b;
Fig. 5 is a schematic perspective view of an intersection of conductors in the bus bar field of Fig. 4A; and
Fig. 6 is a view analogous to that of Fig. 5 of an intersection of conductors in the bus bar field of Fig. 4B.
Fig. 1 schematically illustrates the layout of an image sensor circuit according to the present invention. In the center of a semiconductor chip, there is a pixel array 1 comprising a large number of sensor pixels arranged in a pattern of rows and columns. The sensor pixels may be of any known type. They may e.g. be formed of conventional three-transistor circuits, which means that the sensor pixel itself has no storage capability. However, the architecture is not limited to this kind of pixels. It can be extended to pixels with larger numbers of transistors, which have storage associated to them and/or are capable of performing a global shutter operation. The size of the pixel array 1 is very large for HDTV applications, e. g. 1920 x 1080 pixels, which results in about 2 million pix- els in total. This means that the pixel array diagonal on the chip is easily reaching 10 mm or more, depending on the size of the individual pixels. This makes inter-pixel matching or alignment a major issue for imager design.
A vertical scanning circuit 2 provides signals for selecting pixels of array 1 for reset or readout row by row. All pixels in a same row of the array 1 have their outputs connected to a same column line. There are odd- numbered column lines 4o and even-numbered column lines 4e. According to the invention the circuitry for reading out the pixel array 1 has been divided into two blocks. One block is provided for reading out the even column lines 4e, the other block is provided for reading out the
odd column lines 4o. Both readout blocks are identical, one is placed in the layout on top of the pixel array 1, the other, at the bottom of it. Readout blocks include: column readout circuits 3o, 3e comprising a sampling storage block, bus bars and a bus bar multiplexer, an amplification/offset compensation block 6o, 6e comprising a plurality of amplifiers, an ADC multiplexer and a buffer, and an ADC 7.
Fig. 2 illustrates in more detail a section of the pixel array 1 and of the readout circuitry. The readout circuitry is illustrated for even-numbered column lines only, the readout circuitry for the odd-numbered lines is a specular image of that for the even-numbered lines and need not be specifically described. Fig. 2 shows twelve pixels 8 of pixel array 1 arranged in two rows and six columns. The pixels 8 have their outputs connected to odd column lines 4X, 43, ..., 42m-i and even column lines 42, 44, ..., 42m, respectively, 2m being the total number of column lines in pixel array 1.
Two storage capacitors 9d, 9b are connected to the end of each column line by a switch 10 near the border of pixel array 1. When the pixel array 1 is readout row by row un- der control of the vertical scanning circuit 2, the output voltage levels of dark pixels and of illuminated pixels alternate all the column lines. By means of the switch 10, an output voltage from a dark pixel is sampled and stored in storage capacitor 9d, whereas that of an illuminated pixel in an adjacent row is stored in capacitor 9b.
n parallel bus bars Hi, H2, •••, Hn are provided for ex¬ tracting the signals stored in the capacitors 9d, 9b. Each bus bar comprises two lines 12d, 12b. Line 12b of bus bar 11:, j=l, 2,..., n, is connected to the storage ca- pacitors 9b of column lines 42:, 42(n+:), 42(2n+:), •••, 42((r- Dn+]), r=m/n by associated switches 13b2:, 12b2(n+:), 13b2(2n+:), •••' 13b2< (r-i)n+:) • Similarly, bus bar line 12d is connected to the storage capacitors 9d of column lines 42], 42(n+:), 42(4n+:), ..., 42((r-i)n+:) by associated switches 13d2:, 13d2(n+:), 13d2(2n+:), ..., 13d2 ( (r-i)n+:) • The assembly of switches 13 is referred to as a bus bar multiplexer 14
The amplification/offset compensation block 6e comprises n switch capacitor amplifiers 16:, j=l, ..., n, each of which is associated to one bus bar H1 and has two inputs connected to its lines 12d, 12b, an ADC multiplexer 19 having its inputs connected to the outputs of switch capacitor amplifiers 16:, and a buffer 20, the output of which is connected to ADC 7
The amplification/offset compensation block 6e is the first active circuitry in the readout path. In principle, the passive structure formed of bus bar multiplexer 14 and bus bars 11 has a drawback in that the amplitude of the output signals from the pixels is reduced due to charge distribution effects in the bus bars 11. Charge distribution effects have an influence on the gain of the switch capacitor amplifiers 16:. namely, this gain is given by: Gain=C_storage/ (C_storage+C_parasitic+C_ampin) , wherein
C_storage is the capacity of a storage capacitor 9b, 9d,
C_parasitic is the parasitic capacity due to conductors such as busbar lines 12d, 12b and to busbar multiplexer switches 13, and
C_ampin is the input capacitance of amplifier 16:. It is desirable to make C_storage as large aas possible and C_parasitic as small as possible. Since the readout circuitry at each side of the pixel array 1 is only connected to one of every two column lines, sufficient space for the storage capacitors is available. Therefore, the capacity of the storage capacitors 9b, 9d can be made large with respect to the parasitic capacitance of the bus bar H1 to which they are connected, of the multiplexer switches 12 and the input capacitance of switch capacitor amplifiers 15:. C_storage is practically limited only by the driving capacity of each pixel 8 and by the time available for charging and discharging the storage capacitors, i.e. by the frame rate.
Since the length of each bus bar 12-, can be as long as the x axis dimension of the pixel array 1, special care has to be taken to minimize the parasitic capacitance of each bus bar 12-,, of conductor lines 17 extending between the storage capacitors 9b, 9d and bus bars 11 and of conductor lines 18 extending form the bus bars 12-, to the ampli- fication/offset compensation block 6e . One way to minimize this parasitic capacitance is to enlarge the pitch of the bus bar lines 12b, 12d. Other measures will be discussed in detail later referring to Fig. 3 and 6.
The block 6e has three main tasks, namely to amplify the pixel signals such that they optimally fit into the ADC 7 input range, secondly to drive the ADC input load with sufficient bandwidth to resolve sharp image contrasts,
and, thirdly to avoid ADC kickback noise and contribute as little as possible to noise. In order to satisfy these requirements, the block 6e is divided into stages as described above. The parallel amplifiers 16: may have rather low bandwidth and can therefore achieve low noise levels. They provide the required amplification. The buffer 20 in front of the ADC 7 is responsible for the high speed demands. It is essential that the matching of the parallel amplifiers 16: be perfect. This is why switch capacitor amplifiers with automatic offset compensation are preferably used as amplifiers 16:. An offset of the buffer 20 is not included in the switch capacitor offset compensation. But this is not a problem, because it can be compensated by calibration on external pins or filtered out in digital signal processing, because there are only two buffers 20, one associated to the odd column lines 4o, the other associated to the even column lines 4e, which have to be adjusted to each other. The fast multiplexer 19 is responsible for combining the parallel outputs from the amplifiers 16: into a single input signal for the ADC 7.
Although Fig. 2 shows only one ADC 7 associated to the even column lines, it is obvious that two or more ADCs 7 (and multiplexers 19, buffers 20) may be provided, each of which handles part of the output signals from the amplifiers 15]. The multiplex transition from one amplifier output to the next is preferably as fast as the clocking speed of the ADC.
The bus bar array may be regarded as formed of r=m/n bus bar fields 21, 22, each field being associated to n adjacent even (or odd) column lines 4e (4o) . There are two
different kinds of bus bar fields, a regular one 21 in which conductor lines 17 coming from the storage capacitors intersect the bus bars 11, and a readout bus bar field 22, which comprises conductor lines 18 extending from the bus bar to the amplification/offset compensation block 6e . The readout bus bar field 22 is preferably located in the middle of the bus bars, because this results in lowest time constants and lowest time constant mismatches .
The design of the bus bar fields 21, 22 is shown in Figs 4A to 4C. Fig. 4A shows a regular bus bar field 21, Fig. 4B the readout bus bar field 22, and Fig. 4C illustrates the structure of an intersection between a bus bar 11 and conductor lines 17, 18. In Fig. 4a and b, "sw" denotes a pair of multiplexer switches 13d:, 13b:, as illustrated in Fig. 4C, for establishing contact between bus bar lines 12b, 12d and conductor lines 17 or 18. The notation "d" and "b" means dark and bright and corresponds to the two storage capacitors 9d, 9b per column line 4e (4o) . It should be noted that in the regular bus bar field 21, all conductor lines 17 extend across all bus bars 11, so that the number of intersections is the same for every bus bar Hi to Hn- Accordingly, the parasitic capacitance C_parasitic is the same for all bus bars 12-,, j=l, 2, ..., n. The multiplexer switches 13d:, 13b: are placed exactly at the location where the conductor lines 17 from the storage capacitors cross the bus bars. This eliminates all parasitic wire capacitances of the wire connections from bus bar connection point and multiplexer switch.
Figs. 5 and 6 show details of an intersection of the regular bus bar field 21 and the readout bus bar field 22, respectively, in perspective views.
In the regular bus bar field 21 of Fig. 5, the conductor lines 17 from the storage capacitors 9b, 9d are routed in the metal-1 layer surrounded by grounded metal-1 wires 23 to avoid horizontal cross coupling. Vertical cross coupling is avoided by shielding the conductor lines 17 by a grounded metal-2 conductor 24 on top of lines 17. The metal-3 layer is reserved for lines 12d, 12b of the bus bars 11.
Each bus bar line 12b, 12d is surrounded by grounded metal-3 layer wires, not shown, to avoid cross coupling.
Fig. 6 shows the layout of the readout bus bar field 22. It is identical to the regular bus bar field 21 in the metal layers 1 to 3. The conductor lines 18 are realized in metal-4 layer. Also here the output signals are shielded by grounded metal-4-layer wires. It is important that the conductor lines 16 from the storage capacitors 9b, 9d provide exactly the same coupling in the regular bus bar field 21 as in readout bus bar field 22. The shielding by metal-2-layer conductors 24 is completely blocking the coupling of the conductor lines 17 to the output conductor lines 18 in the metal-4-layer. The width of the metal-2 shielding conductors 24 is optimized to avoid this coupling and to be as thin as possible to minimize parasitic capacitance. The parasitic capacitances of conductor lines 17 are essentially the same for all columns and will therefore not produce a mismatch.
The above described architecture allows for designing an imager with high frame rates, high S/N ratio, high image quality, low power, using of the shelf IP components, in particular for the ADCs 7.
Claims
1. An image sensor circuit comprising a pixel cell array (1) having a plurality of pixel cells (8) arranged along a plurality of column lines
(4o, 4e), a plurality of readout circuits (3e, 6e, 7; 3o, 6o,
7) connected to said column lines (4o, 4e) , each of which comprises an analog-to-digital converter (7) and a multiplexer (14; 19) for selectively applying an output signal of one of said column lines (4o, 4e) to said analog-to-digital converter (7); characterized in that between two of said column lines (4X, 43, ...) which are connected to a first one of said readout circuits (3o, 6o, 7) located at a first side of said pixel cell array (1), there is a column line (42, 44, ...) which is connected to a second one (3e, 6e, 7) of said readout circuits located at a second side of said pixel cell array (1) opposite to said first side .
2. The image sensor of claim 1, wherein between any two column lines (4i, 43, ...) connected to two adjacent inputs of said first readout circuit (3o, 6o, 7) there is a column line (42, 44, ...) connected to the second readout circuit (3e, 6e, 7) .
3. The image sensor of claim 1 or 2, wherein each read- out circuit (3e, 6e, 7; 3o, 6o, 7) comprises a plurality of busbars (Hi, H2, •••, Hn), each busbar having a subset of said column lines (4o, 4e) associated to it by switches (13b, 13d) located at in- tersections of the busbars (Hi, H2, •••, Hn) and of said associated column lines (16) for selectively opening and closing an electrical connection between one of said column lines (17) and said busbars, no two adjacent column lines being associated to a same busbar .
4. The image sensor of claim 3, wherein the readout circuit comprises a plurality of amplifiers (I61, I62, ..., 16n) having an input connected to an associ¬ ated one of said busbars (Hi, H2, •••, Hn), and a multiplexer (19) having inputs connected to outputs of said amplifiers (I61, I62, ..., 16n).
6. The image sensor of claim 5, wherein each column line (17) extends across all of said busbars.
7. The image sensor of any of claims 5 to 7, wherein each amplifier (I61, I62, ..., 16n) is connected to its associated busbar (Hi, H2, ..., Hn) by a line (18) extending across all of said busbars.
8. The image sensor of any of the claims 3 to 7, wherein each column line (4o, 4e) has associated to it two storage capacitors (9b, 9d) and a switch (10) for selectively connecting one of said two capacitors to the column line, and each busbar (Hi, H2,
..., Hn) comprises a first line (12b) for connecting to the first capacitor (9b) and a second line (12d) for connecting to the second capacitor (9d) .
9. The image sensor of claim 4 and claim 8, wherein the amplifiers (16i, I62, ..., 16n) are differential ampli¬ fiers having their inputs connected to the first and second lines (12b, 12d) of their associated busbar.
10. The image sensor of any of the preceding claims, wherein in said readout circuit at least part of each column line is formed of a planar conductor
(17) defining a first plane and is shielded by at least one grounded conductor (23, 24) which extends along said planar conductor (17) in said first plane or in a second plane parallel to said first plane.
11. The image sensor of claim 3, wherein each busbar
(Hi, H2, -r Hn) comprises a planar conductor (12d, 12b) defining a second plane and is shielded by at least one grounded conductor which extends along said planar conductor in said second plane or in a plane parallel to said second plane.
Priority Applications (2)
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EP07729407.2A EP2022253B1 (en) | 2006-05-23 | 2007-05-22 | Image sensor circuit |
US12/227,677 US8102442B2 (en) | 2006-05-23 | 2007-05-22 | Image sensor circuit |
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EP06300510.2 | 2006-05-23 | ||
EP06300510 | 2006-05-23 |
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PCT/EP2007/054968 WO2007135158A1 (en) | 2006-05-23 | 2007-05-22 | Image sensor circuit |
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US (1) | US8102442B2 (en) |
EP (1) | EP2022253B1 (en) |
WO (1) | WO2007135158A1 (en) |
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WO2011078970A1 (en) | 2009-12-22 | 2011-06-30 | Omnivision Technologies, Inc. | Column output circuits for image sensors |
DE102011120099A1 (en) * | 2011-12-02 | 2013-06-06 | Arnold & Richter Cine Technik Gmbh & Co. Betriebs Kg | Image sensor and method for reading an image sensor |
KR101543674B1 (en) * | 2009-01-13 | 2015-08-11 | 삼성전자주식회사 | - - Image sensor for reducing kick-back noise and image pick-up device having the same |
TWI497909B (en) * | 2008-12-08 | 2015-08-21 | Omnivision Tech Inc | Analog multiplexer configured to reduce kickback perturbation |
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CN103609097A (en) * | 2012-03-13 | 2014-02-26 | 奥林巴斯医疗株式会社 | Signal processing device for solid state image pick-up device and solid state image pick-up device |
US9521349B2 (en) * | 2014-06-19 | 2016-12-13 | Rambus Inc. | Image sensor architecture with power saving readout |
GB2606047B (en) | 2017-09-29 | 2023-02-15 | Canon Kk | Image sensor and image capturing apparatus |
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EP2022253A1 (en) | 2009-02-11 |
US20090237542A1 (en) | 2009-09-24 |
US8102442B2 (en) | 2012-01-24 |
EP2022253B1 (en) | 2015-11-04 |
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