WO2002080529A1 - Diversity combiner for reception of digital television signals - Google Patents
Diversity combiner for reception of digital television signals Download PDFInfo
- Publication number
- WO2002080529A1 WO2002080529A1 PCT/IB2002/001041 IB0201041W WO02080529A1 WO 2002080529 A1 WO2002080529 A1 WO 2002080529A1 IB 0201041 W IB0201041 W IB 0201041W WO 02080529 A1 WO02080529 A1 WO 02080529A1
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- Prior art keywords
- signal
- signals
- receiver
- digital
- output signal
- Prior art date
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- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000872 buffer Substances 0.000 claims description 29
- 230000015654 memory Effects 0.000 claims description 25
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 3
- 230000004044 response Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 101000630267 Homo sapiens Probable glutamate-tRNA ligase, mitochondrial Proteins 0.000 description 2
- 102100026125 Probable glutamate-tRNA ligase, mitochondrial Human genes 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 241000724202 Maize stripe tenuivirus Species 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
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- 238000012360 testing method Methods 0.000 description 1
- 238000012549 training Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
- H04B7/0837—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station using pre-detection combining
- H04B7/0842—Weighted combining
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/08—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
- H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream
- H04N21/4263—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
- H04N21/44004—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving video buffer management, e.g. video decoder buffer or video display buffer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/442—Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed, the storage space available from the internal hard disk
- H04N21/44209—Monitoring of downstream path of the transmission network originating from a server, e.g. bandwidth variations of a wireless network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
Definitions
- the present invention is directed, in general, to antenna systems and signal receivers and, more specifically, to an apparatus for and method of improving the reception of signals such as digital television signals used in digital terrestrial televisions.
- SDTV Standard Definition Television
- HDTV High Definition Television
- ATSC Advanced Television Standards Committee
- HDTV standard images allow up to 6 times the resolution of analog television images and up to a full 60 frames per second temporal resolution which is twice the current NTSC resolution. Motion is seen smooth and the picture is clear enough to sit very close to a very large screen. The picture is displayed in a panoramic 16:9 horizontal- to-vertical aspect ratio to be more like movies and add the feeling of realism to TV.
- An HDTV video signal contains almost four to five times the data of an NTSC image.
- the present invention which addresses the needs of the prior art provides an apparatus which includes at least two first receiver chips each associated with an antenna, each chip having a front-end section, equalizer, and a back-end section; a digital combiner circuit for receiving signals from said chips, the digital combiner circuit having at least two first buffer memories, at least two second buffer memories, and a clock synchronizing module, with each buffer memory generating an output signal; a common bus coupled to the first receiver chips and the digital combiner circuit; the clock synchronizing module capable of generating a delay signal and aligning the output signal of each buffer memory based on a common clock; the digital combiner circuit capable of generating a combined output signal; and a single second receiver chip for receiving the combined output signal of the digital combiner circuit, the second receiver chip comprising a front-end section, equalizer and a back-end section.
- a method in another embodiment, includes receiving first and second signals from the first and second antennae in the first receiver chips; processing the signals in a digital combiner circuit that includes first and second buffer memories and a clock synchronizing module, so as to generate a delay signal that synchronizes and combines output signals from the buffer memories to generate a combined output signal; and feeding the combined output signal to a single second receiver chip.
- Fig. 1 is a block diagram of a signal receiver apparatus in accordance with prior art
- Fig. 2 is a block diagram of an illustrative embodiment of a signal receiver apparatus in accordance with one embodiment of the present invention
- Fig. 3 is a block diagram illustrating communications among the receivers in the apparatus of Fig. 2 in accordance with one embodiment of the present invention
- Fig. 4 is flow diagram illustrating maximum ratio combining algorithm utilized in one embodiment of the present invention.
- a typical signal receiver system comprises an antenna 1 for receiving a television signal coupled to a tuner 5 which receives an intermediate frequency (IF) signal 2 and down-converts the signal to a low IF signal 3.
- IF intermediate frequency
- the standard IF signal is a 44Mhz signal and the low IF signal is a signal of less than lOMhz.
- ADC analog to digital converter
- a receiver chip 15 comprising a front-end section (FE) 16, equalizer (EQ) 17 and a back-end section (BE) 18, receives the digital signal 4 and processes the signal in all three sections.
- the receiver chip 15 is preferably an ATSC A/53 compliant chip, which means that it is capable of receiving an 8-VSB signal, an 8 level ( ⁇ 1, ⁇ 3, ⁇ 5, +7 ⁇ ) VSB signal broadcasted in a terrestrial broadcast mode over the same 6 MHz channel currently used by the analog NTSC television system.
- the number and letters 8-VSB refer to a television signal modulation format in which the television signal has eight vestigial sidebands.
- a typical standard symbol rate is 10.76MHz.
- multiple, and at least two, ATSC A/53 compliant DTV receiver chips 15 A, 15B and 15C are combined on one board to act as a diversity combiner receiver that will improve receiver performance for digital terrestrial TV.
- antennae 1 A and IB receive two different IF signals 2A-2B, which are passed to tuners 5A-5B.
- An I 2 C bus 30A is electrically coupled to integrated chip (IC) boards 20A-20B and establishes communication between the tuners 5A-5B.
- the tuners 5A-5B are then tuned to the same channel through the I 2 C bus 30A, which is controlled and programmable by a computer (not shown).
- the bus 30A may be controlled by a television set.
- the tuners 5A-5B must be receiving the same signal.
- the computer will typically have standard communications software installed for controlling the I C bus 30 A.
- the tuners 5A-5B down-convert the IF signals 2A-2B to low IF signals 3A-3B, which are then converted into digital signals 4A-4B by analog to digital converters 10A-10B, respectively.
- the receiver chips 15A-15B receive the digital signals 4A-4B at the front-end sections 16A-16B and process the signals in the front-end section 16A-16B and the equalizer 17A-17B. As illustrated in Fig. 3, the back-end section 18A-18B is not used.
- the front-end section of the receiver chip is typically utilized for timing recovery purposes, while the equalizer is utilized as a demodulator for removing interferences and echoes.
- the back-end section is utilized as a decoder, in particular for forward error correction (FEC) processing.
- FEC forward error correction
- a digital combiner circuit 25 is a field programmable gate array (FPGA).
- the digital combiner circuit 25 may be a digital signal processor (DSP) or software run on a computer.
- Sync outputs 33 A- 33B are fed into a correlator 50 of a clock synchronizing module 85.
- Sync outputs 33A-33B indicate when the segment sync is to arrive.
- the segment sync is transmitted vertically in a standard ATSC signal. Based on these sync outputs, correlator 50 generates a delay signal 45 which is a time difference between the two signals 4A-4B.
- the signal on channel 1 might arrive 0.1 microseconds before the signal on channel 2, i.e. antenna 1A receives the signal earlier than the antenna IB.
- the correlator 50 typically acts as a subtractor, which calculates the time difference between the two sync signals, i.e. the correlator 50 notifies the digital combiner 25 of the offset in time between the two data streams and hence what the delay 45 is on one of the streams for the buffer memory 35.
- the correlator 50 then averages the offset over multiple sync signals.
- the correlator 50 also generates a synchronization output signal 52, which is fed into the symbol clock selector 55.
- the synchronization output signal 52 notifies the system where the data stream is within the ATSC structure.
- the receiver chips 15A-15B also generate lock signals 34A-34B, which represent the existence of the signals 4A-4B or lack thereof, i.e. the lock signals indicate whether the signal has been acquired.
- the other outputs of the receiver chips 15A-15B are equalizer outputs 41A-41B and symbol strobe outputs 42A-42B, which act as inputs to buffer memories 35 and 40.
- the lock signals 34A-34B and symbol strobe signals 42A-42B are then fed into a symbol clock selector 55.
- the symbol strobe signals 42A-42B preferably, operate at a frequency of 10.76MHz.
- symbol clock selector 55 In response to the inputs 34A-34B and 42A-42B, symbol clock selector 55 generates a symbol strobe output 60, which is selected as a common clock of the system illustrated in Fig. 2.
- the first memory buffer is preferably a first-in first-out memory (FIFO) 35. This means that the data written into the buffer first, comes out first.
- the second memory buffer is preferably a random access memory (RAM) 40.
- the FIFO 35 is preferably implemented with hardware, however, an alternative implementation with software is also possible.
- the FIFO 35 receives the equalizer output signal 41 A and the symbol strobe signal 42A. So the equalizer output signal 41 A is written into the FIFO 35 based on the symbol strobe 42 A.
- the two incoming 10.76MHz symbol streams are aligned such that each symbol is added to the respective symbol from the other stream. It is expected that no more than 1-2 symbols variation ( ⁇ 200ns) will exist between each path.
- a relatively short FIFO may be used.
- a 4 symbol in length FIFO may be used.
- the respective field synchronization outputs can be used to align the symbol streams.
- the field synchronization outputs are part of the standard ATSC signal.
- the ATSC standard has data structured in fields - for every 312 segments of data, there is one segment called a field sync to create the complete ATSC field. This field sync can be used to align the data streams.
- the symbol clock selector 55 selects the symbol strobe 42 A or 42B and generates the symbol strobe output signal 60.
- the delay signal 45 generated by the correlator 50 is also fed into the FIFO 35.
- the FIFO 35 delays the signal 41 A so that the buffer output signals 74A-74B are exactly synchronized and arrive at points 75 A and 75B at the same time.
- the FIFO is typically measured in terms of depth, which represents the length of the FIFO. In a preferred embodiment, the length of the FIFO is equal to the delay. For example, the FIFO of 8 x 16 (8 bits per symbol with a 16 symbol array in length) may be used.
- the buffer output signals are read out at the same time based on the symbol strobe output 60, which is fed into each buffer 35 and 40 from the symbol clock selector 55.
- the receiver chips 15A-15B also generate a signal quality indicator (SQI) output (not shown).
- An I 2 C bus 30B which is electrically coupled to receiver chips 15A-15B has an input and an output.
- the I 2 C bus 30B reads the SQI output out of the receiver chips 15A-15B.
- the SQI value is typically generated in software run on the computer (not shown).
- the standard ATSC signal has a frame sync transmitted horizontally and a segment sync transmitted vertically. The frame sync acts as a training signal; once it arrives the entire signal following it becomes apparent. The anticipated signal is then compared to what has actually arrived and on the basis of the comparison, SNR (signal-to-noise ratio) is generated within each receiver chip.
- SQI is derived from the SNR.
- An I 2 C bus 30C is electrically coupled to the digital combiner circuit 25, and in particular to an interface module 65, which applies weighting factors K and 1-K to the buffer output signals 74A-74B.
- the weighting factors are ⁇ determined using a maximum ratio combining algorithm illustrated in Fig. 4.
- SQI represents the quality of the signal.
- mean squared error MSE
- other functions of measuring an error in a signal may be used.
- a known field sync arrives every 24 milliseconds as a part of a standard ATSC signal. The field sync is known beforehand because, based on the symbol strobe signals 42A-42B and the sync clock signals 33 A-33B, the exact position in the frame is known. Therefore, since a standard frame is known to be 832 by 313 symbols, the exact time when the next frame will arrive is known.
- the field sync is compared to what has actually arrived and from this comparison the MSE is calculated. Performing the same procedure for each channel for multiple field syncs and averaging out the MSEs produces an average MSE, which is the SQI. The lower the MSE on a channel, the better the signal quality. The reverse is also true: the higher the MSE, the worse the signal quality is.
- the above described procedure of determining the quality of a signal is executed. If only the signal at channel 1 is good, and the signal at channel 2 is not to be used, the weighting factor K is set to zero at step A 10. If only the signal at channel 2 is good, the weighting factor K is set to one at step A20. If the signals are good at both channels, they are combined intelligently by an adder 70 at step A15, wherein K is set to:
- the combined output signal 77 is then fed into a receiver chip 15C. In particular, as illustrated in Fig. 3, the signal 77 is fed only into the back-end section 18C, preferably a forward error correction (FEC) unit, for decoding purposes.
- the output of the back-end section 18C is a desired digital signal 80. This combined signal 80 is of a significantly better quality than a signal 13 illustrated in Fig.
- the receiver according to the present invention reduces the probability that the receiver lies in a low field strength area. For example, with n antennae there is n times less chance of being in a field null. Also, the reduced threshold of visibility helps reduce the effect of lower field strength.
- more than two antennae with more than two parallel receiver chains associated with the antennae may be implemented. This will result in a more complex and expensive system than the two antenna system, as those of ordinary skill in the art will appreciate.
- the digital combiner circuit will become more complex, in particular, and multiple buffer memories will need to be used. For example, for n receiver chains there will need to be (n-1) FIFOs and (n-1) RAMs for n>2. However, only one decoder in a single receiver chip and one clock synchronizing module as in the preferred embodiment will be used.
- the apparatus and method of the present invention is not limited to improving only a television signal.
- Those skilled in the art will readily understand that the principles of the present invention may also be successfully applied to other types of signals.
- the terms used herein should be read as terms of description rather than of limitation, as those of skill in the art with this specification before them will be able to make modifications therein without departing from the spirit of the invention.
- Other embodiments beyond those here discussed are within the spirit and scope of the appended claims.
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Abstract
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002577404A JP2004523983A (en) | 2001-03-29 | 2002-03-28 | Diversity synthesizer for receiving digital television signals |
EP02713137A EP1374569A1 (en) | 2001-03-29 | 2002-03-28 | Diversity combiner for reception of digital television signals |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/820,594 US20020150185A1 (en) | 2001-03-29 | 2001-03-29 | Diversity combiner for reception of digital television signals |
US09/820,594 | 2001-03-29 |
Publications (1)
Publication Number | Publication Date |
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WO2002080529A1 true WO2002080529A1 (en) | 2002-10-10 |
Family
ID=25231244
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2002/001041 WO2002080529A1 (en) | 2001-03-29 | 2002-03-28 | Diversity combiner for reception of digital television signals |
Country Status (6)
Country | Link |
---|---|
US (1) | US20020150185A1 (en) |
EP (1) | EP1374569A1 (en) |
JP (1) | JP2004523983A (en) |
KR (1) | KR20030007784A (en) |
CN (1) | CN1460359A (en) |
WO (1) | WO2002080529A1 (en) |
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- 2002-03-28 JP JP2002577404A patent/JP2004523983A/en not_active Withdrawn
- 2002-03-28 WO PCT/IB2002/001041 patent/WO2002080529A1/en not_active Application Discontinuation
- 2002-03-28 CN CN02800836A patent/CN1460359A/en active Pending
- 2002-03-28 KR KR1020027016286A patent/KR20030007784A/en not_active Application Discontinuation
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Also Published As
Publication number | Publication date |
---|---|
US20020150185A1 (en) | 2002-10-17 |
CN1460359A (en) | 2003-12-03 |
KR20030007784A (en) | 2003-01-23 |
JP2004523983A (en) | 2004-08-05 |
EP1374569A1 (en) | 2004-01-02 |
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