WO2001037148A1 - Systeme de conception lsi a base ip et procede de conception associe - Google Patents
Systeme de conception lsi a base ip et procede de conception associe Download PDFInfo
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- WO2001037148A1 WO2001037148A1 PCT/JP2000/007869 JP0007869W WO0137148A1 WO 2001037148 A1 WO2001037148 A1 WO 2001037148A1 JP 0007869 W JP0007869 W JP 0007869W WO 0137148 A1 WO0137148 A1 WO 0137148A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
Definitions
- the present invention belongs to a technology related to a so-called IP-based LSI design. Background art
- integrated circuit devices in electronic devices have been configured such that individual LSIs of various types, such as a memory and a processor, are formed on a semiconductor chip, and then each chip is mounted on a motherboard such as a printed wiring board. It has been manufactured by
- system-on-chip in which a memory and various logic circuits are provided on a single chip.
- process technology for forming elements with different structures on a common substrate is required, and major changes are required in the design technology.
- IP IP-based method of designing a desired system LSI by combining blocks.
- each function block has already performed its function. Since the configuration for realizing this is specified, the design of the integrated circuit device only requires the design of the wiring between the function blocks and the peripheral circuits. Such a design technique can greatly improve the design efficiency.
- An object of the present invention is to reduce design man-hours and improve design efficiency in an IP-based LSI design.
- the present invention provides, as an IP-based LSI design system, an IP database having a system-level IP used in system-level design.
- a processing algorithm description section that describes the processing algorithm of the input data
- an input data structure definition section that indicates the structure definition of the input data that is the processing unit
- an output data structure definition section that indicates the structure definition of the output data that is the processing unit It is described separately.
- the IP-based LSI design system When providing a communication channel between system-level IPs for performing data communication in an architectural design or a functional design, the IP-based LSI design system performs communication between the communication channel and each system-level IP.
- the conversion circuit generating means searches the IP database when providing a communication channel between the first and second system-level IPs for performing communication, and outputs the output of the first system-level IP. It is preferable that the description of the data structure definition unit and the description of the input data structure definition unit of the second system level IP be read, and a conversion circuit be generated based on the read description.
- the IP database further has a communication channel IP, and the conversion circuit generating means, when providing the communication channel between the first and second system level IPs, — It is preferable to search the evening base and further read the input / output data structure definition of the IP of the communication channel.
- the conversion circuit generation unit receives the information indicating the correspondence between the input / output data structures and generates the conversion circuit. Is preferred. Further, it is preferable that the conversion circuit converts a data amount per unit for performing communication. Alternatively, it is preferable that the conversion circuit performs conversion between the address data indicating the data area and the actual data corresponding to the address data.
- the present invention uses an IP database having system-level IPs used in system-level design as an IP-based LSI design method. In the system-level IP, each IP describes a processing algorithm of the IP. A processing algorithm description section, an input data structure definition section representing the structure definition of the input data serving as a processing unit, and an output data structure definition section representing the structure definition of the output data serving as the processing unit. Is what it is.
- the IP-based LSI design method is used for providing communication between the communication channel and each system-level IP when providing a communication channel between system-level IPs for performing data communication in an architectural design or a functional design. It is preferable that the method further comprises a step of generating a conversion circuit for performing the data conversion. Further, the conversion circuit generating step searches the IP database when providing a communication channel between the first and second system-level IPs that perform communication, and outputs the output data of the first system-level IP. It is preferable to read the description of the input data structure definition part of the configuration definition part and the input data structure definition part of the second system level IP, and to generate a conversion circuit based on the read description.
- the IP database further includes an IP of a communication channel
- the conversion circuit generation step includes the step of: providing the communication channel between the first and second system-level IPs; It is preferable to search the database and further read the input / output data structure definition of the IP of the communication channel.
- the conversion circuit generation step generates the conversion circuit by receiving information indicating a correspondence between the input / output data structures. Is preferred.
- the conversion circuit converts a data amount per unit for performing communication.
- the conversion circuit preferably performs conversion between an address data indicating a data area and actual data corresponding to the address data.
- the present invention also provides, as an IP-based LSI design system, a function classification database in which device configurations are classified into elements in terms of functions and systematized, and an IP-based LSI design is performed using the function classification database. Is what you do.
- the IP-based LSI design system includes an existing design asset database in which each generated IP is stored in association with each element in the function classification database, and selects an IP suitable for an LSI to be designed. It is preferable to select from each IP stored in the existing design asset data base while referring to the function classification database.
- the IP-based LSI design system is designed to be compatible with design assets in which information defining mutual compatibility of each IP stored in the existing design asset database is stored. It is preferable to provide a performance evaluation rule database and evaluate the suitability of the selected IP for the LSI to be designed with reference to the compatibility evaluation rule database between design assets. Alternatively, the IP-based LSI design system selects an IP having a function similar to the IP suitable for the LSI to be designed from each of the IPs stored in the existing design asset database, and assigns the function of the selected IP to the LSI to be designed.
- the existing design asset database includes means for managing history information such as a parent IP for each IP to be stored and a difference from the parent IP. Is preferred.
- the present invention as an IP-based LSI design method, performs an IP-based LSI design using a functional classification database in which a device configuration is classified into elements in terms of functions and systematized.
- the IP-based LSI design method uses an existing design asset database in which each generated IP is stored in association with each element in the function classification database, and is suitable for the LSI to be designed. It is preferable to select an IP from each IP stored in the existing design asset database with reference to the function classification database.
- the IP-based LSI design method uses a design asset compatibility evaluation rule database that stores information defining compatibility between the respective IPs stored in the existing design asset database, and It is preferable to evaluate the suitability of the selected IP for the above LSI by referring to the compatibility evaluation rule database between design assets.
- the IP-based LSI design method includes selecting an IP having a function similar to an IP suitable for the LSI to be designed from each IP stored in the existing design asset database, and selecting a function of the selected IP from the design target. It is preferable to modify it so that it is suitable for LSI.
- the present invention also provides an IP-based LSI design system, a means for generating architectural-level design data from a system-level function definition for an LSI to be designed, and a method for generating the generated architectural-level design data and the design object.
- a means for performing an operation analysis of the LSI to be designed using an operation pattern definition of the LSI, and a means for generating a power control block in the architecture-level design data based on the operation analysis result It is.
- the present invention provides, as an IP-based LSI design method, a step of generating architecture-level design data from a system-level function definition, the generated architecture-level design data, and an operation pattern definition of the design target LSI.
- FIG. 1 is a diagram conceptually showing an IP-based LSI design.
- Figures 2 (a) and 2 (b) schematically show the conversion from the system level to the architecture level or function level.
- FIG. 3 is a diagram showing an example of a configuration of a main part of the IP-based LSI design system according to the first embodiment of the present invention.
- FIGS. 4A and 4B are diagrams showing an example of the generated data conversion circuit.
- FIG. 5 is a diagram showing another example of the data conversion circuit.
- FIG. 6 is a diagram showing another example of the data conversion circuit.
- FIG. 7 is a diagram schematically showing the conversion from the system level to the architecture level or the function level when the data structure is changed between IPs.
- FIG. 8 is a main part of the IP-based LSI design system according to the first embodiment of the present invention.
- FIG. 3 is a diagram showing an example of the configuration of FIG.
- FIG. 9 is a diagram showing an example of the generated data conversion circuit.
- FIG. 10 is a diagram showing a configuration of an IP-based LSI design system according to the second embodiment of the present invention.
- FIG. 11 is a diagram showing an example of the contents of the function classification DB.
- FIG. 12 is a diagram showing an example of input data obtained by referring to the function classification DB.
- FIG. 13 is a diagram showing an example of the contents of the existing design asset DB.
- Figure 14 shows an example of IP information included in the existing design DB.
- FIG. 15 is a diagram showing an example of the contents of the compatibility evaluation rule DB between design assets.
- FIG. 16 is a diagram showing a configuration of an IP-based LSI design system according to the third embodiment of the present invention.
- FIG. 17 is a diagram showing an example of the operation analysis result. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 1 is a diagram conceptually showing an IP-based LSI design.
- IP-based LSI design is performed hierarchically as system-level design S11, architecture design S12, functional design S13, logical design S14, and layout design S15. Is done. Then, in the system level design S11, architecture design S12, and function design S13, which are the upstream processes, the IP database 1 that stores so-called IP used for LSI design is used. You.
- One day 1 includes, for each IP, a system-level IP 11 with system-level information, a behavioral IP 12 with architecture-level information, and an RTLIP 13a with function-level information.
- software IP 13 b is stored in association with each.
- system level design S 1 1 The system level IP 11 is reused, the architecture design S 12 searches for the behavior IP 12 corresponding to the reused system level IP 11 via the interface 15, and the functional design S 13 re-uses it.
- RTLIP 13 a or software IP 13 b corresponding to the used system level IP 11 is searched through the interface 15.
- Figure 2 is a diagram schematically showing the conversion from the system level to the architecture level or function level.
- Fig. 2 (a) in system level design, reuse design is performed using system level IPA and IPB.
- Fig. 2 (b) in architecture design or functional design, system level I PA and IPB are used.
- the lower IP (RT LI PA, IPB in the figure) corresponding to PA, IPB is searched from the IP database and reused.
- a data conversion circuit 2 for properly connecting the input / output of the RT LI PA, IPB and the communication channel X is used. New development of 1 A, 21 B is required. Then, in order to develop the data conversion circuits 21A and 21B, it is necessary to analyze the input and output of the system level IPA and IPB and verify the consistency of the input and output data. In other words, it is necessary to consider not only the implementation of the processing algorithm but also the “integrity of input / output data”.
- RTLIP and software IP can be easily searched by referring to the IP database, but the design man-hours are required to generate the data conversion circuit, so that there is a problem that the design efficiency cannot be improved. .
- the invention according to the present embodiment solves such a problem and realizes an IP-based LSI design with high design efficiency.
- FIG. 3 is a diagram showing an example of a configuration of a main part of the IP-based LSI design system according to the present embodiment.
- the system level IP 31 includes, for each IPA and IPB, a processing algorithm description section 33A, 33B that describes a processing algorithm of the IP, and an input serving as a processing unit.
- Data structure definition This is divided into an input data structure definition part 34A, 34B, and an output data structure definition part 35A, 35B, which represents the structure definition of the output data as a processing unit.
- the IP 32 representing the information of the communication channel X is also stored in the IP device 30.
- IP32 describes the definition of the input / output data structure of communication channel X.
- the processing algorithm description section describes an algorithm for processing for separating an NTSC signal into a luminance signal and a chrominance signal on a line-by-line basis.
- the definition of one line of the NTSC signal to be input is described, for example, as “in [8] [5 25]”.
- the definitions of the luminance signal and the chrominance signal to be output are described, for example, as “outl [4] [5 25], out 2 [4] [5 2 5]”.
- the conversion circuit generation means 36 generates a data conversion circuit in response to the design data at the system level and the designation of the communication channel. At this time, the input data structure definition sections 34A and 34B and the output data structure definition sections 35A and 35B of the system level IP 31 in the IP database 30 and the communication channel IP32 are connected. Search for.
- FIG. 4 is a diagram showing an example of the data conversion circuit generated by the conversion circuit generation means 36.
- 2A shows an example of the data conversion circuit 21A in FIG. 2B
- FIG. 2B shows an example of the data conversion circuit 21B.
- RTL IPA and IPB are both IPs related to image processing and perform data input / output in line units, and that communication channel X performs data transfer in pixel units.
- the channel input side conversion circuit generation section 37 and the output data structure definition section 35 A of the system level IPA retrieve the information of the input data structure of IP32 of communication channel X. Then, as shown in Fig. 4 (a), according to the retrieved information, the line The size of the buffer 41 is determined, the output selector 42 is generated, and the control circuit 43 is generated. Similarly, the channel output side conversion circuit generation unit 38 generates the data conversion circuit 21B between the communication channel X and RTLIPB by using the output data structure of the IP 32 of the communication channel X. The information and the input data structure definition part 34B of the system level IPB are searched. Then, as shown in FIG.
- FIG. 5 assumes a case where the data word length per communication unit is converted.
- RTLI PA and IPB both perform data input / output in 32-bit units, and communication channel X performs data transfer in 16-bit units.
- a data conversion circuit 21A including a 32-bit register 51, a selector 52 and a control circuit 53 is generated between the RTLIPA and the communication channel X as shown in FIG. 5 (b).
- a data conversion circuit including a 16-bit data distribution circuit 56, a 32-bit register 57, and a control circuit 58 as shown in FIG. 5 (c) is provided between the communication channel X and the RTL IPB. 2 1 B is generated.
- FIG. 6 is a diagram showing another example of the data conversion circuit.
- the RTLI PA has an internal memory 61 having a length of 32 bits and outputs an address data specifying the storage position of output data in the internal memory 61.
- Panel X shall be capable of 32-bit data transfer. That is, in FIG. 6, it is assumed that conversion is performed between address data designating a data storage location and actual data.
- a data conversion circuit 21 A comprising a DMA (Direct Memory Access) circuit is generated between the RTLIPA and the communication channel X, and the work memories 62 and R are provided between the communication channel X and the RT LI PB.
- a data conversion circuit 21 B including the / W control circuit 63 is generated.
- the data converter 21 A which is a DMA circuit, stores internal memory 6 1 Data is read continuously from.
- the R / W control circuit 63 writes a series of data continuously transmitted from the communication channel X to the work memory 62, and outputs address data representing a write position to the RTLIPB. From the RTLIPB, the work memory 62 is accessed to obtain data.
- FIG. 7 is a diagram schematically showing the conversion from the system level to the architecture level or the function level when the data structure is changed between IPs.
- the output data of the system level IPA is in units of lines (50 pixels x 100 lines)
- the input data of the system level IPB is in units of sub-blocks (40 pixels x 90 lines). It is assumed that there is.
- FIG. 8 is an example of a configuration of a main part of the IP-based LSI design system according to the present embodiment, and is a diagram corresponding to FIG.
- the conversion circuit generating means 36 A shown in FIG. 8 receives the information indicating the correspondence between the data structure of the IPA output and the IPB input in addition to the system-level design data and the designation of the communication channel. Generates
- FIG. 9 is a diagram showing an example of the data conversion circuit generated by the conversion circuit generation means 36A.
- the channel output side conversion circuit generation unit 38 searches the information of the output data structure of IP 32 of the communication channel X and the input data structure definition unit 34 B of the system level IPB, and as shown in FIG.
- a distribution circuit 71 is generated in accordance with the obtained information, a size of the buffer 72 is determined, a selector 73 is generated, and a control circuit 74 is generated.
- IP-based LSI design when selecting an applicable IP by searching the IP database, it is extremely rare that the selected IP can be used as it is for the LSI to be newly designed. In practice, it is considered that most of the time, the selected IP is inappropriate from the viewpoint of specifications, or even if applicable, it needs to be corrected and verified. This leads to an increase in design man-hours and an efficient LSI. It hinders the realization of the design.
- IP-DB driven reuse design technique This classifies input data into components that are likely to have existing IPs so that existing design assets (IPs) can be used effectively.
- FIG. 10 is a diagram showing a configuration of an IP-based LSI design system according to the second embodiment of the present invention.
- each of the steps S21 to S25 is realized by, for example, a software executed by the combination user.
- input data is hierarchically generated with reference to the function classification DB 81, and in the performance request allocation step S22, the elements of each layer of the input data are generated. Assign performance specifications.
- FIG. 11 is a diagram showing an example of the contents of the function classification DB81.
- the device configuration is classified into elements in terms of function and systematized.
- functions are classified for two types of digital video equipment.
- digital video equipment A is divided into an input interface, a servo control, a signal processing, a system control, and an output interface.
- the input and output interfaces are classified into signal reading units, the signal processing units are classified into error correction units and AV processing units, and the output interface units are classified into output signal generation units and signal transmission units.
- the AV processing unit is further classified into an AV separation unit, a VIDEO processing unit, and an Audio processing unit.
- FIG. 12 is a diagram showing an example of the input data obtained in the input data generation step S 21 and the performance requirement assignment step S 22.
- digital televideo equipment is assumed as a new design target, and the digital TV function added with the digital video function is given as its specification 80.
- the function classification DB 8 shown in FIG. A new function hierarchy is constructed as input data based on the function classification in 1.
- an IP suitable for the LSI to be designed is selected from each IP stored in the existing design asset DB82 while referring to the functional classification DB81.
- FIG. 13 is a diagram showing an example of the contents of the existing design asset DB82.
- the existing design assets DB82 are stored in association with the elements in each of the IP function classifications DB81 already generated.
- blocks surrounded by squares indicate each IP, and those surrounded by an ellipse correspond to each element in the function class DB81.
- the function “error correction” three types of IPs, “Reed Solomon”, “Viterbi” and “Trellis”, have been generated.
- the selection of the IP may be performed for any hierarchy. That is, there may be multiple choices for IP selection.
- the suitability of the selected IP is evaluated with reference to the existing design assets DB82 and the design asset compatibility evaluation rule DB83. That is, the optimal solution for IP selection is determined from the viewpoints of cost, power consumption, operating speed, and the like.
- FIG. 14 is a diagram showing an example of each IP information included in the existing design asset DB82.
- the format of the data, the format of the data notation, the design method, the design results, and the deliverables are described as IP information.
- FIG. 15 is a diagram showing an example of the contents of the design asset compatibility evaluation rule DB 83.
- the DB83 for design asset compatibility evaluation rule stores information that specifies the compatibility of each IP stored in the existing design asset DB82 as shown in Fig. 14. ing.
- Theoretical rules include “good compatibility” and “long life” as examples of good compatibility, and “additional functions required” as examples of poor compatibility. Does not fit. "
- the rules of experience are that, when compatibility is good, there are many shared parts and "power consumption can be reduced", and when compatibility is poor, operation cannot be verified and "area becomes large”. and so on.
- a related design asset search step S25 for functional elements for which no matching IP exists, an IP having a similar function is selected from each of the IPs stored in the existing design asset DB82. Then, the function of the selected IP is modified so as to be suitable for the functional element. As a result, the man-hours required for function modification can be significantly reduced.
- the modified IP is registered in the existing design asset DB82 as a newly generated IP.
- the existing design asset DB 82 may be provided with a means for managing history information such as a parent IP for each IP to be stored and a difference from the parent IP.
- FIG. 16 is a diagram showing a configuration of an IP-based LSI design system according to the third embodiment of the present invention.
- the effective use of the IP makes it possible to reduce the power consumption (low power consumption) of the system LSI.
- the function definition 91 for the LSI to be designed is obtained by the system-level IP.
- an architecture generation step S31 an architecture-level design data 92 is generated from the function definition 91 by the system-level IP.
- the operation analysis step S32 uses the architecture-level design data 92 and the instruction 93 and the operation pattern definition 94 that defines the operation of the system LSI.
- the operation analysis step S32 uses the architecture-level design data 92 and the instruction 93 and the operation pattern definition 94 that defines the operation of the system LSI.
- the operation analysis of the LSI to be designed is performed.
- c Figure 1 7 performed is a diagram showing an example of the operation analysis results. In FIG. 17, power is required for the part that is operating, but power is not required for the part that is not operating, so the power can be turned off. In addition, instead of changing the It is also conceivable to stop the supply of energy.
- a power control function generation step S33 based on the operation analysis result 95, the power control pro- cess CTL1 of the entire LSI and the power control pro- Waits CTL2 to CTL6 of each IP are archi- tected. Generate to level design data ⁇ method 1>.
- power control may be performed by adding a low-power instruction to the original instruction.
- each IP is described as being divided into the processing algorithm description section, the input data structure definition section, and the output data structure definition section.
- the data conversion circuit can be easily generated.
- the equipment configuration is classified into elements in terms of functions and a systematic function classification data base is used, the IP reuse efficiency can be improved.
- a power control block can be easily generated. Therefore, in the IP-based LSI design, the design efficiency can be further improved.
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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EP00974849A EP1237099A4 (en) | 1999-11-18 | 2000-11-08 | IP-BASED LSI DESIGN SYSTEM AND DESIGN METHOD THEREOF |
US10/130,546 US6961913B1 (en) | 1999-11-18 | 2000-11-08 | IP base LSI designing system and designing method |
KR1020027006318A KR100725680B1 (ko) | 1999-11-18 | 2000-11-08 | 아이피 기반 엘에스아이 설계시스템 및 설계방법 |
US11/211,512 US20060036974A1 (en) | 1999-11-18 | 2005-08-26 | IP-based LSI design system and design method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP32779699A JP3974300B2 (ja) | 1999-11-18 | 1999-11-18 | Ipベースlsi設計システムおよび設計方法 |
JP11-327796 | 1999-11-18 |
Related Child Applications (1)
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US11/211,512 Division US20060036974A1 (en) | 1999-11-18 | 2005-08-26 | IP-based LSI design system and design method |
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WO2001037148A1 true WO2001037148A1 (fr) | 2001-05-25 |
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PCT/JP2000/007869 WO2001037148A1 (fr) | 1999-11-18 | 2000-11-08 | Systeme de conception lsi a base ip et procede de conception associe |
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US (2) | US6961913B1 (ja) |
EP (1) | EP1237099A4 (ja) |
JP (1) | JP3974300B2 (ja) |
KR (1) | KR100725680B1 (ja) |
CN (3) | CN1702659A (ja) |
TW (1) | TW542978B (ja) |
WO (1) | WO2001037148A1 (ja) |
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CN103412842A (zh) * | 2013-08-30 | 2013-11-27 | 国网能源研究院 | 基于电力***与通信***的联合模拟方法 |
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1999
- 1999-11-18 JP JP32779699A patent/JP3974300B2/ja not_active Expired - Fee Related
-
2000
- 2000-11-08 CN CNA2005100689640A patent/CN1702659A/zh active Pending
- 2000-11-08 US US10/130,546 patent/US6961913B1/en not_active Expired - Fee Related
- 2000-11-08 WO PCT/JP2000/007869 patent/WO2001037148A1/ja active IP Right Grant
- 2000-11-08 CN CN00815698A patent/CN1390331A/zh active Pending
- 2000-11-08 CN CNA2005100689636A patent/CN1702658A/zh active Pending
- 2000-11-08 EP EP00974849A patent/EP1237099A4/en not_active Withdrawn
- 2000-11-08 TW TW089123668A patent/TW542978B/zh not_active IP Right Cessation
- 2000-11-08 KR KR1020027006318A patent/KR100725680B1/ko not_active IP Right Cessation
-
2005
- 2005-08-26 US US11/211,512 patent/US20060036974A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0584828A2 (en) * | 1992-08-26 | 1994-03-02 | Matsushita Electric Industrial Co., Ltd. | LSI automated design system |
JPH07129657A (ja) * | 1993-10-29 | 1995-05-19 | Nec Corp | 論理最適化装置 |
EP0674285A2 (en) * | 1994-03-24 | 1995-09-27 | Matsushita Electric Industrial Co., Ltd. | LSI design automation system |
Non-Patent Citations (2)
Title |
---|
KATSUYA FURUKI ET AL.: "System LSI sekkei system open CAD (V5)", NEC HIGOU, vol. 50, no. 3, March 1997 (1997-03-01), JAPAN, pages 98 - 102, XP002935896 * |
See also references of EP1237099A4 * |
Also Published As
Publication number | Publication date |
---|---|
TW542978B (en) | 2003-07-21 |
KR20030004304A (ko) | 2003-01-14 |
CN1390331A (zh) | 2003-01-08 |
US20060036974A1 (en) | 2006-02-16 |
US6961913B1 (en) | 2005-11-01 |
EP1237099A4 (en) | 2009-06-24 |
EP1237099A1 (en) | 2002-09-04 |
CN1702658A (zh) | 2005-11-30 |
CN1702659A (zh) | 2005-11-30 |
JP2001142932A (ja) | 2001-05-25 |
JP3974300B2 (ja) | 2007-09-12 |
KR100725680B1 (ko) | 2007-06-07 |
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