WO2001016702A1 - Register set used in multithreaded parallel processor architecture - Google Patents
Register set used in multithreaded parallel processor architecture Download PDFInfo
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- WO2001016702A1 WO2001016702A1 PCT/US2000/023993 US0023993W WO0116702A1 WO 2001016702 A1 WO2001016702 A1 WO 2001016702A1 US 0023993 W US0023993 W US 0023993W WO 0116702 A1 WO0116702 A1 WO 0116702A1
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- 230000006870 function Effects 0.000 claims abstract description 14
- 230000015654 memory Effects 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 16
- 238000012545 processing Methods 0.000 claims description 13
- 230000009977 dual effect Effects 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 238000004590 computer program Methods 0.000 claims 1
- 238000012546 transfer Methods 0.000 description 11
- 238000004891 communication Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000011664 signaling Effects 0.000 description 5
- 238000005457 optimization Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000006855 networking Effects 0.000 description 2
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 description 1
- 241001522296 Erithacus rubecula Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
- G06F9/30127—Register windows
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
Definitions
- This invention relates to computer processors.
- Parallel processing is an efficient form of information processing of concurrent events in a computing process.
- Parallel processing demands concurrent execution of many programs in a computer, in contrast to sequential processing.
- parallelism involves doing more than one thing at the same time.
- a serial paradigm where all tasks are performed sequentially at a single station or a pipelined machine where tasks are performed at specialized stations
- parallel processing a plurality of stations are provided with each capable of performing all tasks. That is, in general all or a plurality of the stations work simultaneously and independently on the same or common elements of a problem. Certain problems are suitable for solution by applying parallel processing.
- FIG. 1 is a block diagram of a communication system employing a hardware-based multithreaded processor.
- FIG. 2 is a detailed block diagram of the hardware-based multithreaded processor of FIG. 1.
- FIG. 3 is a block diagram of a microengine functional unit employed in the hardware-based multithreaded processor of FIGS. 1 and 2.
- FIG. 4 is a block diagram of a pipeline in the microengine of FIG. 3.
- FIG. 5 is a block diagram showing general purpose register address arrangement.
- a communication system 10 includes a parallel, hardware-based multithreaded processor 12.
- the hardware-based multithreaded processor 12 is coupled to a bus such as a PCI bus 14, a memory system 16 and a second bus 18.
- the system 10 is especially useful for tasks that can be broken into parallel subtasks or functions.
- hardware-based multithreaded processor 12 is useful for tasks that are bandwidth oriented rather than latency oriented.
- the hardware-based multithreaded processor 12 has multiple microengines 22 each with multiple hardware controlled threads that can be simultaneously active and independently work on a task.
- the hardware-based multithreaded processor 12 also includes a central controller 20 that assists in loading microcode control for other resources of the hardware-based multithreaded processor 12 and performs other general purpose computer type functions such as handling protocols, exceptions, extra support for packet processing where the microengines pass the packets off for more detailed processing such as in boundary conditions.
- the processor 20 is a Strong Arm (Arm is a trademark of ARM Limited, United Kingdom) based architecture.
- the general purpose microprocessor 20 has an operating system. Through the operating system the processor 20 can call functions to operate on microengines 22a-22f.
- the processor 20 can use any supported operating system preferably a real time operating system.
- operating systems such as, MicrosoftNT ® real-time, VXWorks and DCUS, a freeware operating system available over the Internet, can be used.
- the hardware-based multithreaded processor 12 also includes a plurality of function microengines 22a-22f.
- Functional microengines (microengines) 22a-22f each maintain a plurality of program counters in hardware and states associated with the program counters. Effectively, a corresponding plurality of sets of threads can be simultaneously active on each of the microengines 22a-22f while only one is actually operating at any one time.
- microengines 22a-22f there are six microengines 22a-22f as shown. Each microengines 22a-22f has capabilities for processing four hardware threads.
- the six microengines 22a-22f operate with shared resources including memory system 16 and bus interfaces 24 and 28.
- the memory system 16 includes a Synchronous Dynamic Random Access Memory (SDRAM) controller 26a and a Static Random Access Memory (SRAM) controller 26b. SDRAM memory 16a and SDRAM controller 26a are typically used for processing large volumes of data, e.g., processing of network payloads from network packets.
- the SRAM controller 26b and SRAM memory 16b are used in a networking implementation for low latency, fast access tasks, e.g., accessing look-up tables, memory for the core processor 20, and so forth.
- the six microengines 22a-22f access either the SDRAM 16a or SRAM 16b based on characteristics of the data. Thus, low latency, low bandwidth data is stored in and fetched from SRAM, whereas higher bandwidth data for which latency is not as important, is stored in and fetched from SDRAM.
- the microengines 22a-22f can execute memory reference instructions to either the SDRAM controller 26a or SRAM controller 16b. Advantages of hardware multithreading can be explained by SRAM or
- SDRAM memory accesses As an example, an SRAM access requested by a Thread_0, from a microengine will cause the SRAM controller 26b to initiate an access to the
- the SRAM controller controls arbitration for the SRAM bus, accesses the SRAM 16b, fetches the data from the SRAM 16b, and returns data to a requesting microengine 22a-22b.
- a requesting microengine 22a-22b During an SRAM access, if the microengine e.g., 22a had only a single thread that could operate, that microengine would be dormant until data was returned from the SRAM.
- the hardware context swapping enables other contexts with unique program counters to execute in that same microengine.
- another thread e.g., Thread_l can function while the first thread, e.g., Thread_0, is awaiting the read data to return.
- Thread_l may access the SDRAM memory 16a. While Thread_l operates on the SDRAM unit, and Thread_0 is operating on the SRAM unit, a new thread, e.g., Thread_2 can now operate in the microengine 22a. Thread_2 can operate for a certain amount of time until it needs to access memory or perform some other long latency operation, such as making an access to a bus interface. Therefore, simultaneously, the processor 12 can have a bus operation, SRAM operation and SDRAM operation all being completed or operated upon by one microengine 22a and have one more thread available to process more work in the data path.
- a bus operation, SRAM operation and SDRAM operation all being completed or operated upon by one microengine 22a and have one more thread available to process more work in the data path.
- the hardware context swapping also synchronizes completion of tasks. For example, two threads could hit the same shared resource e.g., SRAM.
- Each one of these separate functional units, e.g., the FBUS interface 28, the SRAM controller 26a, and the SDRAM controller 26b, when they complete a requested task from one of the microengine thread contexts reports back a flag signaling completion of an operation.
- the microengine can determine which thread to turn on.
- the hardware-based multithreaded processor 12 interfaces to network devices such as a media access controller device e.g., a 10/100BaseT Octal MAC 13a or a Gigabit Ethernet device 13b.
- a media access controller device e.g., a 10/100BaseT Octal MAC 13a or a Gigabit Ethernet device 13b.
- the hardware-based multithreaded processor 12 can interface to any type of communication device or interface that receives/sends large amounts of data.
- Communication system 10 functioning in a networking application could receive a plurality of network packets from the devices 13a, 13b and process those packets in a parallel manner. With the hardware-based multithreaded processor 12, each network packet can be independently processed.
- processor 12 is a print engine for a postscript processor or as a processor for a storage subsystem, i.e., RAID disk storage.
- a further use is as a matching engine.
- the advent of electronic trading requires the use of electronic matching engines to match orders between buyers and sellers. These and other parallel types of tasks can be accomplished on the system 10.
- the processor 12 includes a bus interface 28 that couples the processor to the second bus 18.
- Bus interface 28 in one embodiment couples the processor 12 to the so-called FBUS 18 (FIFO bus).
- the FBUS interface 28 is responsible for controlling and interfacing the processor 12 to the FBUS 18.
- the FBUS 18 is a 64-bit wide FIFO bus, used to interface to Media Access Controller (MAC) devices.
- MAC Media Access Controller
- the processor 12 includes a second interface e.g., a PCI bus interface 24 that couples other system components that reside on the PCI 14 bus to the processor 12.
- the PCI bus interface 24 provides a high speed data path 24a to memory 16 e.g., the SDRAM memory 16a. Through that path data can be moved quickly from the SDRAM 16a through the PCI bus 14, via direct memory access (DMA) transfers.
- the hardware based multithreaded processor 12 supports image transfers.
- the hardware based multithreaded processor 12 can employ a plurality of DMA channels so if one target of a DMA transfer is busy, another one of the DMA channels can take over the PCI bus to deliver information to another target to maintain high processor 12 efficiency.
- the PCI bus interface 24 supports target and master operations.
- Target operations are operations where slave devices on bus 14 access SDRAMs through reads and writes that are serviced as a slave to target operation.
- the processor core 20 sends data directly to or receives data directly from the PCI interface
- Each of the functional units are coupled to one or more internal buses.
- the internal buses are dual, 32 bit buses (i.e., one bus for read and one for write).
- the hardware-based multithreaded processor 12 also is constructed such that the sum of the bandwidths of the internal buses in the processor 12 exceed the bandwidth of external buses coupled to the processor 12.
- the processor 12 includes an internal core processor bus 32, e.g., an ASB bus (Advanced System Bus) that couples the processor core 20 to the memory controller 26a, 26c and to an ASB translator 30 described below.
- ASB bus Advanced System Bus
- the ASB bus is a subset of the so called AMBA bus that is used with the Strong Arm processor core.
- the processor 12 also includes a private bus 34 that couples the microengine units to SRAM controller 26b, ASB translator 30 and FBUS interface 28.
- a memory bus 38 couples the memory controller 26a, 26b to the bus interfaces 24 and 28 and memory system 16 including flashrom 16c used for boot operations and so forth.
- each of the microengines 22a-22f includes an arbiter that examines flags to determine the available threads to be operated upon. Any thread from any of the microengines 22a-22f can access the SDRAM controller 26a, SDRAM controller 26b or FBUS interface 28.
- the memory controllers 26a and 26b each include a plurality of queues to store outstanding memory reference requests. The queues either maintain order of memory references or arrange memory references to optimize memory bandwidth. For example, if a thread_0 has no dependencies or relationship to a thread l, there is no reason that thread 1 and 0 cannot complete their memory references to the SRAM unit out of order.
- the microengines 22a-22f issue memory reference requests to the memory controllers 26a and 26b.
- the microengines 22a-22f flood the memory subsystems 26a and 26b with enough memory reference operations such that the memory subsystems 26a and 26b become the bottleneck for processor 12 operation. If the memory subsystem 16 is flooded with memory requests that are independent in nature, the processor 12 can perform memory reference sorting. Memory reference sorting improves achievable memory bandwidth. Memory reference sorting, as described below, reduces dead time or a bubble that occurs with accesses to SRAM. With memory references to SRAM, switching current direction on signal lines between reads and writes produces a bubble or a dead time waiting for current to settle on conductors coupling the SRAM 16b to the SRAM controller 26b.
- Memory reference sorting allows the processor 12 to organize references to memory such that long strings of reads can be followed by long strings of writes. This can be used to minimize dead time in the pipeline to effectively achieve closer to maximum available bandwidth. Reference sorting helps maintain parallel hardware context threads. On the SDRAM, reference sorting allows hiding of pre-charges from one bank to another bank. Specifically, if the memory system 16b is organized into an odd bank and an even bank, while the processor is operating on the odd bank, the memory controller can start precharging the even bank. Precharging is possible if memory references alternate between odd and even banks.
- the processor 12 By ordering memory references to alternate accesses to opposite banks, the processor 12 improves SDRAM bandwidth. Additionally, other optimizations can be used. For example, merging optimizations where operations that can be merged, are merged prior to memory access, open page optimizations where by examining addresses an opened page of memory is not reopened, chaining, as will be described below, and refreshing mechanisms, can be employed.
- the FBUS interface 28 supports Transmit and Receive flags for each port that a MAC device supports, along with an Interrupt flag indicating when service is warranted.
- the FBUS interface 28 also includes a controller 28a that performs header processing of incoming packets from the FBUS 18.
- the controller 28a extracts the packet headers and performs a microprogrammable source/destination/protocol hashed lookup (used for address smoothing) in SRAM. If the hash does not successfully resolve, the packet header is sent to the processor core 20 for additional processing.
- the FBUS interface 28 supports the following internal data transactions:
- FBUS unit Shared bus SRAM to/from microengine.
- FBUS unit (via private bus) writes from SDRAM Unit.
- the FBUS 18 is a standard industry bus and includes a data bus, e.g., 64 bits wide and sideband control for address and read/write control.
- the FBUS interface 28 provides the ability to input large amounts of data using a series of input and output
- FIFO's 29a-29b From the FIFOs 29a-29b, the microengines 22a-22f fetch data from or command the SDRAM controller 26a to move data from a receive FIFO in which data has come from a device on bus 18, into the FBUS interface 28. The data can be sent through memory controller 26a to SDRAM memory 16a, via a direct memory access. Similarly, the microengines can move data from the SDRAM 26a to interface 28, out to FBUS 18, via the FBUS interface 28.
- a command request can be a memory request or a FBUS request.
- a command request can move data from a register located in a microengine 22a to a shared resource, e.g., an SDRAM location, SRAM location, flash memory or some MAC address.
- the commands are sent out to each of the functional units and the shared resources.
- the shared resources do not need to maintain local buffering of the data. Rather, the shared resources access distributed data located inside of the microengines. This enables microengines 22a-22f, to have local access to data rather than arbitrating for access on a bus and risk contention for the bus.
- the data buses e.g., ASB bus 30, SRAM bus 34 and SDRAM bus 38 coupling these shared resources, e.g., memory controllers 26a and 26b are of sufficient bandwidth such that there are no internal bottlenecks.
- the processor 12 has an bandwidth requirement where each of the functional units is provided with at least twice the maximum bandwidth of the internal buses.
- the SDRAM can run a 64 bit wide bus at 83 MHz.
- the SRAM data bus could have separate read and write buses, e.g., could be a read bus of 32 bits wide running at 166 MHz and a write bus of 32 bits wide at 166 MHz. That is, in essence, 64 bits running at 166 MHz which is effectively twice the bandwidth of the SDRAM.
- the core processor 20 also can access the shared resources.
- the core processor 20 has a direct communication to the SDRAM controller 26a to the bus interface 24 and to SRAM controller 26b via bus 32.
- the core processor 20 access the microengines 22a-22f via the ASB Translator 30 over bus 34.
- the ASB translator 30 can physically reside in the FBUS interface 28, but logically is distinct.
- the ASB Translator 30 performs an address translation between FBUS microengine transfer register locations and core processor addresses (i.e., ASB bus) so that the core processor 20 can access registers belonging to the microengines 22a- 22c.
- the processor core 20 includes a RISC core 50 implemented in a five stage pipeline performing a single cycle shift of one operand or two operands in a single cycle, provides multiplication support and 32 bit barrel shift support.
- This RISC core 50 is a standard Strong Arm® architecture but it is implemented with a five stage pipeline for performance reasons.
- the processor core 20 also includes a 16 kilobyte instruction cache 52, an 8 kilobyte data cache 54 and a prefetch stream buffer 56.
- the core processor 20 performs arithmetic operations in parallel with memory writes and instruction fetches.
- the core processor 20 interfaces with other functional units via the ARM defined ASB bus.
- the ASB bus is a 32-bit bi-directional bus 32.
- the microengine includes a control store 70 which, in one implementation, includes a RAM of here 1,024 words of 32 bit.
- the RAM stores a microprogram.
- the microprogram is loadable by the core processor 20.
- the microengine 22f also includes controller logic 72.
- the controller logic includes an instruction decoder 73 and program counter (PC) units 72a-72d.
- the four micro program counters 72a-72d are maintained in hardware.
- the microengine 22f also includes context event switching logic 74.
- Context event logic 74 receives messages (e.g., SEQ_#_EVENT_RESPONSE; FBI_EVENT_RESPONSE; SRAM _EVENT_RESPONSE; SDRAM _EVENT_RESPONSE; and ASB
- _EVENT_RESPONSE from each one of the shared resources, e.g., SRAM 26a, SDRAM 26b, or processor core 20, control and status registers, and so forth. These messages provide information on whether a requested function has completed. Based on whether or not a function requested by a thread has completed and signaled completion, the thread needs to wait for that completion signal, and if the thread is enabled to operate, then the thread is placed on an available thread list (not shown).
- the microengine 22f can have a maximum of e.g., 4 threads available.
- the microengines 22 employ signaling states that are global. With signaling states, an executing thread can broadcast a signal state to all microengines 22. Receive Request Available signal, Any and all threads in the microengines can branch on these signaling states. These signaling states can be used to determine availability of a resource or whether a resource is due for servicing.
- the context event logic 74 has arbitration for the four (4) threads. In one embodiment, the arbitration is a round robin mechanism. Other techniques could be used including priority queuing or weighted fair queuing.
- the microengine 22f also includes an execution box (EBOX) data path 76 that includes an arithmetic logic unit 76a and general purpose register set 76b.
- the arithmetic logic unit 76a performs arithmetic and logical functions as well as shift functions.
- the registers set 76b has a relatively large number of general purpose registers. As will be described in FIG. 6, in this implementation there are 64 general purpose registers in a first bank, Bank A and 64 in a second bank, Bank B.
- the general purpose registers are windowed as will be described so that they are relatively and absolutely addressable.
- the microengine 22f also includes a write transfer register stack 78 and a read transfer stack 80. These registers are also windowed so that they are relatively and absolutely addressable.
- Write transfer register stack 78 is where write data to a resource is located.
- read register stack 80 is for return data from a shared resource.
- an event signal from the respective shared resource e.g., the SRAM controller 26a, SDRAM controller 26b or core processor 20 will be provided to context event arbiter 74 which will then alert the thread that the data is available or has been sent.
- Both transfer register banks 78 and 80 are connected to the execution box (EBOX) 76 through a data path.
- the read transfer register has 64 registers and the write transfer register has 64 registers.
- the microengine datapath maintains a 5 -stage micropipeline 82.
- This pipeline includes lookup of microinstruction words 82a, formation of the register file addresses 82b, read of operands from register file 82c, ALU, shift or compare operations 82d, and write-back of results to registers 82e.
- the microengine can perform a simultaneous register file read and write, which completely hides the write operation.
- the SDRAM interface 26a provides a signal back to the requesting microengine on reads that indicates whether a parity error occurred on the read request.
- the microengine microcode is responsible for checking the SDRAM read Parity flag when the microengine uses any return data. Upon checking the flag, if it was set, the act of branching on it clears it. The Parity flag is only sent when the SDRAM is enabled for checking, and the SDRAM is parity protected.
- the microengines and the PCI Unit are the only requestors notified of parity errors. Therefore, if the processor core 20 or FIFO requires parity protection, a microengine assists in the request.
- the two register address spaces that exist are Locally accessibly registers, and Globally accessible registers accessible by all microengines.
- Each bank is capable of performing a simultaneous read and write to two different words within its bank.
- the register set 76b is also organized into four windows 76b 0 -76b 3 of 32 registers that are relatively addressable per thread.
- thread_0 will find its register 0 at 77a (register 0)
- the thread_l will find its register_0 at 77b (register 32)
- thread_2 will find its register_0 at 77c (register 64)
- thread_3 at 77d (register 96).
- Relative addressing is supported so that multiple threads can use the exact same control store and locations but access different windows of register and perform different functions.
- the uses of register window addressing and bank addressing provide the requisite read bandwidth using only dual ported RAMS in the microengine 22f
- windowed registers do not have to save data from context switch to context switch so that the normal push and pop of a context swap file or stack is eliminated.
- Context switching here has a 0 cycle overhead for changing from one context to another.
- Relative register addressing divides the register banks into windows across the address width of the general purpose register set. Relative addressing allows access any of the windows relative to the starting point of the window. Absolute addressing is also supported in this architecture where any one of the absolute registers may be accessed by any of the threads by providing the exact address of the register.
- a GPR
- a6 0
- b6 0
- SRAM/ASB
- a4 0
- SDRAM
- addresses a specified address is offset within context space as defined by a 5 -bit source field (a4-a0 or b4-b0): 7 6 5 4 3 2 1 0 + — + — + — + — + — + — + — + — + — + — + — + — +
- a GPR I a4
- a4 0
- b4 0
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---|---|---|---|
CA002386558A CA2386558C (en) | 1999-09-01 | 2000-08-31 | Register set used in multithreaded parallel processor architecture |
DE60038976T DE60038976D1 (en) | 1999-09-01 | 2000-08-31 | REGISTER SET FOR USE IN A PARALLEL MULTI-WIRE PROCESSOR ARCHITECTURE |
AU70984/00A AU7098400A (en) | 1999-09-01 | 2000-08-31 | Register set used in multithreaded parallel processor architecture |
PCT/US2000/023993 WO2001016702A1 (en) | 1999-09-01 | 2000-08-31 | Register set used in multithreaded parallel processor architecture |
US10/070,091 US7546444B1 (en) | 1999-09-01 | 2000-08-31 | Register set used in multithreaded parallel processor architecture |
EP00959711A EP1236088B9 (en) | 1999-09-01 | 2000-08-31 | Register set used in multithreaded parallel processor architecture |
US12/477,287 US7991983B2 (en) | 1999-09-01 | 2009-06-03 | Register set used in multithreaded parallel processor architecture |
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US15196199P | 1999-09-01 | 1999-09-01 | |
US60/151,961 | 1999-09-01 | ||
PCT/US2000/023993 WO2001016702A1 (en) | 1999-09-01 | 2000-08-31 | Register set used in multithreaded parallel processor architecture |
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US10/070,091 A-371-Of-International US7546444B1 (en) | 1999-09-01 | 2000-08-31 | Register set used in multithreaded parallel processor architecture |
US12/477,287 Continuation US7991983B2 (en) | 1999-09-01 | 2009-06-03 | Register set used in multithreaded parallel processor architecture |
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SG155038A1 (en) * | 2001-09-28 | 2009-09-30 | Consentry Networks Inc | A multi-threaded packet processing engine for stateful packet processing |
US7702004B2 (en) | 2002-12-09 | 2010-04-20 | Alexander Roger Deas | Simultaneous bidirectional differential signalling interface |
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US8364934B2 (en) * | 2006-07-11 | 2013-01-29 | Freescale Semiconductor, Inc. | Microprocessor and method for register addressing therein |
US20090125706A1 (en) * | 2007-11-08 | 2009-05-14 | Hoover Russell D | Software Pipelining on a Network on Chip |
US20090125703A1 (en) * | 2007-11-09 | 2009-05-14 | Mejdrich Eric O | Context Switching on a Network On Chip |
US8261025B2 (en) | 2007-11-12 | 2012-09-04 | International Business Machines Corporation | Software pipelining on a network on chip |
US8526422B2 (en) * | 2007-11-27 | 2013-09-03 | International Business Machines Corporation | Network on chip with partitions |
US7917703B2 (en) * | 2007-12-13 | 2011-03-29 | International Business Machines Corporation | Network on chip that maintains cache coherency with invalidate commands |
US8473667B2 (en) | 2008-01-11 | 2013-06-25 | International Business Machines Corporation | Network on chip that maintains cache coherency with invalidation messages |
US8010750B2 (en) * | 2008-01-17 | 2011-08-30 | International Business Machines Corporation | Network on chip that maintains cache coherency with invalidate commands |
US8018466B2 (en) * | 2008-02-12 | 2011-09-13 | International Business Machines Corporation | Graphics rendering on a network on chip |
US7913010B2 (en) * | 2008-02-15 | 2011-03-22 | International Business Machines Corporation | Network on chip with a low latency, high bandwidth application messaging interconnect |
US8490110B2 (en) * | 2008-02-15 | 2013-07-16 | International Business Machines Corporation | Network on chip with a low latency, high bandwidth application messaging interconnect |
US20090245257A1 (en) * | 2008-04-01 | 2009-10-01 | International Business Machines Corporation | Network On Chip |
US20090260013A1 (en) * | 2008-04-14 | 2009-10-15 | International Business Machines Corporation | Computer Processors With Plural, Pipelined Hardware Threads Of Execution |
US20090271172A1 (en) * | 2008-04-24 | 2009-10-29 | International Business Machines Corporation | Emulating A Computer Run Time Environment |
US8078850B2 (en) * | 2008-04-24 | 2011-12-13 | International Business Machines Corporation | Branch prediction technique using instruction for resetting result table pointer |
US8423715B2 (en) | 2008-05-01 | 2013-04-16 | International Business Machines Corporation | Memory management among levels of cache in a memory hierarchy |
US8494833B2 (en) * | 2008-05-09 | 2013-07-23 | International Business Machines Corporation | Emulating a computer run time environment |
US7861065B2 (en) * | 2008-05-09 | 2010-12-28 | International Business Machines Corporation | Preferential dispatching of computer program instructions |
US8392664B2 (en) * | 2008-05-09 | 2013-03-05 | International Business Machines Corporation | Network on chip |
US8214845B2 (en) * | 2008-05-09 | 2012-07-03 | International Business Machines Corporation | Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data |
US20090282211A1 (en) * | 2008-05-09 | 2009-11-12 | International Business Machines | Network On Chip With Partitions |
US7958340B2 (en) * | 2008-05-09 | 2011-06-07 | International Business Machines Corporation | Monitoring software pipeline performance on a network on chip |
US20090282419A1 (en) * | 2008-05-09 | 2009-11-12 | International Business Machines Corporation | Ordered And Unordered Network-Addressed Message Control With Embedded DMA Commands For A Network On Chip |
US8020168B2 (en) | 2008-05-09 | 2011-09-13 | International Business Machines Corporation | Dynamic virtual software pipelining on a network on chip |
US7991978B2 (en) * | 2008-05-09 | 2011-08-02 | International Business Machines Corporation | Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor |
US8230179B2 (en) * | 2008-05-15 | 2012-07-24 | International Business Machines Corporation | Administering non-cacheable memory load instructions |
US8040799B2 (en) * | 2008-05-15 | 2011-10-18 | International Business Machines Corporation | Network on chip with minimum guaranteed bandwidth for virtual communications channels |
US8438578B2 (en) * | 2008-06-09 | 2013-05-07 | International Business Machines Corporation | Network on chip with an I/O accelerator |
US8195884B2 (en) | 2008-09-18 | 2012-06-05 | International Business Machines Corporation | Network on chip with caching restrictions for pages of computer memory |
US8902902B2 (en) | 2012-07-18 | 2014-12-02 | Netronome Systems, Incorporated | Recursive lookup with a hardware trie structure that has no sequential logic elements |
US9146920B2 (en) * | 2012-09-10 | 2015-09-29 | Netronome Systems, Inc. | Transactional memory that performs an atomic look-up, add and lock operation |
KR102254099B1 (en) | 2014-05-19 | 2021-05-20 | 삼성전자주식회사 | Method for processing memory swapping operation, and host device, storage device and data processing system adopting the same |
GB2546308B (en) * | 2016-01-15 | 2019-04-03 | Advanced Risc Mach Ltd | Data processing systems |
CN109491736B (en) * | 2018-10-16 | 2023-03-31 | 深圳壹账通智能科技有限公司 | Display method and device of pop-up frame window |
US10891708B1 (en) | 2019-11-25 | 2021-01-12 | Arm Limited | Shader program execution in graphics processing |
US11663010B2 (en) * | 2021-03-08 | 2023-05-30 | Unisys Corporation | System and method for securely debugging across multiple execution contexts |
US11726789B1 (en) | 2022-01-27 | 2023-08-15 | Nxp B.V. | Selectable register file blocks for hardware threads of a multithreaded processor |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357617A (en) * | 1991-11-22 | 1994-10-18 | International Business Machines Corporation | Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor |
US5933627A (en) * | 1996-07-01 | 1999-08-03 | Sun Microsystems | Thread switch on blocked load or store using instruction thread field |
US6092175A (en) * | 1998-04-02 | 2000-07-18 | University Of Washington | Shared register storage mechanisms for multithreaded computer systems with out-of-order execution |
Family Cites Families (347)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6336180B1 (en) | 1997-04-30 | 2002-01-01 | Canon Kabushiki Kaisha | Method, apparatus and system for managing virtual memory with virtual-physical mapping |
US3373408A (en) | 1965-04-16 | 1968-03-12 | Rca Corp | Computer capable of switching between programs without storage and retrieval of the contents of operation registers |
US3478322A (en) | 1967-05-23 | 1969-11-11 | Ibm | Data processor employing electronically changeable control storage |
US3577189A (en) | 1969-01-15 | 1971-05-04 | Ibm | Apparatus and method in a digital computer for allowing improved program branching with branch anticipation reduction of the number of branches, and reduction of branch delays |
BE795789A (en) | 1972-03-08 | 1973-06-18 | Burroughs Corp | MICROPROGRAM CONTAINING A MICRO-RECOVERY INSTRUCTION |
US3881173A (en) | 1973-05-14 | 1975-04-29 | Amdahl Corp | Condition code determination and data processing |
IT986411B (en) | 1973-06-05 | 1975-01-30 | Olivetti E C Spa | SYSTEM TO TRANSFER THE CONTROL OF PROCESSING FROM A FIRST PRIORITY LEVEL TO A SECOND PRIORITY LEVEL |
FR2253415A5 (en) | 1973-12-04 | 1975-06-27 | Cii | |
US3913074A (en) | 1973-12-18 | 1975-10-14 | Honeywell Inf Systems | Search processing apparatus |
US4130890A (en) | 1977-06-08 | 1978-12-19 | Itt Industries, Inc. | Integrated DDC memory with bitwise erase |
US4392758A (en) | 1978-05-22 | 1983-07-12 | International Business Machines Corporation | Underscore erase |
JPS56164464A (en) | 1980-05-21 | 1981-12-17 | Tatsuo Nogi | Parallel processing computer |
US4400770A (en) | 1980-11-10 | 1983-08-23 | International Business Machines Corporation | Cache synonym detection and handling means |
CA1179069A (en) | 1981-04-10 | 1984-12-04 | Yasushi Fukunaga | Data transmission apparatus for a multiprocessor system |
US4471426A (en) | 1981-07-02 | 1984-09-11 | Texas Instruments Incorporated | Microcomputer which fetches two sets of microcode bits at one time |
US4454595A (en) | 1981-12-23 | 1984-06-12 | Pitney Bowes Inc. | Buffer for use with a fixed disk controller |
US4477872A (en) | 1982-01-15 | 1984-10-16 | International Business Machines Corporation | Decode history table for conditional branch instructions |
JPS6014338A (en) | 1983-06-30 | 1985-01-24 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Branch mechanism for computer system |
US4569016A (en) | 1983-06-30 | 1986-02-04 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system |
US4606025A (en) | 1983-09-28 | 1986-08-12 | International Business Machines Corp. | Automatically testing a plurality of memory arrays on selected memory array testers |
US4808988A (en) | 1984-04-13 | 1989-02-28 | Megatek Corporation | Digital vector generator for a graphic display system |
US4868735A (en) | 1984-05-08 | 1989-09-19 | Advanced Micro Devices, Inc. | Interruptible structured microprogrammed sixteen-bit address sequence controller |
US4742451A (en) | 1984-05-21 | 1988-05-03 | Digital Equipment Corporation | Instruction prefetch system for conditional branch instruction for central processor unit |
US5187800A (en) | 1985-01-04 | 1993-02-16 | Sun Microsystems, Inc. | Asynchronous pipelined data processing system |
US5045995A (en) | 1985-06-24 | 1991-09-03 | Vicom Systems, Inc. | Selective operation of processing elements in a single instruction multiple data stream (SIMD) computer system |
US4754398A (en) | 1985-06-28 | 1988-06-28 | Cray Research, Inc. | System for multiprocessor communication using local and common semaphore and information registers |
US4755966A (en) | 1985-06-28 | 1988-07-05 | Hewlett-Packard Company | Bidirectional branch prediction and optimization |
US4777587A (en) | 1985-08-30 | 1988-10-11 | Advanced Micro Devices, Inc. | System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses |
US5021945A (en) | 1985-10-31 | 1991-06-04 | Mcc Development, Ltd. | Parallel processor system for processing natural concurrencies and method therefor |
US4847755A (en) | 1985-10-31 | 1989-07-11 | Mcc Development, Ltd. | Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies |
US4745544A (en) | 1985-12-12 | 1988-05-17 | Texas Instruments Incorporated | Master/slave sequencing processor with forced I/O |
US4724521A (en) | 1986-01-14 | 1988-02-09 | Veri-Fone, Inc. | Method for operating a local terminal to execute a downloaded application program |
US5297260A (en) | 1986-03-12 | 1994-03-22 | Hitachi, Ltd. | Processor having a plurality of CPUS with one CPU being normally connected to common bus |
US5170484A (en) | 1986-09-18 | 1992-12-08 | Digital Equipment Corporation | Massively parallel array processing system |
US4992934A (en) | 1986-12-15 | 1991-02-12 | United Technologies Corporation | Reduced instruction set computing apparatus and methods |
US5073864A (en) | 1987-02-10 | 1991-12-17 | Davin Computer Corporation | Parallel string processor and method for a minicomputer |
US4866664A (en) | 1987-03-09 | 1989-09-12 | Unisys Corporation | Intercomputer communication control apparatus & method |
US5142683A (en) | 1987-03-09 | 1992-08-25 | Unisys Corporation | Intercomputer communication control apparatus and method |
US4926322A (en) * | 1987-08-03 | 1990-05-15 | Compag Computer Corporation | Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management |
US4991078A (en) | 1987-09-29 | 1991-02-05 | Digital Equipment Corporation | Apparatus and method for a pipelined central processing unit in a data processing system |
US4816913A (en) | 1987-11-16 | 1989-03-28 | Technology, Inc., 64 | Pixel interpolation circuitry as for a video signal processor |
US5189636A (en) | 1987-11-16 | 1993-02-23 | Intel Corporation | Dual mode combining circuitry |
US5220669A (en) | 1988-02-10 | 1993-06-15 | International Business Machines Corporation | Linkage mechanism for program isolation |
EP0357768B1 (en) | 1988-03-14 | 1994-03-09 | Unisys Corporation | Record lock processor for multiprocessing data system |
US5056015A (en) | 1988-03-23 | 1991-10-08 | Du Pont Pixel Systems Limited | Architectures for serial or parallel loading of writable control store |
US5165025A (en) | 1988-10-06 | 1992-11-17 | Lass Stanley E | Interlacing the paths after a conditional branch like instruction |
EP0374419A3 (en) | 1988-12-21 | 1991-04-10 | International Business Machines Corporation | Method and apparatus for efficient loop constructs in hardware and microcode |
US5202972A (en) | 1988-12-29 | 1993-04-13 | International Business Machines Corporation | Store buffer apparatus in a multiprocessor system |
US5046000A (en) | 1989-01-27 | 1991-09-03 | International Business Machines Corporation | Single-FIFO high speed combining switch |
US5155854A (en) | 1989-02-03 | 1992-10-13 | Digital Equipment Corporation | System for arbitrating communication requests using multi-pass control unit based on availability of system resources |
US5155831A (en) | 1989-04-24 | 1992-10-13 | International Business Machines Corporation | Data processing system with fast queue store interposed between store-through caches and a main memory |
US5113516A (en) | 1989-07-31 | 1992-05-12 | North American Philips Corporation | Data repacker having controlled feedback shifters and registers for changing data format |
US5168555A (en) | 1989-09-06 | 1992-12-01 | Unisys Corporation | Initial program load control |
US5263169A (en) | 1989-11-03 | 1993-11-16 | Zoran Corporation | Bus arbitration and resource management for concurrent vector signal processor architecture |
DE3942977A1 (en) | 1989-12-23 | 1991-06-27 | Standard Elektrik Lorenz Ag | METHOD FOR RESTORING THE CORRECT SEQUENCE OF CELLS, ESPECIALLY IN AN ATM SWITCHING CENTER, AND OUTPUT UNIT THEREFOR |
US5544337A (en) | 1989-12-29 | 1996-08-06 | Cray Research, Inc. | Vector processor having registers for control by vector resisters |
US5179702A (en) | 1989-12-29 | 1993-01-12 | Supercomputer Systems Limited Partnership | System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling |
US5247671A (en) | 1990-02-14 | 1993-09-21 | International Business Machines Corporation | Scalable schedules for serial communications controller in data processing systems |
EP0446721B1 (en) | 1990-03-16 | 2000-12-20 | Texas Instruments Incorporated | Distributed processing memory |
JPH0799812B2 (en) | 1990-03-26 | 1995-10-25 | 株式会社グラフイックス・コミュニケーション・テクノロジーズ | Signal coding apparatus, signal decoding apparatus, and signal coding / decoding apparatus |
DE69129872T2 (en) | 1990-03-27 | 1999-03-04 | Philips Electronics N.V., Eindhoven | Data processing system with a performance-enhancing instruction cache |
US5210870A (en) | 1990-03-27 | 1993-05-11 | International Business Machines | Database sort and merge apparatus with multiple memory arrays having alternating access |
US5390329A (en) | 1990-06-11 | 1995-02-14 | Cray Research, Inc. | Responding to service requests using minimal system-side context in a multiprocessor environment |
JPH0454652A (en) | 1990-06-25 | 1992-02-21 | Nec Corp | Microcomputer |
AU633724B2 (en) | 1990-06-29 | 1993-02-04 | Digital Equipment Corporation | Interlock queueing |
US5404482A (en) | 1990-06-29 | 1995-04-04 | Digital Equipment Corporation | Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills |
US5347648A (en) | 1990-06-29 | 1994-09-13 | Digital Equipment Corporation | Ensuring write ordering under writeback cache error conditions |
CA2045790A1 (en) | 1990-06-29 | 1991-12-30 | Richard Lee Sites | Branch prediction in high-performance processor |
US5432918A (en) | 1990-06-29 | 1995-07-11 | Digital Equipment Corporation | Method and apparatus for ordering read and write operations using conflict bits in a write queue |
AU630299B2 (en) | 1990-07-10 | 1992-10-22 | Fujitsu Limited | A data gathering/scattering system in a parallel computer |
JP2508907B2 (en) | 1990-09-18 | 1996-06-19 | 日本電気株式会社 | Control method of delayed branch instruction |
US5367678A (en) | 1990-12-06 | 1994-11-22 | The Regents Of The University Of California | Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically |
US5394530A (en) | 1991-03-15 | 1995-02-28 | Nec Corporation | Arrangement for predicting a branch target address in the second iteration of a short loop |
US5956514A (en) | 1991-04-12 | 1999-09-21 | Boeing North American, Inc. | Apparatus and method for multiple processor software development |
KR960001273B1 (en) | 1991-04-30 | 1996-01-25 | 가부시키가이샤 도시바 | Single chip microcomputer |
EP0522513A2 (en) | 1991-07-09 | 1993-01-13 | Hughes Aircraft Company | High speed parallel microcode program controller |
US5255239A (en) | 1991-08-13 | 1993-10-19 | Cypress Semiconductor Corporation | Bidirectional first-in-first-out memory device with transparent and user-testable capabilities |
US5623489A (en) | 1991-09-26 | 1997-04-22 | Ipc Information Systems, Inc. | Channel allocation system for distributed digital switching network |
US5392412A (en) | 1991-10-03 | 1995-02-21 | Standard Microsystems Corporation | Data communication controller for use with a single-port data packet buffer |
GB2260429B (en) | 1991-10-11 | 1995-05-24 | Intel Corp | Versatile cache memory |
US5392391A (en) | 1991-10-18 | 1995-02-21 | Lsi Logic Corporation | High performance graphics applications controller |
US5557766A (en) | 1991-10-21 | 1996-09-17 | Kabushiki Kaisha Toshiba | High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous bank pointers to specify a return bank |
US5640528A (en) * | 1991-10-24 | 1997-06-17 | Intel Corporation | Method and apparatus for translating addresses using mask and replacement value registers |
US5452437A (en) | 1991-11-18 | 1995-09-19 | Motorola, Inc. | Methods of debugging multiprocessor system |
US5442797A (en) | 1991-12-04 | 1995-08-15 | Casavant; Thomas L. | Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging |
JP2823767B2 (en) | 1992-02-03 | 1998-11-11 | 松下電器産業株式会社 | Register file |
KR100309566B1 (en) | 1992-04-29 | 2001-12-15 | 리패치 | Method and apparatus for grouping multiple instructions, issuing grouped instructions concurrently, and executing grouped instructions in a pipeline processor |
US5459842A (en) | 1992-06-26 | 1995-10-17 | International Business Machines Corporation | System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory |
DE4223600C2 (en) | 1992-07-17 | 1994-10-13 | Ibm | Multiprocessor computer system and method for transmitting control information and data information between at least two processor units of a computer system |
US5274770A (en) | 1992-07-29 | 1993-12-28 | Tritech Microelectronics International Pte Ltd. | Flexible register-based I/O microcontroller with single cycle instruction execution |
US5692167A (en) | 1992-07-31 | 1997-11-25 | Intel Corporation | Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor |
US5442756A (en) | 1992-07-31 | 1995-08-15 | Intel Corporation | Branch prediction and resolution apparatus for a superscalar computer processor |
US5481683A (en) | 1992-10-30 | 1996-01-02 | International Business Machines Corporation | Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions |
US5463746A (en) | 1992-10-30 | 1995-10-31 | International Business Machines Corp. | Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes |
US5428779A (en) | 1992-11-09 | 1995-06-27 | Seiko Epson Corporation | System and method for supporting context switching within a multiprocessor system having functional blocks that generate state programs with coded register load instructions |
JPH06161873A (en) | 1992-11-27 | 1994-06-10 | Fujitsu Ltd | Hang-up processings system for plural access points to main memory |
US5450603A (en) | 1992-12-18 | 1995-09-12 | Xerox Corporation | SIMD architecture with transfer register or value source circuitry connected to bus |
DK0627100T3 (en) | 1992-12-23 | 2000-06-26 | Ebauchesfabrik Eta Ag | Low power multitasking controller |
US5404464A (en) | 1993-02-11 | 1995-04-04 | Ast Research, Inc. | Bus control system and method that selectively generate an early address strobe |
US5448702A (en) | 1993-03-02 | 1995-09-05 | International Business Machines Corporation | Adapters with descriptor queue management capability |
DE69429204T2 (en) | 1993-03-26 | 2002-07-25 | Cabletron Systems Inc | Sequence control method and device for a communication network |
US6311286B1 (en) | 1993-04-30 | 2001-10-30 | Nec Corporation | Symmetric multiprocessing system with unified environment and distributed system functions |
WO1994027216A1 (en) | 1993-05-14 | 1994-11-24 | Massachusetts Institute Of Technology | Multiprocessor coupling system with integrated compile and run time scheduling for parallelism |
CA2122182A1 (en) | 1993-05-20 | 1994-11-21 | Rene Leblanc | Method for rapid prototyping of programming problems |
JP3203401B2 (en) | 1993-05-21 | 2001-08-27 | 三菱電機株式会社 | Data processing device |
DE69329059T2 (en) | 1993-06-29 | 2001-03-22 | Alcatel, Paris | Sequential reordering method and apparatus |
US5363448A (en) | 1993-06-30 | 1994-11-08 | United Technologies Automotive, Inc. | Pseudorandom number generation and cryptographic authentication |
JP3452655B2 (en) | 1993-09-27 | 2003-09-29 | 株式会社日立製作所 | Digital signal processor and method of executing instructions using the same |
CA2107299C (en) | 1993-09-29 | 1997-02-25 | Mehrad Yasrebi | High performance machine for switched communications in a heterogenous data processing network gateway |
US6141689A (en) | 1993-10-01 | 2000-10-31 | International Business Machines Corp. | Method and mechanism for allocating switched communications ports in a heterogeneous data processing network gateway |
US5446736A (en) | 1993-10-07 | 1995-08-29 | Ast Research, Inc. | Method and apparatus for connecting a node to a wireless network using a standard protocol |
EP0650117B1 (en) | 1993-10-21 | 2002-04-10 | Sun Microsystems, Inc. | Counterflow pipeline |
DE69415126T2 (en) | 1993-10-21 | 1999-07-08 | Sun Microsystems Inc., Mountain View, Calif. | Counterflow pipeline processor |
US5450351A (en) | 1993-11-19 | 1995-09-12 | International Business Machines Corporation | Content addressable memory implementation with random access memory |
US6116768A (en) * | 1993-11-30 | 2000-09-12 | Texas Instruments Incorporated | Three input arithmetic logic unit with barrel rotator |
US6079014A (en) | 1993-12-02 | 2000-06-20 | Intel Corporation | Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state |
US5848276A (en) | 1993-12-06 | 1998-12-08 | Cpu Technology, Inc. | High speed, direct register access operation for parallel processing units |
US5487159A (en) | 1993-12-23 | 1996-01-23 | Unisys Corporation | System for processing shift, mask, and merge operations in one instruction |
SG52391A1 (en) | 1994-01-03 | 1998-09-28 | Intel Corp | Method and apparatus for implementing a four stage branch resolution system in a computer processor |
US5490204A (en) | 1994-03-01 | 1996-02-06 | Safco Corporation | Automated quality assessment system for cellular networks |
US5835755A (en) | 1994-04-04 | 1998-11-10 | At&T Global Information Solutions Company | Multi-processor computer system for operating parallel client/server database processes |
JP3547482B2 (en) | 1994-04-15 | 2004-07-28 | 株式会社日立製作所 | Information processing equipment |
AUPM519694A0 (en) | 1994-04-19 | 1994-05-12 | Griffith University | Method for testing and debugging computer programs |
US5659722A (en) | 1994-04-28 | 1997-08-19 | International Business Machines Corporation | Multiple condition code branching system in a multi-processor environment |
US5542088A (en) | 1994-04-29 | 1996-07-30 | Intergraph Corporation | Method and apparatus for enabling control of task execution |
US5721870A (en) | 1994-05-25 | 1998-02-24 | Nec Corporation | Lock control for a shared main storage data processing system |
US5544236A (en) | 1994-06-10 | 1996-08-06 | At&T Corp. | Access to unsubscribed features |
US5574922A (en) | 1994-06-17 | 1996-11-12 | Apple Computer, Inc. | Processor with sequences of processor instructions for locked memory updates |
US5781774A (en) | 1994-06-29 | 1998-07-14 | Intel Corporation | Processor having operating modes for an upgradeable multiprocessor computer system |
FR2722041B1 (en) | 1994-06-30 | 1998-01-02 | Samsung Electronics Co Ltd | HUFFMAN DECODER |
JP3810449B2 (en) | 1994-07-20 | 2006-08-16 | 富士通株式会社 | Queue device |
US5860085A (en) | 1994-08-01 | 1999-01-12 | Cypress Semiconductor Corporation | Instruction set for a content addressable memory array with read/write circuits and an interface register logic block |
US5655132A (en) | 1994-08-08 | 1997-08-05 | Rockwell International Corporation | Register file with multi-tasking support |
US5555432A (en) * | 1994-08-19 | 1996-09-10 | Intel Corporation | Circuit and method for scheduling instructions by predicting future availability of resources required for execution |
US5640538A (en) | 1994-08-22 | 1997-06-17 | Adaptec, Inc. | Programmable timing mark sequencer for a disk drive |
US5748950A (en) | 1994-09-20 | 1998-05-05 | Intel Corporation | Method and apparatus for providing an optimized compare-and-branch instruction |
US5717760A (en) | 1994-11-09 | 1998-02-10 | Channel One Communications, Inc. | Message protection system and method |
JP3169779B2 (en) | 1994-12-19 | 2001-05-28 | 日本電気株式会社 | Multi-thread processor |
US5610864A (en) | 1994-12-23 | 1997-03-11 | Micron Technology, Inc. | Burst EDO memory device with maximized write cycle timing |
US5550816A (en) | 1994-12-29 | 1996-08-27 | Storage Technology Corporation | Method and apparatus for virtual switching |
JPH08272648A (en) | 1994-12-29 | 1996-10-18 | Hitachi Ltd | Method for automatically generating debugging command file and device for automatically regenerating break point in debugging command file |
US5812811A (en) | 1995-02-03 | 1998-09-22 | International Business Machines Corporation | Executing speculative parallel instructions threads with forking and inter-thread communication |
US5784712A (en) | 1995-03-01 | 1998-07-21 | Unisys Corporation | Method and apparatus for locally generating addressing information for a memory access |
US6081880A (en) * | 1995-03-09 | 2000-06-27 | Lsi Logic Corporation | Processor having a scalable, uni/multi-dimensional, and virtually/physically addressed operand register file |
US5649157A (en) | 1995-03-30 | 1997-07-15 | Hewlett-Packard Co. | Memory controller with priority queues |
TW360852B (en) | 1995-04-12 | 1999-06-11 | Matsushita Electric Ind Co Ltd | Pipeline processor |
US5651137A (en) | 1995-04-12 | 1997-07-22 | Intel Corporation | Scalable cache attributes for an input/output bus |
US5886992A (en) | 1995-04-14 | 1999-03-23 | Valtion Teknillinen Tutkimuskeskus | Frame synchronized ring system and method |
US5758184A (en) | 1995-04-24 | 1998-05-26 | Microsoft Corporation | System for performing asynchronous file operations requested by runnable threads by processing completion messages with different queue thread and checking for completion by runnable threads |
US5704054A (en) | 1995-05-09 | 1997-12-30 | Yale University | Counterflow pipeline processor architecture for semi-custom application specific IC's |
US5592622A (en) | 1995-05-10 | 1997-01-07 | 3Com Corporation | Network intermediate system with message passing architecture |
GB9509988D0 (en) | 1995-05-17 | 1995-07-12 | Sgs Thomson Microelectronics | Matrix transposition |
GB9509983D0 (en) | 1995-05-17 | 1995-07-12 | Sgs Thomson Microelectronics | Replication of data |
GB9509989D0 (en) | 1995-05-17 | 1995-07-12 | Sgs Thomson Microelectronics | Manipulation of data |
GB9509987D0 (en) | 1995-05-17 | 1995-07-12 | Sgs Thomson Microelectronics | Manipulation of data |
JPH08320797A (en) | 1995-05-24 | 1996-12-03 | Fuji Xerox Co Ltd | Program control system |
US5680564A (en) | 1995-05-26 | 1997-10-21 | National Semiconductor Corporation | Pipelined processor with two tier prefetch buffer structure and method with bypass |
US5644780A (en) | 1995-06-02 | 1997-07-01 | International Business Machines Corporation | Multiple port high speed register file with interleaved write ports for use with very long instruction word (vlin) and n-way superscaler processors |
US5828746A (en) | 1995-06-07 | 1998-10-27 | Lucent Technologies Inc. | Telecommunications network |
US5828863A (en) | 1995-06-09 | 1998-10-27 | Canon Information Systems, Inc. | Interface device connected between a LAN and a printer for outputting formatted debug information about the printer to the printer |
US5541920A (en) | 1995-06-15 | 1996-07-30 | Bay Networks, Inc. | Method and apparatus for a delayed replace mechanism for a streaming packet modification engine |
KR0180169B1 (en) | 1995-06-30 | 1999-05-01 | 배순훈 | A variable length coder |
GB9513515D0 (en) | 1995-07-03 | 1995-09-06 | Sgs Thomson Microelectronics | Expansion of data |
US5613071A (en) | 1995-07-14 | 1997-03-18 | Intel Corporation | Method and apparatus for providing remote memory access in a distributed memory multiprocessor system |
GB9514695D0 (en) | 1995-07-18 | 1995-09-13 | Sgs Thomson Microelectronics | Combining data values |
GB9514684D0 (en) | 1995-07-18 | 1995-09-13 | Sgs Thomson Microelectronics | An arithmetic unit |
US5680641A (en) | 1995-08-16 | 1997-10-21 | Sharp Microelectronics Technology, Inc. | Multiple register bank system for concurrent I/O operation in a CPU datapath |
US5900025A (en) * | 1995-09-12 | 1999-05-04 | Zsp Corporation | Processor having a hierarchical control register file and methods for operating the same |
US5940612A (en) | 1995-09-27 | 1999-08-17 | International Business Machines Corporation | System and method for queuing of tasks in a multiprocessing system |
US5875470A (en) | 1995-09-28 | 1999-02-23 | International Business Machines Corporation | Multi-port multiple-simultaneous-access DRAM chip |
US5689566A (en) | 1995-10-24 | 1997-11-18 | Nguyen; Minhtam C. | Network with secure communications sessions |
US5809530A (en) | 1995-11-13 | 1998-09-15 | Motorola, Inc. | Method and apparatus for processing multiple cache misses using reload folding and store merging |
KR0150072B1 (en) | 1995-11-30 | 1998-10-15 | 양승택 | Device for controlling memory data path in parallel processing computer system |
US5796413A (en) | 1995-12-06 | 1998-08-18 | Compaq Computer Corporation | Graphics controller utilizing video memory to provide macro command capability and enhanched command buffering |
US5940866A (en) | 1995-12-13 | 1999-08-17 | International Business Machines Corporation | Information handling system having a local address queue for local storage of command blocks transferred from a host processing side |
US5699537A (en) | 1995-12-22 | 1997-12-16 | Intel Corporation | Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions |
US5787454A (en) | 1995-12-27 | 1998-07-28 | Intel Corporation | Recorder buffer with interleaving mechanism for accessing a multi-parted circular memory array |
ATE191819T1 (en) | 1995-12-29 | 2000-04-15 | Tixi Com Gmbh | METHOD AND MICROCOMPUTER SYSTEM FOR AUTOMATIC, SECURE AND DIRECT DATA TRANSMISSION |
US5819080A (en) | 1996-01-02 | 1998-10-06 | Advanced Micro Devices, Inc. | Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer system employing the microprocessor |
US6088783A (en) | 1996-02-16 | 2000-07-11 | Morton; Steven G | DPS having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word |
US5802373A (en) | 1996-01-29 | 1998-09-01 | Digital Equipment Corporation | Method for providing a pipeline interpreter for a variable length instruction set |
US6201807B1 (en) | 1996-02-27 | 2001-03-13 | Lucent Technologies | Real-time hardware method and apparatus for reducing queue processing |
US5761507A (en) | 1996-03-05 | 1998-06-02 | International Business Machines Corporation | Client/server architecture supporting concurrent servers within a server with a transaction manager providing server/connection decoupling |
US5809235A (en) | 1996-03-08 | 1998-09-15 | International Business Machines Corporation | Object oriented network event management framework |
US5784649A (en) | 1996-03-13 | 1998-07-21 | Diamond Multimedia Systems, Inc. | Multi-threaded FIFO pool buffer and bus transfer control system |
US5797043A (en) | 1996-03-13 | 1998-08-18 | Diamond Multimedia Systems, Inc. | System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs |
US6199133B1 (en) | 1996-03-29 | 2001-03-06 | Compaq Computer Corporation | Management communication bus for networking devices |
KR100219597B1 (en) | 1996-03-30 | 1999-09-01 | 윤종용 | Queuing control method in cd-rom drive |
US5944816A (en) | 1996-05-17 | 1999-08-31 | Advanced Micro Devices, Inc. | Microprocessor configured to execute multiple threads including interrupt service routines |
JPH1091443A (en) | 1996-05-22 | 1998-04-10 | Seiko Epson Corp | Information processing circuit, microcomputer and electronic equipment |
US5946487A (en) | 1996-06-10 | 1999-08-31 | Lsi Logic Corporation | Object-oriented multi-media architecture |
KR980004067A (en) | 1996-06-25 | 1998-03-30 | 김광호 | Data Transceiver and Method in Multiprocessor System |
JP3541335B2 (en) | 1996-06-28 | 2004-07-07 | 富士通株式会社 | Information processing apparatus and distributed processing control method |
US5937187A (en) | 1996-07-01 | 1999-08-10 | Sun Microsystems, Inc. | Method and apparatus for execution and preemption control of computer process entities |
US6023742A (en) | 1996-07-18 | 2000-02-08 | University Of Washington | Reconfigurable computing architecture for providing pipelined data paths |
JP3745039B2 (en) | 1996-08-01 | 2006-02-15 | 株式会社ルネサステクノロジ | Microprocessor with delayed instructions |
US5745913A (en) | 1996-08-05 | 1998-04-28 | Exponential Technology, Inc. | Multi-processor DRAM controller that prioritizes row-miss requests to stale banks |
US6058465A (en) | 1996-08-19 | 2000-05-02 | Nguyen; Le Trong | Single-instruction-multiple-data processing in a multimedia signal processor |
US6061711A (en) | 1996-08-19 | 2000-05-09 | Samsung Electronics, Inc. | Efficient context saving and restoring in a multi-tasking computing system environment |
CN100373331C (en) | 1996-08-27 | 2008-03-05 | 松下电器产业株式会社 | Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream |
US5812868A (en) | 1996-09-16 | 1998-09-22 | Motorola Inc. | Method and apparatus for selecting a register file in a data processing system |
US5937177A (en) | 1996-10-01 | 1999-08-10 | Sun Microsystems, Inc. | Control structure for a high-speed asynchronous pipeline |
US6072781A (en) | 1996-10-22 | 2000-06-06 | International Business Machines Corporation | Multi-tasking adapter for parallel network applications |
JPH10177482A (en) | 1996-10-31 | 1998-06-30 | Texas Instr Inc <Ti> | Microprocessor and operating method |
US5860158A (en) | 1996-11-15 | 1999-01-12 | Samsung Electronics Company, Ltd. | Cache control unit with a cache request transaction-oriented protocol |
US5857104A (en) | 1996-11-26 | 1999-01-05 | Hewlett-Packard Company | Synthetic dynamic branch prediction |
US6009505A (en) | 1996-12-02 | 1999-12-28 | Compaq Computer Corp. | System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot |
CN1153133C (en) | 1996-12-09 | 2004-06-09 | 松下电器产业株式会社 | Information processing device by using small scale hardware for high percentage of hits branch foncast |
US6212542B1 (en) | 1996-12-16 | 2001-04-03 | International Business Machines Corporation | Method and system for executing a program within a multiscalar processor by processing linked thread descriptors |
US5905876A (en) | 1996-12-16 | 1999-05-18 | Intel Corporation | Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system |
US5946222A (en) | 1996-12-20 | 1999-08-31 | Oak Technology, Inc. | Method and apparatus for performing a masked byte addition operation |
US6098110A (en) | 1996-12-30 | 2000-08-01 | Compaq Computer Corporation | Network switch with a multiple bus structure and a bridge interface for transferring network data between different buses |
US6029228A (en) | 1996-12-31 | 2000-02-22 | Texas Instruments Incorporated | Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions |
US5854922A (en) | 1997-01-16 | 1998-12-29 | Ford Motor Company | Micro-sequencer apparatus and method of combination state machine and instruction memory |
US5961628A (en) | 1997-01-28 | 1999-10-05 | Samsung Electronics Co., Ltd. | Load and store unit for a vector processor |
US6356551B1 (en) | 1997-02-14 | 2002-03-12 | Advanced Micro Devices, Inc. | Method and network switch having dual forwarding models with a virtual lan overlay |
US5872963A (en) | 1997-02-18 | 1999-02-16 | Silicon Graphics, Inc. | Resumption of preempted non-privileged threads with no kernel intervention |
US6256115B1 (en) | 1997-02-21 | 2001-07-03 | Worldquest Network, Inc. | Facsimile network |
US6269391B1 (en) | 1997-02-24 | 2001-07-31 | Novell, Inc. | Multi-processor scheduling kernel |
US5742587A (en) | 1997-02-28 | 1998-04-21 | Lanart Corporation | Load balancing port switching hub |
CN1113289C (en) | 1997-03-04 | 2003-07-02 | 松下电器产业株式会社 | Processor capable of high effective actuating asynchronous event mission in multiple asynchronous missions |
US5905889A (en) | 1997-03-20 | 1999-05-18 | International Business Machines Corporation | Resource management system using next available integer from an integer pool and returning the integer thereto as the next available integer upon completion of use |
US5996068A (en) * | 1997-03-26 | 1999-11-30 | Lucent Technologies Inc. | Method and apparatus for renaming registers corresponding to multiple thread identifications |
US6298370B1 (en) | 1997-04-04 | 2001-10-02 | Texas Instruments Incorporated | Computer operating process allocating tasks between first and second processors at run time based upon current processor load |
US5983274A (en) | 1997-05-08 | 1999-11-09 | Microsoft Corporation | Creation and use of control information associated with packetized network data by protocol drivers and device drivers |
US6141765A (en) | 1997-05-19 | 2000-10-31 | Gigabus, Inc. | Low power, high speed communications bus |
KR100212064B1 (en) | 1997-05-21 | 1999-08-02 | 윤종용 | 2n x n multiplexer switch architecture |
US6009515A (en) | 1997-05-30 | 1999-12-28 | Sun Microsystems, Inc. | Digital data processing system including efficient arrangement to support branching within trap shadows |
GB2326253A (en) | 1997-06-10 | 1998-12-16 | Advanced Risc Mach Ltd | Coprocessor data access control |
US6139199A (en) | 1997-06-11 | 2000-10-31 | Sun Microsystems, Inc. | Fast just-in-time (JIT) scheduler |
US6092158A (en) | 1997-06-13 | 2000-07-18 | Intel Corporation | Method and apparatus for arbitrating between command streams |
US6182177B1 (en) | 1997-06-13 | 2001-01-30 | Intel Corporation | Method and apparatus for maintaining one or more queues of elements such as commands using one or more token queues |
US6067585A (en) | 1997-06-23 | 2000-05-23 | Compaq Computer Corporation | Adaptive interface controller that can operate with segments of different protocol and transmission rates in a single integrated device |
US5993627A (en) | 1997-06-24 | 1999-11-30 | Large Scale Biology Corporation | Automated system for two-dimensional electrophoresis |
US5870597A (en) * | 1997-06-25 | 1999-02-09 | Sun Microsystems, Inc. | Method for speculative calculation of physical register addresses in an out of order processor |
KR100216371B1 (en) | 1997-06-30 | 1999-08-16 | 윤종용 | Large scale atm switch with fault tolerant scheme and self routing method in 2nxn multiplexing switches |
US6393483B1 (en) | 1997-06-30 | 2002-05-21 | Adaptec, Inc. | Method and apparatus for network interface card load balancing and port aggregation |
US5887134A (en) | 1997-06-30 | 1999-03-23 | Sun Microsystems | System and method for preserving message order while employing both programmed I/O and DMA operations |
US5938736A (en) | 1997-06-30 | 1999-08-17 | Sun Microsystems, Inc. | Search engine architecture for a high performance multi-layer switch element |
US6385720B1 (en) | 1997-07-14 | 2002-05-07 | Matsushita Electric Industrial Co., Ltd. | Branch prediction method and processor using origin information, relative position information and history information |
US6247025B1 (en) | 1997-07-17 | 2001-06-12 | International Business Machines Corporation | Locking and unlocking mechanism for controlling concurrent access to objects |
US6157988A (en) | 1997-08-01 | 2000-12-05 | Micron Technology, Inc. | Method and apparatus for high performance branching in pipelined microsystems |
US6141348A (en) | 1997-08-25 | 2000-10-31 | Cisco Technology, Inc. | Constant-time programmable field extraction system and method |
US6243735B1 (en) | 1997-09-01 | 2001-06-05 | Matsushita Electric Industrial Co., Ltd. | Microcontroller, data processing system and task switching control method |
US5926646A (en) | 1997-09-11 | 1999-07-20 | Advanced Micro Devices, Inc. | Context-dependent memory-mapped registers for transparent expansion of a register file |
US6014729A (en) | 1997-09-29 | 2000-01-11 | Firstpass, Inc. | Shared memory arbitration apparatus and method |
US6223208B1 (en) | 1997-10-03 | 2001-04-24 | International Business Machines Corporation | Moving data in and out of processor units using idle register/storage functional units |
US5943491A (en) | 1997-10-20 | 1999-08-24 | Sun Microsystems, Inc. | Control circuit of mutual exclusion elements |
US6697935B1 (en) | 1997-10-23 | 2004-02-24 | International Business Machines Corporation | Method and apparatus for selecting thread switch events in a multithreaded processor |
US6085294A (en) | 1997-10-24 | 2000-07-04 | Compaq Computer Corporation | Distributed data dependency stall mechanism |
US6061710A (en) | 1997-10-29 | 2000-05-09 | International Business Machines Corporation | Multithreaded processor incorporating a thread latch register for interrupt service new pending threads |
US5915123A (en) | 1997-10-31 | 1999-06-22 | Silicon Spice | Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements |
IL135953A0 (en) | 1997-11-07 | 2001-05-20 | Bops Inc | Methods and apparatus for efficient synchronous mimd operations with ivliw pe-to-pe communication |
US6279066B1 (en) | 1997-11-14 | 2001-08-21 | Agere Systems Guardian Corp. | System for negotiating access to a shared resource by arbitration logic in a shared resource negotiator |
US6223277B1 (en) | 1997-11-21 | 2001-04-24 | Texas Instruments Incorporated | Data processing circuit with packed data structure capability |
US6360262B1 (en) | 1997-11-24 | 2002-03-19 | International Business Machines Corporation | Mapping web server objects to TCP/IP ports |
US5923872A (en) | 1997-11-26 | 1999-07-13 | Digital Equipment Corporation | Apparatus for sampling instruction operand or result values in a processor pipeline |
US6070231A (en) | 1997-12-02 | 2000-05-30 | Intel Corporation | Method and apparatus for processing memory requests that require coherency transactions |
US6144669A (en) | 1997-12-12 | 2000-11-07 | Newbridge Networks Corporation | Prioritized PVC management queues for improved frame processing capabilities |
US5948081A (en) | 1997-12-22 | 1999-09-07 | Compaq Computer Corporation | System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed |
US6259699B1 (en) | 1997-12-30 | 2001-07-10 | Nexabit Networks, Llc | System architecture for and method of processing packets and/or cells in a common switch |
JPH11203860A (en) | 1998-01-07 | 1999-07-30 | Nec Corp | Semiconductor memory device |
US6134665A (en) | 1998-01-20 | 2000-10-17 | Digital Equipment Corporation | Computer with remote wake up and transmission of a status packet when the computer fails a self test |
US6145054A (en) | 1998-01-21 | 2000-11-07 | Sun Microsystems, Inc. | Apparatus and method for handling multiple mergeable misses in a non-blocking cache |
US6138254A (en) | 1998-01-22 | 2000-10-24 | Micron Technology, Inc. | Method and apparatus for redundant location addressing using data compression |
US6230119B1 (en) | 1998-02-06 | 2001-05-08 | Patrick Michael Mitchell | Integrated circuit with embedded emulator and emulation system for use with such an integrated circuit |
US6415338B1 (en) | 1998-02-11 | 2002-07-02 | Globespan, Inc. | System for writing a data value at a starting address to a number of consecutive locations equal to a segment length identifier |
US5970013A (en) | 1998-02-26 | 1999-10-19 | Lucent Technologies Inc. | Adaptive addressable circuit redundancy method and apparatus with broadcast write |
US6205468B1 (en) | 1998-03-10 | 2001-03-20 | Lucent Technologies, Inc. | System for multitasking management employing context controller having event vector selection by priority encoding of contex events |
US6446190B1 (en) | 1998-03-12 | 2002-09-03 | Bops, Inc. | Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor |
US6279113B1 (en) | 1998-03-16 | 2001-08-21 | Internet Tools, Inc. | Dynamic signature inspection-based network intrusion detection |
US6005575A (en) | 1998-03-23 | 1999-12-21 | Microsoft Corporation | Foreground window determination through process and thread initialization |
US6052769A (en) | 1998-03-31 | 2000-04-18 | Intel Corporation | Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction |
US6223238B1 (en) | 1998-03-31 | 2001-04-24 | Micron Electronics, Inc. | Method of peer-to-peer mastering over a computer bus |
US6079008A (en) | 1998-04-03 | 2000-06-20 | Patton Electronics Co. | Multiple thread multiple data predictive coded parallel processing system and method |
KR100280460B1 (en) | 1998-04-08 | 2001-02-01 | 김영환 | Data processing device and its multiple thread processing method |
FR2777672B1 (en) * | 1998-04-15 | 2000-05-19 | Bull Sa | METHOD FOR ACCESSING THE PHYSICAL AND VIRTUAL ADDRESSING DIFFERENTLY IN THE SAME MEMORY AREA OF A DIGITAL PROCESSING MACHINE AND A MACHINE IMPLEMENTING THIS METHOD |
US6115777A (en) | 1998-04-21 | 2000-09-05 | Idea Corporation | LOADRS instruction and asynchronous context switch |
US6275508B1 (en) | 1998-04-21 | 2001-08-14 | Nexabit Networks, Llc | Method of and system for processing datagram headers for high speed computer network interfaces at low clock speeds, utilizing scalable algorithms for performing such network header adaptation (SAPNA) |
US6408325B1 (en) * | 1998-05-06 | 2002-06-18 | Sun Microsystems, Inc. | Context switching technique for processors with large register files |
US6496847B1 (en) | 1998-05-15 | 2002-12-17 | Vmware, Inc. | System and method for virtualizing computer systems |
US6092127A (en) | 1998-05-15 | 2000-07-18 | Hewlett-Packard Company | Dynamic allocation and reallocation of buffers in links of chained DMA operations by receiving notification of buffer full and maintaining a queue of buffers available |
US6275505B1 (en) | 1998-05-30 | 2001-08-14 | Alcatel Canada Inc. | Method and apparatus for packetizing data into a data stream |
US6157955A (en) | 1998-06-15 | 2000-12-05 | Intel Corporation | Packet processing system including a policy engine having a classification unit |
US6272616B1 (en) | 1998-06-17 | 2001-08-07 | Agere Systems Guardian Corp. | Method and apparatus for executing multiple instruction streams in a digital processor with multiple data paths |
US6434145B1 (en) | 1998-06-22 | 2002-08-13 | Applied Micro Circuits Corporation | Processing of network data by parallel processing channels |
US6836838B1 (en) | 1998-06-29 | 2004-12-28 | Cisco Technology, Inc. | Architecture for a processor complex of an arrayed pipelined processing engine |
US6101599A (en) | 1998-06-29 | 2000-08-08 | Cisco Technology, Inc. | System for context switching between processing elements in a pipeline of processing elements |
US6195739B1 (en) | 1998-06-29 | 2001-02-27 | Cisco Technology, Inc. | Method and apparatus for passing data among processor complex stages of a pipelined processing engine |
US6145123A (en) | 1998-07-01 | 2000-11-07 | Advanced Micro Devices, Inc. | Trace on/off with breakpoint register |
US6356994B1 (en) | 1998-07-09 | 2002-03-12 | Bops, Incorporated | Methods and apparatus for instruction addressing in indirect VLIW processors |
US6373848B1 (en) | 1998-07-28 | 2002-04-16 | International Business Machines Corporation | Architecture for a multi-port adapter with a single media access control (MAC) |
US6073215A (en) | 1998-08-03 | 2000-06-06 | Motorola, Inc. | Data processing system having a data prefetch mechanism and method therefor |
US6160562A (en) | 1998-08-18 | 2000-12-12 | Compaq Computer Corporation | System and method for aligning an initial cache line of data read from local memory by an input/output device |
IL131839A (en) | 1998-09-10 | 2004-12-15 | Dsp Group Ltd | Method for reducing code size using programmable delay slots |
US6505229B1 (en) | 1998-09-25 | 2003-01-07 | Intelect Communications, Inc. | Method for allowing multiple processing threads and tasks to execute on one or more processor units for embedded real-time processor systems |
US6356962B1 (en) | 1998-09-30 | 2002-03-12 | Stmicroelectronics, Inc. | Network device and method of controlling flow of data arranged in frames in a data-based network |
US6347344B1 (en) | 1998-10-14 | 2002-02-12 | Hitachi, Ltd. | Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor |
US6560629B1 (en) | 1998-10-30 | 2003-05-06 | Sun Microsystems, Inc. | Multi-thread processing |
US6212611B1 (en) | 1998-11-03 | 2001-04-03 | Intel Corporation | Method and apparatus for providing a pipelined memory controller |
US6230261B1 (en) | 1998-12-02 | 2001-05-08 | I. P. First, L.L.C. | Method and apparatus for predicting conditional branch instruction outcome based on branch condition test type |
US6718457B2 (en) | 1998-12-03 | 2004-04-06 | Sun Microsystems, Inc. | Multiple-thread processor for threaded software applications |
US6230230B1 (en) | 1998-12-03 | 2001-05-08 | Sun Microsystems, Inc. | Elimination of traps and atomics in thread synchronization |
US6389449B1 (en) | 1998-12-16 | 2002-05-14 | Clearwater Networks, Inc. | Interstream control and communications for multi-streaming digital processors |
US6401155B1 (en) | 1998-12-22 | 2002-06-04 | Philips Electronics North America Corporation | Interrupt/software-controlled thread processing |
US6378125B1 (en) | 1999-02-22 | 2002-04-23 | International Business Machines Corporation | Debugger thread identification points |
US6378124B1 (en) | 1999-02-22 | 2002-04-23 | International Business Machines Corporation | Debugger thread synchronization control points |
US6574702B2 (en) | 1999-02-23 | 2003-06-03 | Netlogic Microsystems, Inc. | Method and apparatus for determining an exact match in a content addressable memory device |
US6338133B1 (en) | 1999-03-12 | 2002-01-08 | International Business Machines Corporation | Measured, allocation of speculative branch instructions to processor execution units |
US6304956B1 (en) | 1999-03-25 | 2001-10-16 | Rise Technology Company | Using two barrel shifters to implement shift, rotate, rotate with carry, and shift double as specified by the X86 architecture |
US6314510B1 (en) | 1999-04-14 | 2001-11-06 | Sun Microsystems, Inc. | Microprocessor with reduced context switching overhead and corresponding method |
US6256713B1 (en) | 1999-04-29 | 2001-07-03 | International Business Machines Corporation | Bus optimization with read/write coherence including ordering responsive to collisions |
US6351808B1 (en) * | 1999-05-11 | 2002-02-26 | Sun Microsystems, Inc. | Vertically and horizontally threaded processor with multidimensional storage for storing thread data |
US6631422B1 (en) | 1999-08-26 | 2003-10-07 | International Business Machines Corporation | Network adapter utilizing a hashing function for distributing packets to multiple processors for parallel processing |
US6606704B1 (en) | 1999-08-31 | 2003-08-12 | Intel Corporation | Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode |
US6427196B1 (en) | 1999-08-31 | 2002-07-30 | Intel Corporation | SRAM controller for parallel processor architecture including address and command queue and arbiter |
US6983350B1 (en) | 1999-08-31 | 2006-01-03 | Intel Corporation | SDRAM controller for parallel processor architecture |
US6668317B1 (en) | 1999-08-31 | 2003-12-23 | Intel Corporation | Microengine for parallel processor architecture |
US7191309B1 (en) | 1999-09-01 | 2007-03-13 | Intel Corporation | Double shift instruction for micro engine used in multithreaded parallel processor architecture |
WO2001016714A1 (en) | 1999-09-01 | 2001-03-08 | Intel Corporation | Fast write instruction for micro engine used in multithreaded parallel processor architecture |
US6543049B1 (en) | 1999-09-03 | 2003-04-01 | International Business Machines Corporation | Ranked break points and method for debugging a computer program |
US6681341B1 (en) | 1999-11-03 | 2004-01-20 | Cisco Technology, Inc. | Processor isolation method for integrated multi-processor systems |
US6523108B1 (en) | 1999-11-23 | 2003-02-18 | Sony Corporation | Method of and apparatus for extracting a string of bits from a binary bit string and depositing a string of bits onto a binary bit string |
US6532509B1 (en) | 1999-12-22 | 2003-03-11 | Intel Corporation | Arbitrating command requests in a parallel multi-threaded processing system |
US6694380B1 (en) | 1999-12-27 | 2004-02-17 | Intel Corporation | Mapping requests from a processing unit that uses memory-mapped input-output space |
US6560667B1 (en) | 1999-12-28 | 2003-05-06 | Intel Corporation | Handling contiguous memory references in a multi-queue system |
US6307789B1 (en) | 1999-12-28 | 2001-10-23 | Intel Corporation | Scratchpad memory |
US6324624B1 (en) | 1999-12-28 | 2001-11-27 | Intel Corporation | Read lock miss control and queue management |
US6625654B1 (en) | 1999-12-28 | 2003-09-23 | Intel Corporation | Thread signaling in multi-threaded network processor |
US6463072B1 (en) | 1999-12-28 | 2002-10-08 | Intel Corporation | Method and apparatus for sharing access to a bus |
US6631430B1 (en) | 1999-12-28 | 2003-10-07 | Intel Corporation | Optimizations to receive packet status from fifo bus |
US6661794B1 (en) | 1999-12-29 | 2003-12-09 | Intel Corporation | Method and apparatus for gigabit packet assignment for multithreaded packet processing |
US6976095B1 (en) | 1999-12-30 | 2005-12-13 | Intel Corporation | Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch |
US6584522B1 (en) | 1999-12-30 | 2003-06-24 | Intel Corporation | Communication between processors |
US6631462B1 (en) | 2000-01-05 | 2003-10-07 | Intel Corporation | Memory shared between processing threads |
US7681018B2 (en) * | 2000-08-31 | 2010-03-16 | Intel Corporation | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
US20020053017A1 (en) | 2000-09-01 | 2002-05-02 | Adiletta Matthew J. | Register instructions for a multithreaded processor |
US6629237B2 (en) | 2000-09-01 | 2003-09-30 | Intel Corporation | Solving parallel problems employing hardware multi-threading in a parallel processing environment |
US6560671B1 (en) | 2000-09-11 | 2003-05-06 | Intel Corporation | Method and apparatus for accelerating exchange or swap instructions using a register alias table (RAT) and content addressable memory (CAM) with logical register numbers as input addresses |
US6784889B1 (en) | 2000-12-13 | 2004-08-31 | Micron Technology, Inc. | Memory system and method for improved utilization of read and write bandwidth of a graphics processing system |
US7020871B2 (en) | 2000-12-21 | 2006-03-28 | Intel Corporation | Breakpoint method for parallel hardware threads in multithreaded processor |
US6862676B1 (en) | 2001-01-16 | 2005-03-01 | Sun Microsystems, Inc. | Superscalar processor having content addressable memory structures for determining dependencies |
US7487505B2 (en) | 2001-08-27 | 2009-02-03 | Intel Corporation | Multithreaded microprocessor with register allocation based on number of active threads |
US6934951B2 (en) | 2002-01-17 | 2005-08-23 | Intel Corporation | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section |
US7181594B2 (en) | 2002-01-25 | 2007-02-20 | Intel Corporation | Context pipelines |
US7437724B2 (en) | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
US6971103B2 (en) | 2002-10-15 | 2005-11-29 | Sandbridge Technologies, Inc. | Inter-thread communications using shared interrupt register |
-
2000
- 2000-08-31 US US10/070,091 patent/US7546444B1/en not_active Expired - Fee Related
- 2000-08-31 WO PCT/US2000/023993 patent/WO2001016702A1/en active Application Filing
-
2009
- 2009-06-03 US US12/477,287 patent/US7991983B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357617A (en) * | 1991-11-22 | 1994-10-18 | International Business Machines Corporation | Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor |
US5933627A (en) * | 1996-07-01 | 1999-08-03 | Sun Microsystems | Thread switch on blocked load or store using instruction thread field |
US6092175A (en) * | 1998-04-02 | 2000-07-18 | University Of Washington | Shared register storage mechanisms for multithreaded computer systems with out-of-order execution |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1530761A2 (en) * | 2001-09-19 | 2005-05-18 | Bay Microsystems, Inc. | Vertical instruction and data processing in a network processor architecture |
EP1530761A4 (en) * | 2001-09-19 | 2008-01-23 | Bay Microsystems Inc | Vertical instruction and data processing in a network processor architecture |
SG155038A1 (en) * | 2001-09-28 | 2009-09-30 | Consentry Networks Inc | A multi-threaded packet processing engine for stateful packet processing |
CN100440151C (en) * | 2002-01-25 | 2008-12-03 | 英特尔公司 | Context pipelines |
US7702004B2 (en) | 2002-12-09 | 2010-04-20 | Alexander Roger Deas | Simultaneous bidirectional differential signalling interface |
CN111459630A (en) * | 2020-03-24 | 2020-07-28 | 华东计算技术研究所(中国电子科技集团公司第三十二研究所) | Network processor adopting hardware multithreading mechanism |
CN111459630B (en) * | 2020-03-24 | 2023-12-08 | 华东计算技术研究所(中国电子科技集团公司第三十二研究所) | Network processor adopting hardware multithreading mechanism |
Also Published As
Publication number | Publication date |
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US7546444B1 (en) | 2009-06-09 |
US20090307469A1 (en) | 2009-12-10 |
US7991983B2 (en) | 2011-08-02 |
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