WO1998047151A1 - Electrically erasable nonvolatile memory - Google Patents
Electrically erasable nonvolatile memory Download PDFInfo
- Publication number
- WO1998047151A1 WO1998047151A1 PCT/US1998/007082 US9807082W WO9847151A1 WO 1998047151 A1 WO1998047151 A1 WO 1998047151A1 US 9807082 W US9807082 W US 9807082W WO 9847151 A1 WO9847151 A1 WO 9847151A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- well
- biasing
- bias
- drain
- vcc
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
Definitions
- This invention relates generally to nonvolatile memories and particularly to electrically erasable nonvolatile memories.
- Nonvolatile memory cells are advantageous since they retain recorded information even when the power to the memory is turned off.
- nonvolatile memories including erasable programmable read only memories (EPROMs) , electrically erasable and programmable read only memories (EEPROMs) and flash EEPROM memories.
- EPROMs are erasable through light exposure but are electrically programmable by channel hot electron injection onto a floating gate.
- Conventional EEPROMs have the same programming functionality, but instead of being light erasable they can be erased and programmed by electron tunneling. Thus, information may be stored in these memories, retained when the power is off, and the memories may be erased for reprogramming, as necessary, using appropriate techniques.
- Flash EEPROMs may be block erased, typically giving them better read access times than regular EEPROMs .
- flash memories have gained considerable popularity.
- flash memories are often utilized to provide on-chip memory for microcontrollers, modems and
- flash memories and EEPROMs are closely related, in many instances flash memories are preferred because their smaller cell size means that they can be made more economically. However, flash memories and EEPROMs often have very similar cell attributes.
- EEPROMs When EEPROMs are erased, one or more of cells are erased in one operation. A high positive potential is applied to the cell sources and/or drain while the control electrode and the substrate are grounded. As a result, negative charges on the floating gate are drawn to the source and/or drain region by Fowler-Nordheim tunneling. This technique is effective where the dielectric between the floating gate electrode and the source and/or drain regions is very thin.
- a nonvolatile memory cell is formed in a P-type region.
- the memory cell also includes a transistor having a floating gate and a control gate and a pair of doped regions acting as a source and a drain formed in the P-type region.
- the floating gate is erasable by tunneling of electrons from the floating gate to one of the doped regions.
- the P-type region and one of the doped regions are biased separately by positive potentials. The difference between the doped region bias and the P-type region potential is less than Vcc and greater than zero.
- the control gate is negatively biased.
- a method for erasing a memory cell having a control gate, a floating gate, a channel, and a pair of doped regions acting as a source and drain formed in a P- well in turn formed in an N-well includes the step of negatively biasing the control gate.
- the P-well and one of the doped regions are positively biased such that the doped region bias minus the P-well bias is less than Vcc and more than zero .
- Figure 2 is a schematic depiction of a cell configuration for another embodiment.
- a memory cell 10 shown in Fig. 1, includes a control gate 12 and a floating gate 14. This structure is advantageously implemented on a semiconductor layer 30 having situated thereon an electrically isolated floating gate 14.
- the particular cell structure is not critical and the present invention could be implemented using a variety of memory cell structures, including, for example, split gate and stacked gate cell structures.
- the substrate 30, which may be a P-type semiconductor, includes a heavily doped source region 16 and a heavily doped drain region 18.
- the regions 16 and 18 could also include lightly doped drain (LDD) extensions (not shown) .
- LDD lightly doped drain
- the drain bias potential 24, the substrate bias potential 26, the source potential 20 and gate bias potential 36 may be tailored to maximize the performance of the cell .
- the cell 10 may be read and programmed using any known technique.
- the bias potentials illustrated in Figure 1 are for implementing a Fowler-Nordheim tunneling of electrons from the floating gate 14 primarily to the drain 18, as indicated by the arrow "e" .
- the control gate 12 is forced to a negative voltage of from -7 to -14 volts, for example, with the source 20 floating, or at potential equal to the P-well potential.
- the process for forming the cell can be made more compatible with standard logic processes.
- the drain diffusion 18, and the substrate 30 they are biased to a positive potential close to Vcc or higher.
- Vcc is determined by the particular technology utilized. For example, it could be 5.0 to 2.5 volts with present technologies. This reduces the electric field across the junction between the N+ diffusion 18 and the substrate 30. The reduced GIDL current and the lateral electric field prevents acceleration of hot hole trapping in the gate oxide under the floating gate 14.
- the drain 18 is preferably not biased to a voltage higher than the substrate 30 to such an extent that gate induced drain leakage (GIDL) becomes a problem.
- GIDL gate induced drain leakage
- the drain 18 bias is advantageously not higher than the substrate 30 bias by more than about one to two volts. See S. Parke, et al . ; "Design for Suppression of Gate-Induced Drain Leakage in LDD MOSFETs using a Quasi-two-dimensional Analytical Model," IEEE Transactions on Electron Devices, vol. 39, p. 1694-1703, 1992, hereby expressly incorporated by reference herein.
- the drain 18 bias significantly exceeds the substrate 30 bias, hot hole trapping may occur due to the lateral junction field acceleration.
- the drain 18 bias minus the substrate 30 bias be greater than zero and less than Vcc.
- the ability to apply a positive voltage to the substrate 30 is facilitated by using a P-well 30 embedded in an N-well 32, as shown in Figure 2.
- the P-well voltage 26 is preferably equal to or less than N-well potential 28 to avoid P-well/N-well forward biasing.
- applying a positive voltage of Vcc or higher to the P-well 30, N-well 32 and the drain 18 can eliminate hot hole trapping induced by GIDL while allowing the drain 18 voltage to be raised to Vcc or higher.
- the source potential 20 may be allowed to float.
- the drain bias minus the P-well bias is greater than zero and less than Vcc.
- the voltage across the capacitor 33 is the difference between the floating gate 14 potential on the one hand and the diffusion 18 and P-well 30 potentials. When the difference exceeds 8 to 10 volts, sufficient tunneling current is generated and the floating gate 14 can be erased to a negative potential in the time frame of a few milliseconds to a few seconds, depending on the tunneling oxide 42 thickness.
- Electrons tunnel to the drain region 18 (drain erase) .
- the tunneling current depends on the voltage from the floating gate 14 to the drain 18.
- a source erase mechanism may be provided instead of the drain erase mechanism. During source erase, the drain potential would be allowed to float.
- the cells 10 and 10a may be formed using conventional process technologies such as a double poly, single metal CMOS process.
- CMOS process CMOS process
- the illustrative parameters set forth herein contemplate a .35 ⁇ m or lower feature size with Vcc potentials of 1.8 volts. As the technology permits lowering voltages and smaller feature sizes, the parameters herein would scale accordingly.
- the starting substrate material is typically P-type (100) silicon, for example having a resistivity in the range of 10-20 ohm-cm.
- the P-well 30 is embedded in an N- well 32 in the so-called triple well process.
- the P-well 30 has a typical well depth of, for example, 2 to 4 urn with an average doping concentration, for example, in the range of 1 x 10 ⁇ to 5 x 10 16 atoms per cubic centimeter.
- the N-well 30 has a typical well depth of, for example, 4-8 urn.
- the doping concentration may be from 4 x 10 15 to 1 x 10 16 atoms per cubic centimeter.
- the triple well is formed by the P-well 30 counterdoping the N-well 32.
- the formation of the elements in the triple well is as follows.
- An N-well implant is done, for example, with phosphorous P31 with a typical dose of 1 to 1.5 x 10 13 atoms per square centimeter and an energy from about 160 to lOOKev.
- the N-well implant is driven using a high temperature step which may typically be 6 to 12 hours at 1125 to 1150° C.
- the N-well 32 is then counterdoped with a P-well implant.
- Typical dosages for the P-well implant could be 1.5 to 2.5 x 10 13 atoms per square centimeter with an energy of 30Kev to 180Kev using a species such as boron Bll.
- the N-well 32 and P-well 30 are then driven, typically 6 to 10 hours at 1125 to 1150°C. This sets the wells to the desired doping concentrations and depths.
- field oxide and field isolation follows using a standard logic field process.
- the field oxide thickness and field doping may be slightly adjusted to satisfy the cell programming requirements.
- a memory cell implant may be performed. For example, a Bll implant at 30 to 50Kev with a dose of 1.0 to 3.5 x 10 13 atoms per square centimeter may be done through a sacrificial oxide.
- the gate is then formed. For example, an 85 to 100 Angstrom dry oxide may be grown across the wafer. A dry oxide is grown, for example, at 900°C in partial oxygen followed by a 975 to 1050 °C anneal.
- the floating gate 14 may then be formed of poly- silicon, suicide or metals. If polysilicon is used, it can be 1600 Angstroms thick, and POCL3 doped at 870 to 1000°C.
- the interpoly dielectric is formed of an oxide- nitride-oxide sandwich (ONO) with the lower oxide being from 60 to 80 Angstroms, the nitride layer having a thickness of from 90 to 180 Angstroms and the upper oxide being from 30 to 40 Angstroms.
- the polysilicon (poly 2) for the control gate 12 may then be deposited and suicided if desired.
- the gates are patterned and defined using standard self-aligned gate etching techniques. With the completion of these capacitor and transistor structures, all subsequent processing for contacts and interconnect layers follows standard logic rear end processing.
- the present invention is particularly desirable with technologies having .35 ⁇ m feature sizes or less with a Vcc of 3.3 volts or less.
- GIDL creates a hole trapping problem which adversely affects reliability and causes drain leakage which adversely affects the power supply.
- the P-well potential and drain voltage are different voltages, the GIDL leakage current can be made tolerable, while optimizing the P-well potential for tunneling erasure.
- the P-well potential can be selected to allow a less negative control gate voltage while achieving excellent GIDL and erase conditions.
- the lower control gate potential makes the technology more compatible with standard logic procedures.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002286125A CA2286125A1 (en) | 1997-04-11 | 1998-04-07 | Electrically erasable nonvolatile memory |
EP98914631A EP0974147A1 (en) | 1997-04-11 | 1998-04-07 | Electrically erasable nonvolatile memory |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US83885697A | 1997-04-11 | 1997-04-11 | |
US08/838,856 | 1997-04-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998047151A1 true WO1998047151A1 (en) | 1998-10-22 |
Family
ID=25278228
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/007082 WO1998047151A1 (en) | 1997-04-11 | 1998-04-07 | Electrically erasable nonvolatile memory |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0974147A1 (en) |
JP (1) | JPH10335504A (en) |
KR (1) | KR20010006135A (en) |
CN (1) | CN1252156A (en) |
CA (1) | CA2286125A1 (en) |
TW (1) | TW389998B (en) |
WO (1) | WO1998047151A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999031669A1 (en) * | 1997-12-18 | 1999-06-24 | Advanced Micro Devices, Inc. | Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices |
WO2000068952A1 (en) * | 1999-05-06 | 2000-11-16 | Advanced Micro Devices, Inc. | Ramped or stepped gate channel erase for flash memory application |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100454117B1 (en) * | 2001-10-22 | 2004-10-26 | 삼성전자주식회사 | Methods of operating a non-volatile memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) gate structure |
US6876582B2 (en) * | 2002-05-24 | 2005-04-05 | Hynix Semiconductor, Inc. | Flash memory cell erase scheme using both source and channel regions |
WO2004006264A2 (en) * | 2002-07-08 | 2004-01-15 | Koninklijke Philips Electronics N.V. | Erasable and programmable non-volatile cell |
CN100334715C (en) * | 2003-01-14 | 2007-08-29 | 力旺电子股份有限公司 | Non-volatile storage element |
CN101091252B (en) * | 2004-12-28 | 2012-09-05 | 斯班逊有限公司 | Semiconductor device and operation control method for same |
KR101043383B1 (en) * | 2009-12-23 | 2011-06-21 | 주식회사 하이닉스반도체 | Semiconductor memory device |
CN102446719B (en) * | 2011-09-08 | 2014-05-28 | 上海华力微电子有限公司 | Method for increasing writing speed of floating body dynamic random access memory |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5235544A (en) * | 1990-11-09 | 1993-08-10 | John Caywood | Flash EPROM cell and method for operating same |
US5457652A (en) * | 1994-04-01 | 1995-10-10 | National Semiconductor Corporation | Low voltage EEPROM |
JPH0927560A (en) * | 1995-07-13 | 1997-01-28 | Toshiba Corp | Nonvolatile semiconductor memory device |
-
1998
- 1998-04-07 EP EP98914631A patent/EP0974147A1/en not_active Withdrawn
- 1998-04-07 CN CN98804053A patent/CN1252156A/en active Pending
- 1998-04-07 WO PCT/US1998/007082 patent/WO1998047151A1/en not_active Application Discontinuation
- 1998-04-07 KR KR1019997009213A patent/KR20010006135A/en not_active Application Discontinuation
- 1998-04-07 CA CA002286125A patent/CA2286125A1/en not_active Abandoned
- 1998-04-10 TW TW087105486A patent/TW389998B/en active
- 1998-04-10 JP JP11604298A patent/JPH10335504A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5235544A (en) * | 1990-11-09 | 1993-08-10 | John Caywood | Flash EPROM cell and method for operating same |
US5457652A (en) * | 1994-04-01 | 1995-10-10 | National Semiconductor Corporation | Low voltage EEPROM |
JPH0927560A (en) * | 1995-07-13 | 1997-01-28 | Toshiba Corp | Nonvolatile semiconductor memory device |
US5657271A (en) * | 1995-07-13 | 1997-08-12 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device in which band to band tunneling current is suppressed |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999031669A1 (en) * | 1997-12-18 | 1999-06-24 | Advanced Micro Devices, Inc. | Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices |
US6236596B1 (en) | 1997-12-18 | 2001-05-22 | Advanced Micro Devices, Inc. | Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices |
WO2000068952A1 (en) * | 1999-05-06 | 2000-11-16 | Advanced Micro Devices, Inc. | Ramped or stepped gate channel erase for flash memory application |
US6188609B1 (en) | 1999-05-06 | 2001-02-13 | Advanced Micro Devices, Inc. | Ramped or stepped gate channel erase for flash memory application |
Also Published As
Publication number | Publication date |
---|---|
KR20010006135A (en) | 2001-01-26 |
CA2286125A1 (en) | 1998-10-22 |
CN1252156A (en) | 2000-05-03 |
JPH10335504A (en) | 1998-12-18 |
EP0974147A1 (en) | 2000-01-26 |
TW389998B (en) | 2000-05-11 |
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