US7538754B2 - Signal circuit, display apparatus including same, and method for driving data line - Google Patents
Signal circuit, display apparatus including same, and method for driving data line Download PDFInfo
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- US7538754B2 US7538754B2 US10/995,196 US99519604A US7538754B2 US 7538754 B2 US7538754 B2 US 7538754B2 US 99519604 A US99519604 A US 99519604A US 7538754 B2 US7538754 B2 US 7538754B2
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- 238000000034 method Methods 0.000 title claims description 14
- 238000005070 sampling Methods 0.000 description 117
- 230000003071 parasitic effect Effects 0.000 description 31
- 239000004973 liquid crystal related substance Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 10
- 238000009825 accumulation Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 101000832687 Cavia porcellus 3-alpha-hydroxysteroid sulfotransferase Proteins 0.000 description 5
- 101000643834 Cavia porcellus 3-beta-hydroxysteroid sulfotransferase Proteins 0.000 description 5
- 102100028633 Cdc42-interacting protein 4 Human genes 0.000 description 5
- 102100028075 Fibroblast growth factor 6 Human genes 0.000 description 5
- 101000766830 Homo sapiens Cdc42-interacting protein 4 Proteins 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 239000011159 matrix material Substances 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 101000831940 Homo sapiens Stathmin Proteins 0.000 description 1
- 102100024237 Stathmin Human genes 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
Definitions
- the present invention relates to a signal circuit for use in a display apparatus such as a liquid crystal display panel, and to a method for driving data lines of the signal circuit.
- a liquid crystal display apparatus (i) which includes a switch provided in every source line via which a signal (video signal) from a signal line is to be written, and (ii) which carries out a point-at-a-time driving with respect to each pixel, a method for simultaneously supplying signals of two or more channels is adopted so as to lower a driving frequency of the source line.
- FIG. 5 is a block diagram illustrating a conventional liquid crystal display apparatus in which signals (video signals) that are supplied via two independent signal channels are supplied to the source lines via sampling switches, and the point-at-a-time drive is carried out.
- a display section 195 of the liquid crystal display apparatus includes a gate driver 185 , a timing signal generating circuit 177 , and a shift register 170 having output stages SiR 155 and SiR 156 .
- the timing signal generating circuit 177 outputs a start pulse HST 10 .
- the output stages SiR 155 and SiR 156 output sampling pulses Vh 20 .
- signals of two independent channels are outputted. Specifically, the a-channel signals that respectively correspond to R (red), G (green), and B (blue) are sent to signal lines SLRa 149 through SLBa 151 , respectively. Also, the b-channel signals that respectively correspond to R, G, and B are sent to signal lines SLRb 152 through SLBa 154 , respectively.
- a plurality of gate lines G 190 , G 191 , . . . , and the source lines SR 101 through SB 112 are wired in a matrix manner.
- the gate line G 191 intersects with the source lines SR 101 through SB 112 , respectively, and in their intersections, thin film transistors TR 125 through TB 136 serving as a switching element are provided, respectively.
- the thin film transistors TR 125 through TB 136 have (i) respective gates connected to the gate line G 191 , and (ii) sources connected to the source lines SR 101 through SB 112 , respectively, and (iii) drains connected to the pixel capacitance PR 113 through PB 124 , respectively.
- the source lines SR 101 through SB 112 are divided into four groups Gr 154 , Gr 155 , Gr 156 , and Gr 157 so that each group is constituted by three source lines (that correspond to one pixel).
- the groups Gr 154 , Gr 155 , Gr 156 , and Gr 157 are further divided into two blocks B 158 and B 159 so that each block is constituted by two groups (that correspond to two pixels) adjacent to each other.
- the source lines SR 101 through SB 112 are connected to the signal lines SLRa 149 through SLBb 154 , via sampling switches SWR 137 through SWB 148 , respectively.
- the sampling switches SWR 137 through SWB 148 may be realized by transistors, respectively, and are provided so as to correspond to the source lines SR 101 through SB 112 , respectively.
- the three source lines SR 101 , SG 102 , and SB 103 are connected to the a-channel signal lines SLRa 149 , SLGa 150 , and SLBa 151 , via the sampling switches SWR 137 , SWG 138 , and the SWB 139 , respectively.
- the three source lines SR 104 , SG 105 , and SB 106 are connected to the b-channel signal lines SLRb 152 , SLGb 153 , and SLBb 154 , via the sampling switches SWR 140 , SWG 141 , and the SWB 142 , respectively.
- the groups Gr 154 (the a-channel) and Gr 155 (the b-channel), which are adjacent to each other, constitute the block B 158 .
- each of the six sampling switches SWR 137 through SWB 142 in the block B 158 is connected to the output stage SiR 155 of the shift register 170 , and each ON/OFF of the six sampling switches SWR 137 through SWB 142 is controlled in response to the sampling pulse Vh 20 outputted from the output stage SiR 155 . Further, in response to the sampling pulses Vh 20 , the signals of the two channels are sent from the respective signal lines (the a-channel: SLRa 149 through SLBa 151 ; the b-channel: SLRb 152 through SLBb 154 ).
- the three source lines SR 107 , SG 108 , and SB 109 are connected to the a-channel signal lines SLRa 149 , SLGa 150 , and SLBa 151 , via the sampling switches SWR 143 , SWG 144 , and SWB 145 , respectively.
- the three source lines SR 110 , SG 111 , and SB 112 are connected to the b-channel signal lines SLRb 152 , SLGb 153 , and SLBb 154 , via the sampling switches SWR 146 , SWG 147 , and SWB 148 , respectively.
- the groups Gr 156 (the a-channel) and Gr 157 (the b-channel), which are adjacent to each other, constitute the block B 159 .
- each of the six sampling switches SWR 143 through SWB 148 of the block B 159 is connected to the output stage SiR 156 of the shift register 170 , and each ON/OFF of the six sampling switches SWR 143 through SWB 148 is controlled in response to the sampling pulse Vh 20 outputted from the output stage SiR 156 . Further, in response to the sampling pulses Vh 20 , the signals of the two systems are sent from the signal lines (the a-channel: SLRa 149 through SLBa 151 ; the b-channel: SLRb 152 through SLBb 154 ), respectively.
- the output stage SiR 155 or SiR 156 sends, at the same timing, the sampling pulses (selection signals) Vh 20 to the sampling switches (such as the sampling switch 137 ) for every block (or for every group). Accordingly, the signals which are supplied via the signal lines (such as the signal line SLRa 149 ) are written, via the source lines that correspond to the sampling switches, in the pixel capacitance (such as the pixel capacitance PR 113 ), respectively.
- FIG. 6 is a timing chart illustrating the twelve sampling switches SWR 137 through SWB 148 during an odd-numbered frame period and an even-numbered frame period, the switches SWR 137 through SWB 148 belonging to the block B 158 or B 159 , each block corresponding to two pixels.
- FIG. 6 also illustrates electric potential states (writing states of the signals) of the respective twelve source lines SR 101 through SB 112 that belong to the block 158 or 159 , and that correspond to four pixels.
- T is a period (that corresponds to one cycle of the timing signal) in which the signals are written in two pixels.
- frame period indicates time required for scanning all the gate lines G 190 , . . . , in the display section 195 (i.e., a period of time required for scanning one screen).
- the signals which are supplied via the signal lines SLRa 149 through SLBb 154 are written, at the same timing, in the pixel capacitance PR 113 through PB 118 , via the source lines SR 101 through SB 106 that are connected to the sampling switches SWR 137 through SWB 142 , respectively.
- a timing signal (not shown) is outputted.
- (i) simultaneously turned OFF are the sampling switches SWR 137 through SWB 142 of the group Gr 154 or Gr 155 , each group belonging to the block B 158 , and (ii) simultaneously selected (turned ON) are the sampling switches SWR 143 through SWB 148 of the group Gr 156 or Gr 157 , each belonging to the block B 159 .
- the signals which are supplied via the signal lines SLRa 149 through SLBb 154 are written, at the same timing, in the pixel capacitance PR 119 through PB 124 , via the source lines SR 107 through SB 112 that are connected to the sampling switches SWR 143 through SWB 148 , respectively.
- the source line SB 106 edge source line in the block B 158
- the adjacent block B 159 changes in its electric potential due to a parasitic capacitance between the source lines SB 106 and SR 107 (i.e., electric charge of the parasitic capacitance transfers to (jumps into) the source line SB 106 ).
- the source line SB 112 changes in its electric potential due to parasitic capacitance between the source lines SB 112 and SR 161 . This gives rise to the changes in electric potential which has been written in the pixel capacitance PB 118 and PB 124 .
- FIG. 7 schematically shows the parasitic capacitance C 201 and C 202 , the parasitic capacitance C 201 existing between the source line SR 107 and the source line SB 106 (an electrode on a side of the source line of the pixel capacitance PB 118 ), and the parasitic capacitance C 202 existing between the source lines SB 112 and SR 161 .
- the source line SB 106 connected to the sampling switch SWB 142 receives the signal (electric potential) via the signal line SLBb 154 during the period of time from the time t 0 to the time t 1 .
- the sampling switch SWR 143 which belongs to the block B 159 adjacent to the block B 158 is turned OFF. This causes the source line SR 107 connected to the sampling switch SWR 143 to keep electric potential which was given one horizontal period ago.
- an electric potential difference becomes large between the source line SR 107 and the source line SB 106 (the electrode on the side of the pixel capacitance PB 118 ) and, the source line SB 106 receiving a new current signal (electric potential), whereas the source line SR 107 keeping the electric potential which was given one horizontal period ago.
- This causes the large parasitic capacitance (accumulation of electric charge; see C 201 in FIG. 7 ) between the source lines SB 106 and SR 107 .
- FIG. 6 schematically shows (i) the change in electric potential of the source line SB 106 from the time t 1 on, and (ii) the change in electric potential of the source line SB 112 from the time t 2 on (see the electric potential change indicated by the arrows in FIG. 6 ).
- parasitic capacitance (such as the parasitic capacitance C 201 or C 202 ) occurs between two source lines (like between the source lines SB 106 and SR 107 , or between the source lines SB 112 and SR 161 ) which belong to respective different groups, and which are disposed at a “boundary” between the groups adjacent to each other such as the groups Gr 155 and Gr 156 .
- the parasitic capacitance causes the changes in electric potential of end portions of the source lines (SB 106 and SB 112 ), each of the end portions being opposite to a selection direction (i.e., a direction in which the sampling switches shift).
- the present invention is made to solve the foregoing conventional problems, and its object is to provide a signal circuit and a liquid crystal display apparatus for uniformizing, over an entire display section, changes in electric potential of source lines due to parasitic capacitance so that it is difficult for display unevenness having a vertical-striped shape to be noticeable due to the change in electric potential.
- a signal circuit of the present invention includes: (1) a plurality of signal sources; (2) a plurality of data lines to which the signal sources supply signals, respectively; and (3) driving means for driving the data lines, the data lines being divided into a plurality of groups, each of the groups including at least one data line, adjacent groups in the groups constituting one block, the signal sources supplying the signals, at same timing, to the data lines that belong to a group selected by the driving means, respectively, wherein: the driving means selects groups which belong to a clump of blocks including a first block, and a second block adjacent to the first block so that: (i) during a first predetermined period, the driving means simultaneously selects groups that belong to the first block, and simultaneously selects groups that belong to the second block, and (ii) during a second predetermined period subsequent to the first predetermined period, the driving means selects groups one by one from groups disposed at respective ends of the clump of blocks, simultaneously selects adjacent groups that belong to different blocks, and selects remaining groups one by one.
- the data lines of the groups which belong to a clump of blocks including the first block, and the second block adjacent to the first block are driven as follows.
- the driving means simultaneously selects a plurality of groups (hereinafter, referred to as “a first start group through a first terminal group” in this order in a scanning direction) that belong to the first (arbitrary) block.
- the signals are supplied, at the same timing, from the signal sources to the respective data lines provided in the first start group through the first terminal group.
- the driving means simultaneously selects all of the groups (hereinafter, referred to as “a second start group through a second terminal group” in this order in the scanning direction) that belong to the second block adjacent to the first block.
- the signals are supplied, at the same timing, from the signal sources to the respective data lines provided in the second start group through the second terminal group.
- the data lines of the groups that belong to the clump of blocks are driven as follows.
- the first start group disposed at an end of the clump of blocks is selected, and the signals are supplied, at the same timing, to respective data lines provided in the first start group.
- the groups are selected one by one up to the group which is one group before the first terminal group, and the signals are supplied, at the same timing, to respective data lines provided in the selected group.
- the first terminal group and the second start group are simultaneously selected, and the signals are supplied, at the same timing, to respective data lines provided in the first terminal group and the second start group.
- the remaining groups i.e., the groups provided from the next group of the second start group to the second terminal group are selected one by one, and the signals are supplied, at the same timing, to respective data lines provided in the remaining groups.
- the groups are selected in the above-described manner. This causes the data lines to be driven (i.e., causes the signals to be supplied from the signal sources). On this account, the following effect is obtained.
- a plurality of the groups that belong to the first block are simultaneously selected, and the signals are supplied, at the same timing, from the signal sources to the respective data lines (hereinafter, referred to as “a start data line through a terminal data line” in the scanning direction) provided in each of the groups of the first block.
- a start data line through a terminal data line in the scanning direction
- the respective data lines hereinafter, referred to as “a start data line through a terminal data line” in the scanning direction
- the terminal data line of the first terminal group receives new signal electric potential
- the start data line of the second start group adjacent to the first terminal group keeps signal electric potential which the start data line has received before. This causes an electric potential difference between the terminal data line of the first terminal group and the start data line of the second start group, thereby causing parasitic capacitance (accumulation of electric charge) to occur between the terminal data line and the start data line.
- the groups that belong to the second block are simultaneously selected, and the start data line of the second start group receives new signal electric potential.
- This causes the reduction of the electric potential difference between the data lines (i.e., between the start data line of the second start group and the terminal data line of the first terminal group).
- This causes the electric charge accumulated in the parasitic capacitance to transfer to (jump into) the terminal data line of the first terminal group, thereby causing the change in electric potential in the terminal data line of the first terminal group.
- a change in electric potential occurs in the terminal data line of the second terminal group.
- the change in electric potential occurs in the terminal data line of the terminal group of each block.
- the first terminal group and the second start group are simultaneously selected, and the remaining groups are selected one by one.
- the change in electric potential occurs in the terminal data line of the group which had been selected one group before the group which was selected. This is because, when a group was selected, the parasitic capacitance, between the start data line of the group which was selected and the terminal data line of the group which had been selected one group before the group which was selected, causes the change in electric potential in the terminal data line of the group which had been selected one group before the group which was selected.
- the terminal data lines of the respective groups have a uniform change in electric potential during such one period.
- the data line is used as a source line for writing a signal (electric potential) in a pixel of a display apparatus
- the adverse effect causing only terminal data lines of specific groups to have changes in electric potential, respectively, during the first and second predetermined periods.
- the adverse effect causing the display unevenness having a vertical-striped shape to be enhanced for every several data lines (for every several pixels). This allows the display unevenness not to be noticeable over the entire display screen (to be difficult to visually recognize), thereby improving display quality.
- FIG. 1 is a block diagram illustrating a display section of a liquid crystal display apparatus in accordance with the present invention.
- FIG. 2( a ) and FIG. 2( b ) are explanatory diagrams illustrating (i) timing of ON/OFF of sampling switches of the liquid crystal display apparatus of the present invention, and (ii) changes in electric potential of respective source lines.
- FIG. 3 is a block diagram illustrating a timing signal generating circuit of the liquid crystal display apparatus in accordance with the present invention.
- FIG. 4 is an explanatory block diagram illustrating parasitic capacitance existing in the display section of the liquid crystal display apparatus in accordance with the present invention.
- FIG. 5 is a block diagram illustrating a display section of a conventional liquid crystal display apparatus.
- FIG. 6 is an explanatory diagram illustrating (i) timing of ON/OFF of sampling switches in the conventional liquid crystal display apparatus, and (ii) changes in electric potential of respective source lines.
- FIG. 7 is an explanatory block diagram illustrating parasitic capacitance existing in the display section unit of the conventional liquid crystal display apparatus.
- FIG. 1 is a block diagram illustrating a display section of a liquid crystal display apparatus in accordance with the present invention.
- a display section 95 includes (i) a control circuit (not shown); (ii) a gate driver 85 ; (iii) a timing signal generating circuit 77 (driving means); (iv) a shift register 70 (driving means) including output stages SiR 55 through SiR 58 ; (v) signal lines (signal sources) SLRa 49 through SLBa 51 (first signal channel; first through third signal sources) and signal lines (signal sources) SLRb 52 through SLBb 54 (second signal channel; fourth through sixth signal sources); (vi) a plurality of gate lines G 90 , G 91 , . . .
- the gate lines G 90 , G 91 , . . . , in a row direction and the source lines SR 1 through SB 12 in a column direction are provided so as to intersect with each other in a matrix manner.
- the thin film transistors TR 25 through TB 36 switching element
- the thin film transistors TR 25 through TB 36 have (i) gates connected to the gate line G 91 , respectively, and (ii) sources connected to the source lines SR 1 through SB 12 , respectively, and (iii) drains each connected to one electrode of the respective pixel capacitance PR 13 through PB 24 .
- each of the other electrodes of the pixel capacitance PR 13 through PB 24 is connected to a common voltage (VCOM).
- R, G, and B in the reference symbols correspond to Red, Green, and Blue, respectively.
- SR indicates a source line that corresponds to red.
- PR indicates pixel capacitance that corresponds to red.
- SLR indicates a signal line that corresponds to red.
- order of colors that correspond to source lines in each block is R, G, B, R, G, and B.
- the gate driver 85 outputs sampling pulses (selection signal) for the gate lines G 90 , G 91 , . . . , in accordance with a vertical signal or the like which is sent from the control circuit (not shown). This allows the gate lines G 90 , G 91 , . . . , to be sequentially driven (selected).
- the timing signal generating circuit 77 outputs two kinds of start pulses HST 1 and HST 2 in accordance with a horizontal signal or the like which is sent from the control circuit.
- the start pulse HST 1 is supplied to the output stages SiR 55 and SiR 57 of the shift register 70
- the start pulse HST 2 is supplied to the output stages SiR 56 and SiR 58 .
- the output stages 55 through 58 of the shift register 70 outputs sampling pulses Vh 61 through Vh 64 in accordance with the start pulses HST 1 and HST 2 , respectively.
- the sampling pulses Vh 61 through Vh 64 control ON/OFF of the sampling switches SWR 37 through the SWB 48 .
- signals of the independent two channels are outputted. Specifically, from the signal lines SLRa 49 through SLBa 51 , a-channel signals that correspond to R, G, and B, respectively are outputted. Also, from the signal lines SLRb 52 through SLRb 54 , b-channel signals that correspond to R, G, and B, respectively are outputted.
- the source lines SR 1 through SB 12 are divided into four groups Gr 54 , Gr 55 , Gr 56 , and Gr 57 so that each group is constituted by three source lines which correspond to one pixel. Further, one block such as the block B 58 or B 59 is constituted by two groups (which correspond to two pixels) adjacent to each other. Further, the source lines SR 1 through SB 12 are connected to the signal lines SLRa 49 through SLBb 54 , via the sampling switches SWR 37 through SWB 48 , respectively.
- the three source lines SR 1 , SG 2 , and SB 3 are connected to the signal lines SLRa 49 , SLGa 50 , and SLBa 51 of the a-channel, via the sampling switches SWR 37 , SWG 38 , and SWB 39 , respectively.
- the three sampling switches SWR 37 through SWB 39 are connected to the output stage SiR 55 of the shift register 70 .
- Each ON/OFF of the sampling switches SWR 37 through SWB 39 is controlled by the sampling pulse Vh 61 , which is sent from the output stage SiR 55 .
- the a-channel signals are sent from the signal lines SLRa 49 through SLBa 51 in response to the sampling pulse Vh 61 (i.e., in response to the ON/OFF of the sampling switches SWR 37 through SWB 39 ), respectively.
- the a-channel signals are written in the source lines SR 1 through SB 3 , respectively.
- the three source lines SR 4 , SG 5 , and SB 6 are connected to the signal lines SLRb 52 , SLGb 53 , SLBb 54 of the b-channel, via the sampling switches SWR 40 , SWG 41 , and SWB 42 , respectively.
- the three sampling switches SWR 40 through SWB 42 are connected to the output stage SiR 56 of the shift register 70 .
- Each ON/OFF of the sampling switches SWR 40 through SWB 42 is controlled in response to the sampling pulse Vh 62 , which is sent from the output stage SiR 56 .
- the b-channel signals are sent from the signal lines SLRb 52 through SLBb 54 in response to the sampling pulse Vh 62 (i.e., in response to the ON/OFF of the sampling switches SWR 40 through SWB 42 ), respectively.
- the b-channel signals are written in the source lines SR 4 through SB 6 , respectively.
- the groups Gr 54 (a-channel) and Gr 55 (b-channel) adjacent to each other constitute the block B 58 .
- the three source lines SR 7 , SG 8 , and SB 9 are connected to the signal lines SLRa 49 , SLGa 50 , and SLBa 51 of the a-channel, via the sampling switches SWR 43 , SWG 44 , and SWB 45 , respectively.
- the three sampling switches SWR 43 through SWB 45 are connected to the output stage SiR 57 of the shift register 70 .
- Each ON/OFF of the sampling switches SWR 43 through SWB 45 is controlled in response to the sampling pulse Vh 63 which is sent from the output stage SiR 57 .
- the a-channel signals are sent from the signal lines SLRa 49 through SLBa 51 in response to the sampling pulse Vh 63 (i.e., in response to the ON/OFF of the sampling switches SWR 43 through SWB 45 ), respectively.
- the a-channel signals are written in the source lines SR 7 through SB 9 , respectively.
- the three source lines SR 10 , SG 11 , and SB 12 are connected to the signal lines SLRb 52 , SLGb 53 , SLBb 54 of the b-channel, via the sampling switches SWR 46 , SWG 47 , and SWB 48 , respectively.
- the three sampling switches SWR 46 through SWB 48 are connected to the output stage SiR 58 of the shift register 70 .
- Each ON/OFF of the sampling switches SWR 46 through SWB 48 is controlled in response to the sampling pulse Vh 64 , which is sent from the output stage SiR 58 .
- the b-channel signals are sent from the signal lines SLRb 52 through SLBb 54 in response to the sampling pulse Vh 64 (i.e., in response to the ON/OFF of the sampling switches SWR 46 through SWB 48 ), respectively.
- the b-channel signals are written in the source lines SR 10 through SB 12 , respectively.
- the group Gr 56 (a-channel), and the group Gr 57 (b-channel) adjacent to each other constitute the block B 59 .
- FIG. 3 is a block diagram illustrating the timing signal generating circuit 77 (flip-flop circuit) for generating the two types of the start pulses HST 1 and HST 2 .
- the timing signal generating circuit 77 includes: (i) nine D-type flip-flop circuits DFF 67 through DFF 69 , DFF 71 through DFF 74 , DFF 78 and DFF 79 ; (ii) two T-type flip-flop circuits TFF 81 and TFF 82 ; (iii) four AND gates 83 , 84 , 87 , and 88 ; (iv) an exclusive-OR gate 86 ; (v) an OR gate 89 ; and (vi) an inverter 92 .
- outputs of the six logic circuits (i) through (vi) are indicated by f 83 , f 84 , f 87 and f 88 for the AND gates; f 86 for the Exclusive-OR gate; f 89 for the OR gate, respectively.
- f 83 , f 84 , f 87 and f 88 for the AND gates
- f 86 for the Exclusive-OR gate
- f 89 for the OR gate
- a first input pulse (horizontal start pulse) HST is supplied to the D-type flip-flop circuit DFF 67 .
- an output signal from the D-type flip-flop circuit DFF 67 is supplied to the D-type flip-flop circuit DFF 68 .
- An inverted output signal of the D-type flip-flop circuit DFF 68 is supplied to one input terminal (first input terminal) of the AND gate 83 .
- the output signal of the D-type flip-flop circuit DFF 67 is also supplied to another input terminal (second input terminal) of the AND gate 83 .
- the AND gate 83 outputs the output signal f 83 as an output pulse HSTP.
- a second input pulse (vertical start pulse) VST is supplied to the D-type flip-flop circuit DFF 69 .
- An output signal from the D-type flip-flop circuit DFF 69 is supplied to the D-type flip-flop circuit DFF 71 .
- An inverted output signal of the D-type flip-flop circuit DFF 71 is supplied to one input terminal of the AND gate 84 (first input terminal of the AND gate 84 ). Further, the output signal of the D-type flip-flop circuit DFF 69 is also supplied to another input terminal (second input terminal) of the AND gate 84 . This allows the AND gate 84 to output the output signal f 84 (VSTP).
- the output signal f 83 (HSTP) is supplied to the T-type flip-flop circuit TFF 81 .
- the output signal f 84 (VSTP) is supplied to the T-type flip-flop circuit TFF 81 as a reset signal.
- An output signal of the T-type flip-flop circuit TFF 81 is supplied to one input terminal (first input terminal) of the Exclusive-OR gate 86 .
- the output signal f 84 is also supplied to the T-type flip-flop circuit TFF 82 .
- An output signal of the T-type flip-flop circuit TFF 82 is supplied to another input terminal (second input terminal) of the Exclusive-OR gate 86 . This allows the Exclusive-Or gate 86 to output the output signal f 86 .
- the output signal f 86 is supplied to the D-type flip-flop circuit DFF 72 .
- An output signal of the D-type flip-flop circuit DFF 72 is supplied to one input terminal (first input terminal) of the AND gate 87 .
- the first output pulse HSTP is supplied to another input terminal (second input terminal) of the AND gate 87 . This allows the AND gate 87 to output the output signal f 87 .
- an output signal of the D-type flip-flop circuit DFF 72 is supplied to one input terminal (first input terminal) of the AND gate 88 , via the inverter 92 .
- the first output pulse HSTP is supplied to another input terminal (second input terminal) of the AND gate 88 . This allows the AND gate 88 to output the output signal f 88 .
- the output signal f 87 is supplied to the D-type flip-flop circuit DFF 73 .
- An output signal of the D-type flip-flop circuit DFF 73 is supplied to one input terminal (first input terminal) of the OR gate 89 .
- the output signal f 88 is supplied to the D-type flip-flop circuit DFF 74 .
- An output signal of the D-type flip-flop circuit DFF 74 is supplied to the D-type flip-flop circuit DFF 79 .
- An output of the D-type flip-flop circuit DFF 79 is supplied to another input terminal (second input terminal) of the OR gate 89 .
- the output pulse HSTP is supplied to the D-type flip-flop circuit DFF 78 . This allows the D-type flip-flop circuit DFF 78 to output the start pulse HST 1 (see FIG. 1 and FIG. 3 ).
- FIG. 2( a ) shows, during an odd-numbered frame period in the display section 95 , a timing chart of the twelve sampling switches SWR 37 through SWR 48 that belong to the blocks 58 and 59 , each of which corresponds to two pixels.
- FIG. 2( a ) also shows, during the odd-numbered frame period, electric potential states (states in which signals are written in the twelve source lines SR 1 through SB 12 ) of the twelve source lines SR 1 through SB 12 which belong to the blocks 58 and 59 , and which correspond to four pixels.
- FIG. 2( b ) shows, during an even-numbered frame period in the display section 95 , a timing chart of the twelve sampling switches SWR 37 through SWR 48 that belong to the blocks 58 and 59 , each of which corresponds to two pixels.
- FIG. 2( b ) also shows, during the even-numbered frame, electric potential states (states in which signals are written in the twelve source lines SR 1 through SB 12 ) of the twelve source lines SR 1 through SB 12 which belong to the blocks 58 and 59 , and which correspond to four pixels.
- frame period indicates a period of time (a scanning period that corresponds to one screen) required for scanning all the gate lines G 90 , . . . , in the display section 95 .
- 1/60second corresponds to one frame.
- each of a first period for rewriting the display screen, a third period for rewriting the display screen, a fifth period for rewriting the display screen, . . . is referred to as an odd-numbered frame period
- each of the display screens (display section 95 ) that have been subject to the first rewriting, the third rewriting, the fifth rewriting, . . . , is referred to as an odd-numbered frame
- each of the display screens (display section 95 ) that have been subject to the second rewriting, the fourth rewriting, the sixth rewriting is referred to as an even-numbered frame.
- the sampling switches SWR 37 through SWB 42 of the group Gr 54 and Gr 55 that belong to the block B 58 are simultaneously selected (turned ON) at time t 0 , in synchronization with a timing signal (not shown) supplied from the timing circuit 77 .
- each of the source lines SR 7 through SB 12 which are connected to the sampling switches SWR 43 through SWB 48 , keeps electric potential which was written one horizontal period (a scanning period that corresponds to one gate line) ago.
- sampling switches SWR 37 through SWB 42 of the groups Gr 54 and Gr 55 that belong to the block 58 are simultaneously turned OFF, in synchronization with a timing signal (not shown) received at the time t 1 which is one clock (one cycle) after the time t 0 .
- a timing signal not shown
- simultaneously selected (turned ON) are the sampling switches SWR 43 through SWB 48 of the groups Gr 56 and Gr 57 that belong to the block 59 .
- the sampling switches SWR 37 through SWB 39 of the group Gr 54 that belongs to the block B 58 are simultaneously selected (turned ON) at time t 0 ′, in synchronization with a timing signal (not shown) supplied from the timing circuit 77 .
- each of the source lines SR 4 through SB 6 (the group Gr 55 ) and the source lines SR 7 through SB 12 (the block B 59 ) connected to the corresponding sampling switches keeps electric potential which was written one horizontal period (a scanning period that corresponds to one gate line) ago.
- the sampling switches SWR 37 through SWB 39 of the groups Gr 54 that belongs to the block 58 are simultaneously turned OFF, in synchronization with a timing signal (not shown) that is received at the time t 1 ′ which is one clock (one cycle) after the time t 0 ′.
- a timing signal not shown
- the sampling switches SWR 40 through SWB 45 of the groups Gr 55 and Gr 56 which belong to the blocks 58 and 59 , respectively.
- each of the source lines SR 10 through SB 12 which are respectively connected to the sampling switches SWR 46 through SWB 48 , keeps electric potential which was written one horizontal period (a scanning period that corresponds to one gate line) ago.
- the sampling switches SWR 40 through SWB 45 of the groups Gr 55 and Gr 56 which belong to the blocks 58 and 59 , respectively, are simultaneously turned OFF, in synchronization with a timing signal (not shown) that is received at the time t 2 ′ which is one clock (one cycle) after the time t 1 ′.
- a timing signal not shown
- the sampling switches SWR 46 through SWB 48 of the groups Gr 57 that belong to the block 59 .
- FIG. 4 schematically shows the parasitic capacitance C 101 through C 104 of the respective source lines in the display section 95 .
- the sampling switch SWB 42 that belongs to the block B 58 is turned ON at the time t 0 .
- the source line SB 6 which is connected to the sampling switch SWB 42 receives a signal (electric potential) via the signal line SLBb 54 .
- turned OFF is the sampling switch SWR 43 belonging to the block B 59 that is adjacent to the block B 58 .
- the source line SR 7 connected to the sampling switch SWR 43 keeps electric potential that was given one horizontal period ago, accordingly.
- an electric potential difference becomes large between the source line SR 7 and the source line SB 6 (i.e., an electrode on a side of the source line SB 6 of the pixel capacitance PB 18 ), the source line SB 6 receiving a new signal (electric potential), and the source line SR 7 keeping the electric potential that was given one horizontal period ago.
- This causes the parasitic capacitance (accumulation of electric charge; see C 102 in FIG. 4 ) to occur between the source lines SB 6 and SR 7 .
- the sampling switch SWR 43 that belongs to the block 59 (group Gr 56 ) is turned ON so that a signal (electric potential) is supplied to the source line SR 7 connected to the sampling switch SWR 43 , the electric potential difference between the source line SR 7 and the source line SB 6 (the electrode on the side of the pixel capacitance PB 18 ) is reduced. This causes the electric charge accumulated in the parasitic capacitance to transfer to (jumps into) the source line SB 6 . As such, the source line SB 6 has the change in electric potential, as indicated by arrows in FIG. 2( a ).
- the source line SB 12 is similar to the source line SB 6 . More specifically, the sampling switch SWB 48 that belongs to the block B 59 is turned ON at the time t 1 . As such, during the period of time from the time t 1 to the time t 2 , the source line SB 12 which is connected to the sampling switch SWB 48 receives a signal (electric potential) via the signal line SLBb 54 . In contrast, during the period of time from the time t 1 to the time t 2 , the source line SR 61 adjacent to the source line SB 12 keeps electric potential that was given one horizontal period ago.
- an electric potential difference becomes large between the source line SR 61 and the source line SB 12 (i.e., an electrode on a side of the pixel capacitance PB 24 ), the source line SB 12 receiving a new signal (electric potential), and the source line SR 61 keeping the electric potential that was given one horizontal period ago.
- This causes the parasitic capacitance occurs (accumulation of electric charge; see C 104 in FIG. 4 ) between the source lines SB 12 and SR 61 .
- the source line SR 61 receives a signal (electric potential) after the time t 2 , reduced is the electric potential difference between the source line SR 61 and the source line SB 12 (the electrode on the side of the pixel capacitance PB 24 ).
- the electric charge accumulated in the parasitic capacitance transfers to (jumps into) the source line SB 12 .
- the sampling switch SWB 39 that belongs to the group Gr 54 is turned ON at the time t 0 ′.
- the source line SB 3 which is connected to the sampling switch SWB 39 receives a signal (electric potential) via the signal line SLBa 51 .
- turned OFF is the sampling switch SWR 40 belonging to the group Gr 55 that is adjacent to the group Gr 54 .
- the source line SR 4 connected to the sampling switch SWR 40 keeps electric potential that was given one horizontal period ago.
- an electric potential difference becomes large between the source line SR 4 and the source line SB 3 (i.e., an electrode on a side of the pixel capacitance PB 15 ), the source line SB 3 receiving a new signal (electric potential), and the source line SR 4 keeping the electric potential that was given one horizontal period ago.
- This causes parasitic capacitance (accumulation of electric charge; see C 101 in FIG. 4 ) to occur between the source lines SB 3 and SR 4 .
- the sampling switch SWR 40 that belongs to the group Gr 55 is turned ON so that a signal (electric potential) is supplied to the source line SR 4 connected to the sampling switch SWR 40 , the electric potential difference between the source line SR 4 and the source line SB 3 (the electrode on the side of the pixel capacitance PB 18 ) is reduced.
- the electric charge accumulated in the parasitic capacitance C 101 transfers to (jumps into) the source line SB 3 . This causes the source line SB 3 to have the change in electric potential, as indicated by arrows in FIG. 2( b ).
- the source line SB 9 is similar to the source line SB 3 . More specifically, the sampling switch SWB 45 that belongs to the group Gr 56 is turned ON at the time t 1 ′. As such, during the period of time from the time t 1 ′ to the time t 2 ′, the source line SB 9 which is connected to the sampling switch SWB 45 receives a signal (electric potential) via the signal line SLBa 51 . In contrast, during the period of time from the time t 1 ′ to the time t 2 ′, turned OFF is the sampling switch SWR 46 belonging to the group Gr 57 adjacent to the group Gr 56 . As such, the source line SR 10 which is connected to the sampling switch SWR 46 keeps electric potential that was given one horizontal period ago.
- an electric potential difference becomes large between the source line SR 10 and the source line SB 9 (i.e., an electrode on a side of the pixel capacitance PB 21 ), the source line SB 9 receiving a new signal (electric potential), and the source line SR 10 keeping the electric potential that was given one horizontal period ago.
- This causes the parasitic capacitance (accumulation of electric charge; see C 103 in FIG. 4 ) to occur between the source lines SB 9 and SR 10 .
- the sampling switch SWR 46 that belongs to the group Gr 57 is turned ON so that a new signal (electric potential) is supplied to the source line SR 10 connected to the sampling switch SWR 46 , the electric potential difference between the source line SR 10 and the source line SB 9 (the electrode on the side of the pixel capacitance PB 21 ) is reduced. On this account, the electric charge accumulated in the parasitic capacitance C 103 transfers to (jumps into) the source line SB 9 . This causes the source line SB 9 to have the change in electric potential, as indicated by arrows in FIG. 2( b ).
- the source lines SB 6 and SB 12 have the change in electric potential
- the source lines SB 3 and SB 9 have the change in electric potential.
- the display section 95 of the present embodiment is arranged so that each of the output stages SiR 55 through SiR 58 of the shift register 70 corresponds to the six sampling switches SWR 37 through SWB 48 (i.e., the six source lines SR 1 through SB 12 ).
- This arrangement dramatically simplifies the arrangement of the shift register 70 , and then a circuit area of the shift register 70 , as compared with an arrangement in which each output stage of the shift register 70 corresponds to one of the source lines SR 1 through SB 12 .
- the effect of the display section 95 becomes more noticeable when the display section 95 (display panel) is applied to a small-sized or a medium-sized high-resolution panel, having many restrictions on outer shape and wiring pitch, such as a liquid crystal panel. Namely, it is possible to carry out displaying with high quality, in accordance with the downsizing of the panel.
- the output stages SiR 55 through SiR 58 correspond to the three sampling switches SWR 37 through SWB 39 , SWR 40 through SWB 42 , SWR 43 through SWB 45 , and SWR 46 through SWB 48 (i.e., the three source lines SR 1 through SB 3 , SR 4 through SB 6 , SR 7 through SB 9 , SR 10 through SB 12 ), respectively.
- the present invention is not limited to this.
- the shift register 70 may be arranged so that each of the output stages (SiR 55 through SiR 58 ) corresponds to two sampling switches.
- two source lines may be provided for each group, so that four signal lines are used.
- the colors that correspond to the source lines (SR 1 , SG 2 , SB 3 , . . . ) are R, G, and B, in this order.
- the present invention is not limited to this.
- the source lines SR 1 , SG 2 , and SB 3 may correspond to G, R, and B, respectively.
- the source lines (SB 3 , SB 6 , SB 9 , and SB 12 ) disposed at respective ends in their groups (Gr 54 , Gr 55 , Gr 56 , and Gr 57 ) correspond to the color of B (blue).
- the present invention is not limited to this.
- the signal circuit of the present invention may be arranged so that one source line (data line) is provided for each group, so that two signal lines (two signal sources) are used.
- the signal circuit of the present invention may include: (i) two signal lines (two signal sources), (ii) a plurality of source lines (data lines) to which signals are supplied from the source lines, (iii) driving means for driving the source lines (data lines), the source lines being divided into a plurality of groups, and each of the groups including one data line, adjacent groups constituting one block that includes two source lines, the signal sources supplying the signals, at same timing, to the data lines that belong to a group selected by the driving means, respectively, wherein: the driving means selects groups which belong to a clump of blocks including a first block, and a second block adjacent to the first block so that, (i) during an odd-numbered period (first predetermined period), the driving means simultaneously selects groups that belong to the first block, and simultaneously selects groups that belong to the second block, and (ii) during an even-numbered period (second predetermined period) subsequent to the first predetermined period, the driving means selects groups one by one from groups disposed at respective ends of the clump
- each of the first and second blocks has two groups (two source lines) that correspond to the two signal lines, respectively.
- first predetermined period simultaneously selected are the two groups (two source lines) belonging to the first block.
- second predetermined period simultaneously selected are two groups (two source lines) belonging to the second block adjacent to the first block.
- firstly selected is the first group (a source line disposed at an end of the one block) disposed at an end of the clump of blocks including the first through fourth groups in the scanning direction, and then selected are the second and third groups (two source lines) next to the first group, and then selected is the fourth group (a source line) next to the third group.
- the selections of the groups are sequentially carried out.
- the driving means includes a shift register having the output stages, and sampling switches provided in the respective source lines.
- the driving means includes a shift register having the output stages, and sampling switches provided in the respective source lines.
- one output stage of the shift register corresponds to one sampling switch (one source line).
- signals sent via the signal lines SLRa 49 through SLBb 54 are analog signals.
- signals of b-channel are delayed by amount corresponding to one clock, and then are outputted from the signal source side.
- a driver it becomes easy for a driver to include a circuit for carrying out the delaying by the amount corresponding to one clock, by providing a D-type flip flop circuit.
- the present invention as a liquid crystal display apparatus including video signal lines (SLRa 49 , . . . , SLRb 52 , . . . ) for individually inputting video signals of two-channel (a-channel and b-channel), and adopting a point-at-a-time driving method for carrying out a point-at-a-time driving with respect to pixels in every column of a pixel section (display section) 95 in which pixels (the transistors TR 25 through TB 36 , and the pixel capacitance PR 13 through PB 24 ) are provided in a matrix manner, the liquid crystal display apparatus further including: (1) a group of sampling switches (SWR 37 through SWR 48 ) provided between the signal lines provided (wired) in every row of the pixels and the respective video signal lines of the two-channel, and (2) driving means (the timing signal generating circuit 77 , the shift register, or the like) that drives the sampling switches so that a combination of the sampling switches (SWR 37 through SWR 48 ) to
- a signal circuit of the present invention includes: (i) a plurality of signal sources; (ii) a plurality of data lines to which the signal sources supply signals, respectively; and (iii) driving means for driving the data lines, the data lines being divided into a plurality of groups, each of the groups including at least one data line, adjacent groups constituting one block, the signal sources supplying the signals, at same timing, to the data lines that belong to a group selected by the driving means, respectively, wherein: the driving means selects groups which belong to a clump of blocks including a first block, and a second block adjacent to the first block so that, (i) during a first predetermined period, the driving means simultaneously selects groups that belong to the first block, and simultaneously selects groups that belong to the second block, and (ii) during a second predetermined period subsequent to the first predetermined period, the driving means selects groups one by one from groups disposed at respective ends of the clump of blocks, simultaneously selects adjacent groups that belong to different blocks, and selects remaining
- each terminal data line of the terminal group of each block has a change in electric potential.
- each terminal data line of each group other than the terminal group of each block has a change in electric potential.
- the terminal data line of each group has a uniform change in electric potential.
- the data line is used as a source line for writing a signal (electric potential) in a pixel of a display apparatus
- a signal electric potential
- display unevenness having a vertical-striped shape is enhanced for every several data lines (for every several pixels). This allows the display unevenness not to be noticeable over the entire display screen (to be difficult to visually recognize), thereby improving display quality.
- the signal circuit is arranged so that the signal sources include (i) red, green, and blue signal lines that belong to a first signal channel and (ii) red, green, and blue signal lines that belong to a second signal channel, wherein: each of the blocks includes two groups each having three data lines, and the data lines belonging to one of the two groups correspond to the signal lines of the first signal channel, respectively, and the data lines belonging to the other of the two groups correspond to the signal lines of the second signal channel, respectively, and a data line that corresponds to a blue signal line is disposed at an end part of each group in a scanning direction.
- signals are simultaneously supplied to three data lines of the group thus selected, via the signal lines (red, green, blue) that correspond to the three data lines.
- signals can be simultaneously written in one pixel.
- signals can be simultaneously written in two pixels. This can dramatically reduce a frequency during a horizontal period (i.e., the time required for scanning all the data lines).
- the driving means for selecting a group can have a simpler circuit structure (a shift register and other circuit).
- the terminal data line data line disposed at an end part of each group in the scanning direction
- the change in electric potential correspond to blue which has the least change in luminance when the electric potential changes.
- the data line is used for a source line in each pixel (pixel electrode) of a display apparatus
- the signal circuit of the present invention is arranged so that the data lines are source lines that correspond to respective pixels of a display apparatus, and that the first predetermined period is an odd-numbered frame period, and the second predetermined period is an even-numbered frame period.
- frame period means the time required for rewriting once the whole display screen of the display apparatus. That is, a first period for rewriting the display screen, a third period for rewriting the display screen, a fifth period for rewriting the display screen, . . . , correspond to an odd-numbered frame period, and a second period for rewriting the display screen, a fourth period for rewriting the display screen, a sixth period for rewriting the display screen, . . . , correspond to an even-numbered frame period.
- the terminal data lines of the respective groups have a uniform change in electric potential.
- this can avoid the problem in which, for example, in cases where the data lines are used as the source lines provided in the respective pixels of the display apparatus, only the terminal data lines of the specific groups have the changes in electric potential respectively so that the display unevenness having the vertical-striped shape is enhanced for every several data lines (for every several pixels). Namely, this can make it difficult that the display unevenness having a vertical-striped shape is noticeable.
- a display apparatus of the present invention includes the aforementioned signal circuit.
- a method of the present invention for driving data lines in which a plurality of signal sources supply signals to the data lines, respectively, the method including the steps of: (i) dividing a plurality of data lines into a plurality of groups, each of the groups including at least one data line, adjacent groups constituting one block; and (ii) supplying the signals, at the same timing, to the data lines that belong to a selected group, respectively, wherein: groups which belong to a clump of blocks including a first block, and a second block adjacent to the first block are selected so that: (i) during a first predetermined period, groups that belong to the first block are simultaneously selected, and then groups that belong to the second block are simultaneously selected, and (ii) during a second predetermined period subsequent to the first predetermined period, groups are selected one by one from groups disposed at respective ends of the clump of blocks, adjacent groups that belong to different blocks are simultaneously selected, and then remaining groups are selected one by one.
- a signal circuit of the present invention and the liquid crystal display apparatus including such a signal circuit ensure that the change in electric potential of a plurality of the source lines (data lines) are averaged and uniformized over the entire display screen during the two frame periods, the change in electric potential being caused by the parasitic capacitance occurring when signals which are supplied via the signal lines (signal sources) are written in the source lines.
- the present invention may be applied, for example, to a display apparatus, such as a liquid crystal display apparatus, in which respective signal electric potential, supplied from a source driver, are written in a plurality of source lines that are provided to correspond to respective pixels.
- the effect of the present invention becomes more noticeable when the present invention is applied to a small-sized or a medium-sized high-resolution display apparatus (display panel) having restrictions on outer shape and wiring pitch.
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Abstract
Description
Claims (11)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2003-400352 | 2003-11-28 | ||
JP2003400352A JP4071189B2 (en) | 2003-11-28 | 2003-11-28 | Signal circuit, display device using the same, and data line driving method |
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US20050117384A1 US20050117384A1 (en) | 2005-06-02 |
US7538754B2 true US7538754B2 (en) | 2009-05-26 |
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US10/995,196 Expired - Fee Related US7538754B2 (en) | 2003-11-28 | 2004-11-24 | Signal circuit, display apparatus including same, and method for driving data line |
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US (1) | US7538754B2 (en) |
JP (1) | JP4071189B2 (en) |
KR (1) | KR100569024B1 (en) |
CN (1) | CN100565631C (en) |
TW (1) | TWI242312B (en) |
Cited By (3)
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US20090179835A1 (en) * | 2008-01-10 | 2009-07-16 | Seiko Epson Corporation | Electro-optical device, driving method of electro-optical device, and electronic apparatus |
US20090289878A1 (en) * | 2008-05-22 | 2009-11-26 | Chung-Chun Chen | Liquid crystal display device and driving method thereof |
US20150109270A1 (en) * | 2013-10-18 | 2015-04-23 | Seiko Epson Corporation | Electro-optic device, driving method for electro-optic device and electronic device |
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KR100630759B1 (en) | 2005-08-16 | 2006-10-02 | 삼성전자주식회사 | Driving method of liquid crystal display device having multi channel - 1 amplifier structure |
KR101263932B1 (en) | 2005-11-30 | 2013-05-15 | 삼성디스플레이 주식회사 | Method and apparatus driving data of liquid crystal display panel |
CN101281739B (en) * | 2008-06-02 | 2011-12-14 | 友达光电股份有限公司 | Crystal display device and driving method thereof |
CN103632638B (en) * | 2012-08-20 | 2016-08-24 | 群康科技(深圳)有限公司 | Data driver be demultiplexed device and driving method and liquid crystal display systems |
WO2014132303A1 (en) * | 2013-02-27 | 2014-09-04 | 日本電気株式会社 | Communication system, communication device, communication control method, and non-transitory computer readable medium |
TWI550590B (en) * | 2015-05-22 | 2016-09-21 | 天鈺科技股份有限公司 | Data driver, driving method of data driver and driving method of display panel |
JP6812760B2 (en) * | 2016-11-15 | 2021-01-13 | セイコーエプソン株式会社 | Electro-optics, electronic devices, and how to drive electro-optics |
CN107863062B (en) * | 2017-11-30 | 2021-08-03 | 武汉天马微电子有限公司 | Display panel control method |
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- 2004-11-26 KR KR1020040098115A patent/KR100569024B1/en not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
---|---|
KR100569024B1 (en) | 2006-04-07 |
TWI242312B (en) | 2005-10-21 |
JP4071189B2 (en) | 2008-04-02 |
KR20050052396A (en) | 2005-06-02 |
US20050117384A1 (en) | 2005-06-02 |
TW200524214A (en) | 2005-07-16 |
CN100565631C (en) | 2009-12-02 |
CN1622150A (en) | 2005-06-01 |
JP2005164705A (en) | 2005-06-23 |
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