US6256243B1 - Test circuit for testing a digital semiconductor circuit configuration - Google Patents

Test circuit for testing a digital semiconductor circuit configuration Download PDF

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US6256243B1
US6256243B1 US09/642,734 US64273400A US6256243B1 US 6256243 B1 US6256243 B1 US 6256243B1 US 64273400 A US64273400 A US 64273400A US 6256243 B1 US6256243 B1 US 6256243B1
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circuit
test
pattern
data
variation
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Dominique Savignac
Wolfgang Nikutta
Michael Kund
Jan Ten Bröke
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Polaris Innovations Ltd
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Infineon Technologies AG
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices

Definitions

  • the invention relates to a monolithically integrated test circuit for testing a digital semiconductor circuit configuration having a large number of elements to be tested.
  • the test circuit is formed on the same semiconductor chip as the circuit configuration under test.
  • the test circuit includes a read and write circuit for writing and reading a test data pattern to and from the elements to be tested, a comparison circuit, and a pattern variation circuit which can be activated by an activation signal.
  • U.S. Pat. No. 5,418,790 discloses a test circuit for detecting interference for a semiconductor memory apparatus which, for simultaneous investigation of memory cells, programs the memory cells simultaneously with a single test bit that is common to all the memory cells, and combines the determined data values stored on the basis of the test bit such that a check is carried out at the same time to confirm that all the data values are absolutely identical.
  • the previously known apparatus has logic apparatuses which can be activated by a signal, and by which the test bit and the data values determined from the memory cells can be inverted simultaneously before they are combined.
  • the previously known apparatus has the disadvantages mentioned above.
  • the test circuit includes a read and write circuit for writing and reading a test data pattern having a given width to and from the elements to be tested and a test data pattern register for temporarily storing the test data pattern.
  • a pattern variation circuit is provided which receives and is activated by an activation signal.
  • the pattern variation circuit is connected to the test data pattern register and to the read and write circuit.
  • the pattern variation circuit varies the test data pattern received from the test data pattern register before writing it into the elements to be tested.
  • a comparison circuit is connected to the read and write circuit and to the pattern variation circuit. The comparison circuit tests for a difference between written data and read data of the elements to be tested.
  • the invention provides that a test data pattern register is provided for temporary storage of the test data patterns, and that the pattern variation circuit which can be activated by the activation signal varies the test data pattern from the test data pattern register before writing into the elements to be tested.
  • the comparison circuit is configured in such a way that it tests for a difference between the written and read data of the elements to be tested.
  • the activation signal for activating the pattern variation circuit is supplied via a pad, which is already present on the semiconductor chip, and is connected to the pattern variation circuit.
  • the advantage of this configuration is that the semiconductor circuit configuration can be tested with varying patterns while still part of the wafer, without the test data pattern register having to be reloaded.
  • the first mode is a normal mode in which the test circuit is deactivated and the semiconductor circuit configuration has the I/O lines associated with it.
  • the second mode is a test mode in which the pad, which is already present on the semiconductor chip, is connected to the pattern variation circuit of the test circuit.
  • the pad is preferably decoupled from the pattern variation circuit in the normal mode and in the normal mode is intended for coupling the digital semiconductor circuit configuration to a signal.
  • the comparison circuit of the test circuit is formed with a number of logic gates corresponding to the width of the test data pattern, which gates compare the data read from and to be written to the semiconductor memory bit-by-bit.
  • the test circuit is advantageously equipped with an addition gate, which is coupled to the logic gates of the comparison circuit.
  • the addition gate which is advantageously formed by a NOR gate, combines the results of the logic gates of the comparison circuit to form a test result. In this case, a logic “zero” as the result from the NOR gate is then used as a FAIL signal, and a logic “one” is then used as a PASS signal.
  • the pattern variation circuit is formed by a number of logic gates corresponding to the width of the test data pattern, which gates vary the test data pattern of the test data pattern register bit-by-bit.
  • the pattern variation circuit can advantageously be activated by an activation signal.
  • the logic gates in the comparison circuit and in the pattern variation circuit are advantageously formed by exclusive-OR gates.
  • the test circuit has a result variation circuit, which contains a number of logic gates corresponding to the width of the test data pattern.
  • the logic gates are connected to the outputs of the logic gates in the comparison circuit and are disposed downstream from which the addition gate is connected to the outputs.
  • the logic gates in the result variation circuit are in this case preferably formed by exclusive-OR gates, which are activated jointly by a result variation signal.
  • the data bits in each group are linked to the varied test data pattern bits in such a way that the previous operation is reversed. If no error occurs, all the result bits in a group are the same after this operation, otherwise they differ.
  • the activation signal for the pattern variation circuit is supplied via a semiconductor memory input and output line which is not used in the test mode.
  • the result variation circuit can be activated by the result variation signal via a semiconductor memory input and output line which is likewise not used in the test mode.
  • the FAIL or PASS signal can be output via a further semiconductor memory input and output line which is not used in the test mode.
  • Another major advantage of the invention is that data pattern bits can be inserted using those data bits which are compressed and may have any desired data pattern, so that the entire memory can be tested using the same data patterns as is the case, per se, with a standard test.
  • the invention thus results in a high test accuracy level, and the advantages of compression, in terms of a reduced address area and a reduced number of I/O interfaces, can be exploited.
  • a one-from-four multiplexer circuit whose output signal is the activation signal for the pattern variation circuit, and which supplies one of four data values from a data register as the output signal.
  • the result variation circuit can be activated in a similarly advantageous manner by a one-from-four multiplexer circuit whose output signal is the result variation signal and which supplies one of four data values from a result variation data register as the output signal.
  • the address and I/O compression test mode is controlled in accordance with the JEDEC Standard by three test mode sequences.
  • the first test mode sequence selects the test mode and stores in the chip those test data pattern bits which are used for producing data patterns in the column direction throughout the test.
  • the second test mode sequence stores in the data register those data pattern bits which are used for producing data patterns in the row direction, for write accesses, as a function of the row address and in conjunction with the test data pattern register.
  • the I/O interfaces are ignored for these write accesses.
  • the third test mode sequence stores in the result variation data register those data pattern bits which are used as the result variation signal for read accesses as a function of the row address and in conjunction with the test data pattern register.
  • the second and the third test mode sequence can be used as often as required and independently of one another during a test sequence. This is necessary to allow so-called “march patterns” (“sequential test patterns”), which are composed of sequences of read accesses and subsequent write accesses with inverted data for each memory address.
  • one bit is selected from the data register via a multiplexer, as a function of the row address, and is linked to the test data pattern bits in the test data pattern register. This can be done, for example, using exclusive-OR gates.
  • the resultant data bits are used as a write data for each group. Those data bits in each group that are written in the associated memory area may thus have any required pattern in the column direction and in the row direction.
  • the data bits in each group are linked to the data pattern bits in such a way that the previous operation is reversed. This can be done in this case as well using exclusive-OR gates. If no fault has occurred, all the result bits in a group are identical after this operation; otherwise, they differ.
  • the result bits in each group are then each compared with a result variation signal, which is selected from the result variation data register via a multiplexer, as a function of the row address. If all the result bits in a group are the same as the result variation signal, PASS information is passed to the corresponding IO interfaces (for example logic “1”). If at least one result bit does not match the result variation signal, FAIL information is output (for example logic “0”).
  • Test mode sequence 1 The test mode is selected and the test data pattern register is loaded.
  • Test mode sequence 2 The data register is loaded.
  • Test mode sequence 3 The result variation data register is loaded with the data from step b.
  • Test mode sequence 2 The data register is loaded with new write data.
  • Test mode sequence 3 The result variation data register is loaded with the data from step e.
  • test mode is switched off (in accordance with the JEDEC Standard).
  • test data pattern register, the data register and the result variation data register together with their associated multiplexers can thus be used for all the groups at the same time.
  • FIG. 1 is a circuit diagram of a test circuit based on a first exemplary embodiment of the invention
  • FIG. 2 is a circuit diagram of that part of the test circuit which is required for a write procedure, with one I/O interface and four data channels, based on a second exemplary embodiment of the invention
  • FIG. 3 is a circuit diagram of the part of the test circuit for a read procedure, with four data channels and one interface, based on the second exemplary embodiment of the invention
  • FIG. 4 is a circuit diagram of that part of the test circuit which is required for the write procedure, with four data channels, based on a third exemplary embodiment of the invention
  • FIG. 5 is a circuit diagram of the part of the test circuit for the read procedure, with the four data channels and the one interface, based on a third exemplary embodiment of the invention.
  • FIG. 6 is a block circuit diagram of a data path of a digital semiconductor memory with an x4, x8 and x16 organization.
  • FIG. 1 there is shown an exemplary embodiment of a test circuit which is monolithically integrated on a semiconductor chip (not shown in any more detail).
  • the test circuit tests memory cells of a semiconductor memory with a test data pattern stored in a test data pattern register.
  • the register 1 contains, for example, six logic bits D 0 to D 5 and may be in the form of a semiconductor circuit configuration register which is not used in a test mode.
  • Downstream of the register 1 is a number (in this case six) of exclusive-OR gates 2 A to 2 F corresponding to a width of the test data pattern, and the gates 2 A to 2 F form a pattern variation circuit 2 .
  • the pattern variation circuit 2 varies or inverts the test data pattern bit-by-bit.
  • the variation of the test data pattern is initiated by applying a logic “one” as an activation signal 3 to the exclusive-OR gates 2 A to 2 F.
  • the activation signal 3 is in this case applied via a pad 4 which is formed on the semiconductor chip and may in this case be formed by the pad 4 (which is not used in the test mode) of a data control input (DATACTRL) of the semiconductor circuit.
  • DATACTRL data control input
  • the pad 4 may be connected to the pattern variation circuit 2 by a data control unit 5 that is activated in the test mode.
  • Write data lines WDL 0 to WDL 5 are connected downstream of the pattern variation circuit 2 , via which lines the unchanged or varied test data patterns are written by a write and read circuit 20 to the open cells in the semiconductor memory.
  • An output side of the pattern variation circuit 2 furthermore has a comparison circuit 6 assigned to it, which is composed of a number of exclusive-OR gates 6 A to 6 F corresponding to the width of the test data pattern. Inputs of the exclusive-OR gates 6 A to 6 F in this case have the varied test data pattern applied to them, and also have those data contents of the open cells in the semiconductor memory which are applied via the read data lines RDL 0 to RDL 5 applied to them.
  • the comparison circuit 6 is followed by an addition gate 7 which is assigned to the outputs of the exclusive-OR gates 6 A to 6 F and is formed by a NOR gate 7 provided with a number of inputs corresponding to the number of logic gates in the comparison circuit 6 .
  • a logic “one” level is produced at an output 8 of the NOR gate 7 only when all the inputs of the NOR gate 7 are at logic “zero”, that is to say there is no difference between a written and a read data bit, and this corresponds to a PASS signal; otherwise, the output is a logic “zero”, which corresponds to a FAIL signal.
  • the output 8 of the addition gate 7 thus remains at a logic “one” level throughout the entire test of the semiconductor memory, and changes to a logic “zero” level as soon as a fault occurs.
  • the contents of the memory cells are compared with the varied test data pattern via the read data lines RDL 0 to RDL 5 . If it is assumed that one memory cell connected to the write or read data line WDL 4 or RDL 4 is defective, then a logic “one” will be produced at the output of the logic gate 6 B. This would result in a logic “zero”, that is to say an FAIL signal, being produced at the output of the addition gate 7 .
  • FIG. 2 shows the part that is required for writing in a further embodiment of the invention, with only the test data pattern register 1 and the pattern variation circuit 2 being illustrated.
  • the pattern variation circuit 2 in the illustrated example contains four exclusive-OR gates 2 A to 2 D, each having two inputs.
  • the activation signal 3 is jointly applied to one input of each of the logic gates 2 A- 2 D via an associated I/O interface IOi 0 of the semiconductor memory, which I/O interface would otherwise not be required in the test mode, in order to address the semiconductor memory.
  • the respective second inputs of the logic gates 2 A- 2 D each have a test data pattern bit M 0 to M 3 applied to them, from the test data pattern register 1 .
  • the outputs of the logic gates 2 A- 2 D are connected to the write data lines WDL 0 to WDL 3 of the data memory block in the semiconductor memory.
  • a test data pattern bit is logic 0
  • the respective data bit at the output of the logic gate has the same polarity as the information at the I/O interface; otherwise, it has the opposite polarity.
  • the four data bits in a group may thus have any required pattern, even though only one I/O interface is used for writing.
  • FIG. 3 shows the part required for reading in a further embodiment of the invention.
  • FIG. 3 shows the test data pattern register 1 , the comparison circuit 6 and the NOR gate 7 , which operate as already described.
  • the comparison circuit 6 contains four exclusive-OR gates 6 A to 6 D, each having two inputs, which each link one data bit of the read data line RDL 0 to RDL 3 and one test data pattern bit M 0 to M 3 from the test data pattern register 1 . After this operation, the polarities of all the outputs are the same, provided no difference (fault) has occurred.
  • These result bits Ei 0 to Ei 3 are linked to four further exclusive-OR gates 9 A to 9 D in a result variation circuit 9 .
  • the result variation circuit 9 varies or inverts the results from the comparison circuit 6 bit by bit.
  • the variation of the results is initiated by applying a logic “one” as a result variation signal 10 to the exclusive-OR gates 9 A to 9 D.
  • the result variation signal 10 is in this case applied to the result variation circuit 9 via a pad, a register memory cell or an I/O interface 4 ′ which is not required for addressing the semiconductor memory in the test mode.
  • the outputs of the exclusive-OR gates 9 A to 9 D in the result variation circuit 9 are, finally, combined using the NOR gate 7 , whose output 8 is logic 0 , as soon as at least one applied bit is logic 1 (that is to say incorrect).
  • the output of the NOR gate 7 in this exemplary embodiment of the invention is connected to an I/O line which is not required by the semiconductor memory in the test mode and via which the result of the test run is output externally.
  • the result of the addition gate (NOR gate 7 ) is covered by the same statements as those in the description relating to FIG. 1 .
  • the data path and the I/O interfaces are controlled as in the normal mode. For the sake of simplicity, these control signals are not shown.
  • FIG. 4 shows a modification of the embodiment of the invention described in FIG. 2 .
  • the activation signal 3 for activating the pattern variation circuit 2 is provided at an output 12 of a one-from-four multiplexer circuit 11 .
  • the one-from-four multiplexer circuit 11 in this case applies one of four data bits from a data register 13 to the output 12 .
  • the data bit is selected from the data register 13 via the row addresses R 0 and R 1 .
  • the data bits which are written to the semiconductor memory may thus have any required pattern in the column direction and in the row direction (in this case, the pattern depth is 4 ⁇ 4).
  • FIG. 5 shows a modification of the embodiment of the invention described in FIG. 3 .
  • the result variation signal 10 for activating the result variation circuit 9 is provided at the output 15 of a one-from-four multiplexer circuit 14 .
  • the one-from-four multiplexer circuit 14 in this case applies one of four data bits from a result variation data register 16 to the output 15 .
  • the selection of the data bit from the result variation data register 16 is in this case carried out via the row addresses R 2 and R 3 .
  • the one-from-four multiplexer circuit 14 , the result variation data register 16 and the row addresses R 2 and R 3 may in this case be identical to those in FIG. 4 .
  • the two data registers 13 and 16 may in this case also be formed jointly by a single register with a width of eight bits.
  • test data pattern register 1 and the data registers 13 and/or 16 are loaded via four address lines via the test mode sequence a), b) and c) or, if the one-from-four multiplexer circuit is not present, the activation signal 3 and the result variation signal 10 are provided via address or I/O lines.
  • FIG. 6 shows a schematic illustration of the data path in a semiconductor memory in the form of an SDRAM, which allows an x4, an x8 and an x16 organization.
  • Modern memories are normally subdivided into a number of blocks, for example into the four blocks MA 0 , MA 1 , MA 2 and MA 3 . These blocks are not necessarily physically separated from one another. The subdivision should in this case be regarded as meaning that a certain number of data bits are accessible when each block is accessed, for example four data bits D 00 to 03 , D 10 to 13 , D 30 to 33 in each case, which each originate from an active word line WL, and with clear word and column addresses. These data bits may possibly originate from a number of word lines WL if, in the event of a repair, all these word lines are simultaneously replaced by a redundant word line.
  • an x4 organization two address bits of the column address are used to make a one-from-four selection via multiplexers M4:1.
  • the outputs of the multiplexers M4:1 are each connected to one I/O interface (IO 00 , IO 01 , . . . , IO 30 ).
  • one address bit of the column address is used to make a one-from-two selection via multiplexers M2:1.
  • the outputs of the multiplexers M2:1 are each connected to 2 I/O interfaces (IO 00 to 01 , . . . , IO 30 to 31 ).
  • four data bits are in each case connected to four I/O interfaces (IO 00 to 03 , . . . , IO 30 to 33 ) in each block. As is shown in FIG. 1, these data bits may in some cases be supplied to the I/O interfaces via the multiplexers mentioned above, in order to save lines.
  • test circuit T is provided for each block MA 0 , . . . , MA 3 , and is connected between the respective four data bits and the I/O interface in the x4 organization (IO 00 , . . . , IO 30 ).
  • Each of the test circuits T can have the test data pattern register 1 (pattern depth four) applied to it via four lines, and the result variation signal and the activation signal 3 applied to it via one respective line.
  • the test data pattern register 1 is loaded via four address lines on entering the test mode. Irrespective of the data organization, the normal multiplexers and the normal I/O interfaces are deactivated during the test mode, and the test circuits T together with their associated I/O interfaces are activated.
  • the result variation signal 10 is applied, for example, via a column address which is not used for the test mode owing to the saving of I/O lines (not all the I/O lines are required), and is provided via an internal register, or via the described variants with the aid of pads, or via the described multiplexer circuits.
  • the described implementation of the invention uses the same databus structure as in the normal mode, with four I/O interfaces out of sixteen being used to output the test result. In a further implementation, however, four times as many memory cells are activated as in the normal mode. With sixteen test circuits instead of four, the test results can be output at four groups of four I/O interfaces in each case. The number of I/O interfaces in this implementation is admittedly not reduced, but the address area is reduced further by a factor of four.

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US09/642,734 1998-02-17 2000-08-17 Test circuit for testing a digital semiconductor circuit configuration Expired - Lifetime US6256243B1 (en)

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DE19806455 1998-02-17
DE19806455 1998-02-17
PCT/DE1998/002895 WO1999043004A1 (de) 1998-02-17 1998-09-30 Testschaltung und verfahren zum prüfen einer digitalen halbleiter-schaltungsanordnung

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JP (1) JP3842971B2 (zh)
KR (1) KR100383479B1 (zh)
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US20030237033A1 (en) * 2002-06-04 2003-12-25 Simone Borri System for testing a group of functionally independent memories and for replacing failing memory words
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US20130159785A1 (en) * 2011-12-16 2013-06-20 Daisuke Hashimoto Semiconductor storage device, method for controlling the same and control program
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KR100558492B1 (ko) * 2003-11-14 2006-03-07 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 테스트 패턴 데이터발생방법
KR101192556B1 (ko) * 2010-08-12 2012-10-17 한국항공우주산업 주식회사 디지털 회로 검증시스템 설계방법 및 그 검증시스템
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US7085972B2 (en) * 2002-06-04 2006-08-01 Infineon Technologies Ag System for testing a group of functionally independent memories and for replacing failing memory words
WO2003107354A1 (de) * 2002-06-14 2003-12-24 Infineon Technologies Ag Ram-speicherschaltung mit mehreren bänken und einer hilfseinrichtung zum testen
US20050152194A1 (en) * 2002-06-14 2005-07-14 Sven Boldt RAM memory circuit having a plurality of banks and an auxiliary device for testing
US6961273B2 (en) 2002-06-14 2005-11-01 Infineon Technologies Ag RAM memory circuit having a plurality of banks and an auxiliary device for testing
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US20060179370A1 (en) * 2005-02-07 2006-08-10 Samsung Electronis Co., Ltd. Semiconductor memory device in which memory cells are tested using several different test data patterns and method thereof
US20100269001A1 (en) * 2009-04-21 2010-10-21 Shih-Hsing Wang Testing system and method thereof
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TWI425517B (zh) * 2009-04-21 2014-02-01 Etron Technology Inc 一種測試系統及方法
US20130159785A1 (en) * 2011-12-16 2013-06-20 Daisuke Hashimoto Semiconductor storage device, method for controlling the same and control program
US8984375B2 (en) * 2011-12-16 2015-03-17 Kabushiki Kaisha Toshiba Semiconductor storage device, method for controlling the same and control program
US9239758B2 (en) 2011-12-16 2016-01-19 Kabushiki Kaisha Toshiba Semiconductor storage device, method for controlling the same and control program
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EP1055238B1 (de) 2001-08-29
JP3842971B2 (ja) 2006-11-08
CN1285073A (zh) 2001-02-21
EP1055238A1 (de) 2000-11-29
WO1999043004A1 (de) 1999-08-26
KR100383479B1 (ko) 2003-05-12
TW407209B (en) 2000-10-01
KR20010040999A (ko) 2001-05-15
CN1133173C (zh) 2003-12-31
DE59801360D1 (de) 2001-10-04
JP2002504736A (ja) 2002-02-12

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