US5933027A - High-voltage-tolerant output buffers in low-voltage technology - Google Patents
High-voltage-tolerant output buffers in low-voltage technology Download PDFInfo
- Publication number
- US5933027A US5933027A US08/879,212 US87921297A US5933027A US 5933027 A US5933027 A US 5933027A US 87921297 A US87921297 A US 87921297A US 5933027 A US5933027 A US 5933027A
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- 239000000872 buffer Substances 0.000 title description 3
- 230000005540 biological transmission Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 230000002411 adverse Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 230000003071 parasitic effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
Definitions
- the present invention relates to integrated circuits, and, in particular, to integrated circuits that are made in a low-voltage technology and designed to operate with integrated circuits that are made in a relatively high-voltage technology.
- the voltage of a particular technology is typically defined by the gate-oxide breakdown voltage and/or the punch-through between the source and drain.
- One potential problem with interfacing low-voltage circuitry with high-voltage circuitry is that, if the voltages applied to the low-voltage circuitry get too high, one or more of the devices in the low-voltage circuitry may experience temporary or even permanent damage that can inhibit its ability to function properly.
- MOS metal-oxide semiconductor
- conventional integrated circuitry implemented in a 2.5 V technology can typically tolerate voltages as high as 3.3 V.
- Such conventional circuitry cannot however tolerate voltages higher than 3.3 V without experiencing problems.
- such conventional circuitry cannot be connected to conventional circuitry implemented in a higher-voltage technology, such as a 5 V technology.
- the present invention is directed to integrated circuits in a low-voltage technology having an output driver that enables the low-voltage circuitry to be interfaced and operated with relatively high-voltage circuitry.
- Embodiments of the present invention are directed to an integrated circuit in a low-voltage technology having an output driver coupled to other low-voltage technology circuitry.
- the output driver comprises (a) circuitry adapted to generate an output voltage at an output node (e.g., PAD in FIG.
- a first transistor e.g., M7
- a second transistor e.g., M11
- the second transistor limits the drain-to-source voltage drop across the first transistor to enable the integrated circuit to tolerate a voltage of magnitude up to two times the first reference voltage at the output node.
- the output driver is a pull-up, pull-down output driver comprising (a) a NAND gate adapted to receive an input signal (e.g., A in FIG. 1) and an enable sign (e.g., EN); (b) a first transistor (e.g., M1) connected at a first channel node to the output of the NAND gate and adapted to receive a first reference voltage (e.g., Vdd) at its gate; (c) a second transistor (e.g., M2) connected at a first channel node to the output of the NAND gate and at a second channel node to a second channel node of the first transistor to form a node G1; (d) a third transistor (e.g., M3) connected at a first channel node to the gate of the second transistor to form a node X, at a second channel node to an output node (e.g., PAD), and adapted to receive the first reference voltage; (e) an impedance device (e.
- FIG. 1 shows a schematic diagram of a pull-up, pull-down CMOS output driver, according to one embodiment of the present invention.
- the present invention is related to output drivers implemented in a low-voltage technology that are able to tolerate voltages that are significantly greater than their operating voltage.
- 5 V-tolerant output drivers can be implemented in a 2.5 V technology.
- FIG. 1 shows a schematic diagram of pull-up, pull-down CMOS output driver 100, according to one embodiment of the present invention.
- enable input EN is high (i.e., logic 1)
- output driver 100 operates in its "driving" mode.
- enable input EN is low (i.e., logic 0)
- output driver 100 operates in its "tri-state” or “high impedance (Z)” mode.
- the output PAD of output driver 100 follows the logic value of input A. That is, PAD switches between Vdd and Vss (e.g., ground), as input A varies between Vdd and Vss.
- Vdd and Vss e.g., ground
- the NAND and NOR gates are logic blocks that provide tri-state capability.
- transistors M2, M3, M5, M6, M9, and M10 are PMOS-type devices (e.g., pFETs) sharing a common N-well, while transistors M1, M7, M8, and M11 are NMOS-type devices (e.g., nFETs).
- the biasing of the N-well (Vnw) depends on the voltage at the PAD node (Vpad) relative to Vdd, as explained as follows:
- Vtp is the threshold voltage of a p-type field-effect transistor (pFET) (e.g., transistor M9).
- pFET p-type field-effect transistor
- transistors M3, M5, and M10 are off. Impedance device M4 pulls node X low. A "low” on node X keeps transistor M2 fully on. This allows transmission of voltages between Vss and Vdd to the gate of transistors M6, allowing M6 to turn on and off. A "low” on node X also turns on transistor M9 thereby biasing the N-well voltage Vnw to Vdd. Transistor M11 is off and does not affect driver operation. Thus, during driving-mode operations, output driver 100 behaves like a regular CMOS driver operating between Vss and Vdd, with the N-well biased to Vdd.
- transistors M6 and M8 are off, and output driver 100 is in high-impedance mode.
- the voltage at nodes G1 and Vnw is Vdd, while node X is kept at Vss.
- Impedance device M4 is preferably a resistor of about 1-10 Kohms.
- impedance device M4 can be a long-channel-length transistor (2X-3X minimum) with a relatively high resistance (e.g., about 1-10 Kohms).
- impedance device M4 can be two or more transistors in cascade.
- transistor M9 Since the voltage at node X (Vx) is approximately equal to Vpad, and Vpad is greater than or equal to (Vdd+Vtp), transistor M9 turns off and transistor M10 turns on. Since transistor M10 is on and transistor M9 is off, N-well voltage Vnw follows Vpad and prevents the parasitic pn diode from getting forward biased. Also, since transistor M5 is on, the voltage at node G1 (Vg1) follows voltage Vpad and prevents leakage of current from node PAD to Vdd. Transistor M2 is off due to the fact that the voltage at node X (Vx) is the same as voltage Vpad.
- transistor M11 Since voltage Vx is greater than (Vdd+Vtp), transistor M11 turns on (assuming that the threshold voltage of an nFET (Vtn) is approximately equal to the threshold voltage Vtp), and the voltage at node G3 (Vg3) is held at Vdd. The drain-to-source voltage Vds across transistor M7 is therefore (Vpad-Vdd). Thus, transistor M11 has the effect of reducing Vds for transistor M7.
- Vdd-Vtn the voltage at node G3 would be (Vdd-Vtn) and the drain-to-source voltage Vds across transistor M7 would be (Vpad-(Vdd-Vtn)).
- a drain-to-source voltage Vds across transistor M7 as high as 4.0 V can cause reliability problems due to phenomena like punch-through or snapback.
- the drain-to-source voltage Vds and the voltage across the oxide for each transistor in output driver 100 is limited to Vdd5-Vdd, where Vdd5 is the operating voltage for a 5 V-technology circuit. None of the transistor junctions are forward biased, and output driver 100 does not require a Vdd5 supply.
- output driver 100 does not require series pFETs on the outputs, thereby saving considerable layout area.
- the present invention therefore, allows 2.5 V-technology circuitry to be interfaced to circuitry implemented in as high as a 5 V technology, which would not be otherwise possible without incurring reliability problems.
- the circuitry of FIG. 1 is implemented in a 2.5-volt technology and can tolerate voltages up to 5 volts, and even higher.
- the "low-voltage" circuitry of FIG. 1 can be interfaced to "high-voltage" circuitry implemented in a technology up to and including a 5-volt technology.
- the voltage of a particular technology is typically defined by the gate-oxide breakdown voltage and/or the punch-through between the source and drain.
- the present invention may also be implemented in a technology other than a 2.5-volt technology.
- circuitry of the present invention may be implemented in any X-volt technology, and that circuitry will be able to tolerate input voltages up to 2X volts.
- the circuitry implemented in the X-volt technology is the "low-voltage” circuitry which can be interfaced to "high-voltage” circuitry implemented in (as high as) a 2X-volt technology.
- circuitry of the present invention may be implemented in a 1.8-volt technology that is adapted to tolerate voltages as high as 3.6 volts.
- such low-voltage 1.8-volt circuitry may be safely interfaced with relatively high-voltage circuitry of a 3.3-volt technology.
- FIG. 1 shows the present invention implemented in a pull-up, pull-down CMOS output driver.
- CMOS output driver Those skilled in the art will understand that the present invention can be implemented in other types of output drivers that are adapted to be interfaced with circuitry in a relatively high-voltage technology.
- the source and the drain of a transistor are referred to as the two channel nodes of the transistor.
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- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Vnw=Vdd for Vpad<(Vdd+Vtp)
Vnw=Vpad for Vpad>(Vdd+Vtp)
Claims (24)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/879,212 US5933027A (en) | 1997-03-14 | 1997-06-19 | High-voltage-tolerant output buffers in low-voltage technology |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/818,844 US5952848A (en) | 1997-03-14 | 1997-03-14 | High-voltage tolerant input buffer in low-voltage technology |
US08/879,212 US5933027A (en) | 1997-03-14 | 1997-06-19 | High-voltage-tolerant output buffers in low-voltage technology |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US08/818,844 Continuation-In-Part US5952848A (en) | 1997-03-14 | 1997-03-14 | High-voltage tolerant input buffer in low-voltage technology |
Publications (1)
Publication Number | Publication Date |
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US5933027A true US5933027A (en) | 1999-08-03 |
Family
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Family Applications (2)
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US08/818,844 Expired - Lifetime US5952848A (en) | 1997-03-14 | 1997-03-14 | High-voltage tolerant input buffer in low-voltage technology |
US08/879,212 Expired - Lifetime US5933027A (en) | 1997-03-14 | 1997-06-19 | High-voltage-tolerant output buffers in low-voltage technology |
Family Applications Before (1)
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US08/818,844 Expired - Lifetime US5952848A (en) | 1997-03-14 | 1997-03-14 | High-voltage tolerant input buffer in low-voltage technology |
Country Status (6)
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US (2) | US5952848A (en) |
EP (1) | EP0865163A1 (en) |
JP (1) | JPH10270649A (en) |
KR (1) | KR19980080221A (en) |
CN (1) | CN1196609A (en) |
TW (1) | TW421878B (en) |
Cited By (35)
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US6087881A (en) * | 1998-07-23 | 2000-07-11 | International Business Machines Corporation | Integrated circuit dual level shift predrive circuit |
US6137313A (en) * | 1997-06-20 | 2000-10-24 | Altera Corporation | Resistive pull-up device for I/O pin |
US6198316B1 (en) * | 1999-09-16 | 2001-03-06 | International Business Machines Corporation | CMOS off-chip driver circuit |
US6208178B1 (en) | 2000-02-23 | 2001-03-27 | Pericom Semiconductor Corp. | CMOS over voltage-tolerant output buffer without transmission gate |
US6236236B1 (en) * | 1999-06-02 | 2001-05-22 | National Semiconductor Corporation | 2.5 volt input/output buffer circuit tolerant to 3.3 and 5 volts |
DE10031837C1 (en) * | 2000-06-30 | 2001-06-13 | Texas Instruments Deutschland | Complementary MOSFET bus driver circuit has input and output stages each provided with 2 complementary MOSFET's connected in series with diode between MOSFET's of input stage bridged by MOSFET |
US6329835B1 (en) | 2000-02-23 | 2001-12-11 | Pericom Semiconductor Corp. | Quiet output buffers with neighbor sensing of wide bus and control signals |
US6414515B1 (en) * | 1999-12-20 | 2002-07-02 | Texas Instruments Incorporated | Failsafe interface circuit with extended drain devices |
US6429703B1 (en) * | 2000-09-06 | 2002-08-06 | Via Technologies, Inc. | Output circuit for high-frequency transmission applications |
US6483346B2 (en) | 2000-11-15 | 2002-11-19 | Texas Instruments Incorporated | Failsafe interface circuit with extended drain services |
US20020175743A1 (en) * | 2001-01-09 | 2002-11-28 | Ajit Janardhanan S. | Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations |
US6693469B2 (en) | 2001-05-01 | 2004-02-17 | Lucent Technologies Inc. | Buffer interface architecture |
US20040222823A1 (en) * | 2003-05-09 | 2004-11-11 | Todd Ronald C. | Overvoltage detector |
US20050041346A1 (en) * | 2003-08-20 | 2005-02-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuit and method for ESD protection |
US20050134315A1 (en) * | 2003-10-24 | 2005-06-23 | Nec Electronics Corporation | Output circuit |
US20050184789A1 (en) * | 2004-02-20 | 2005-08-25 | Fujitsu Limited | Converting signals from a low voltage domain to a high voltage domain |
US20050189963A1 (en) * | 2003-05-28 | 2005-09-01 | Fujitsu Limited | Semiconductor device |
US20050286333A1 (en) * | 2004-06-08 | 2005-12-29 | Gupta Sushil K | High-voltage tolerant input buffer circuit |
US20060066355A1 (en) * | 2004-09-28 | 2006-03-30 | Vincent Gosmain | Voltage tolerant structure for I/O cells |
WO2006036449A2 (en) * | 2004-09-28 | 2006-04-06 | Atmel Corporation | Voltage tolerant structure for i/o cells |
US20060158224A1 (en) * | 2005-01-14 | 2006-07-20 | Elite Semiconductor Memory Technology, Inc. | Output driver with feedback slew rate control |
US7230810B1 (en) | 2004-12-09 | 2007-06-12 | Lattice Semiconductor Corporation | Dynamic over-voltage protection scheme for integrated-circuit devices |
US20090002028A1 (en) * | 2007-06-28 | 2009-01-01 | Amazing Microelectronic Corporation | Mixed-voltage i/o buffer to limit hot-carrier degradation |
US7505752B1 (en) | 2005-07-25 | 2009-03-17 | Lattice Semiconductor Corporation | Receiver for differential and reference-voltage signaling with programmable common mode |
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US7547995B1 (en) | 2006-02-02 | 2009-06-16 | Lattice Semiconductor Corporation | Dynamic over-voltage protection scheme for interface circuitry |
US20100156504A1 (en) * | 2006-06-30 | 2010-06-24 | Masleid Robert P | Cross point switch |
US20100265622A1 (en) * | 2009-04-15 | 2010-10-21 | International Business Machines Corporation | Robust esd protection circuit, method and design structure for tolerant and failsafe designs |
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US9692398B2 (en) | 2014-08-25 | 2017-06-27 | Micron Technology, Inc. | Apparatuses and methods for voltage buffering |
US9793706B2 (en) | 2012-04-20 | 2017-10-17 | Vishay-Siliconix | Current limiting systems and methods |
CN108667451A (en) * | 2017-03-31 | 2018-10-16 | 意法半导体国际有限公司 | Negative voltage tolerance I/O circuitry for I/O pad |
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US11398822B2 (en) | 2018-10-24 | 2022-07-26 | Ams International Ag | Output driver with reverse current blocking capabilities |
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US6126258A (en) * | 1999-02-12 | 2000-10-03 | Agilent Technologies | System and method for interfacing signals with a processing element |
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US6628159B2 (en) * | 1999-09-17 | 2003-09-30 | International Business Machines Corporation | SOI voltage-tolerant body-coupled pass transistor |
US6362652B1 (en) * | 1999-12-20 | 2002-03-26 | Fujitsu Microelectronics, Inc. | High voltage buffer for submicron CMOS |
US6262600B1 (en) * | 2000-02-14 | 2001-07-17 | Analog Devices, Inc. | Isolator for transmitting logic signals across an isolation barrier |
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JPWO2003065455A1 (en) * | 2002-01-31 | 2005-05-26 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit |
CN100576194C (en) * | 2007-04-24 | 2009-12-30 | 中芯国际集成电路制造(上海)有限公司 | The system and method that is used for hot plug |
US8044684B1 (en) | 2010-04-15 | 2011-10-25 | Stmicroelectronics Pvt. Ltd. | Input and output buffer including a dynamic driver reference generator |
US9086711B2 (en) * | 2013-01-14 | 2015-07-21 | Qualcomm Incorporated | Single-ended high voltage input-capable comparator circuit |
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4739193A (en) * | 1986-10-30 | 1988-04-19 | Rca Corporation | Drive circuit with limited signal transition rate for RFI reduction |
US5004936A (en) * | 1989-03-31 | 1991-04-02 | Texas Instruments Incorporated | Non-loading output driver circuit |
US5418476A (en) * | 1994-07-28 | 1995-05-23 | At&T Corp. | Low voltage output buffer with improved speed |
US5629634A (en) * | 1995-08-21 | 1997-05-13 | International Business Machines Corporation | Low-power, tristate, off-chip driver circuit |
US5635861A (en) * | 1995-05-23 | 1997-06-03 | International Business Machines Corporation | Off chip driver circuit |
US5748010A (en) * | 1995-03-30 | 1998-05-05 | Maxim Integrated Products | Logic signal level translation apparatus having very low dropout with respect to the powering rails |
US5764077A (en) * | 1996-02-05 | 1998-06-09 | Texas Instruments Incorporated | 5 volt tolerant I/O buffer circuit |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0478221A (en) * | 1990-07-18 | 1992-03-12 | Olympus Optical Co Ltd | Integrated circuit for level shift |
US5304867A (en) * | 1991-12-12 | 1994-04-19 | At&T Bell Laboratories | CMOS input buffer with high speed and low power |
AU6445694A (en) * | 1993-03-24 | 1994-10-11 | Apple Computer, Inc. | Differential- to single-ended cmos converter |
US5432467A (en) * | 1993-05-07 | 1995-07-11 | Altera Corporation | Programmable logic device with low power voltage level translator |
US5378945A (en) * | 1993-07-26 | 1995-01-03 | Digital Equipment Corporation | Voltage level converting buffer circuit |
FR2722045B1 (en) * | 1994-06-30 | 1996-08-23 | Alcatel Telspace | METHOD FOR SEARCHING FOR TIME SYNCHRONIZATION ACQUISITION BETWEEN A SPREAD SEQUENCE OF A RECEIVER AND THAT OF A TRANSMITTER |
US5670898A (en) * | 1995-11-22 | 1997-09-23 | Silicon Graphics, Inc. | Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance |
-
1997
- 1997-03-14 US US08/818,844 patent/US5952848A/en not_active Expired - Lifetime
- 1997-06-19 US US08/879,212 patent/US5933027A/en not_active Expired - Lifetime
-
1998
- 1998-02-05 TW TW087101509A patent/TW421878B/en not_active IP Right Cessation
- 1998-03-03 JP JP10050645A patent/JPH10270649A/en active Pending
- 1998-03-03 EP EP98301550A patent/EP0865163A1/en not_active Withdrawn
- 1998-03-12 CN CN98105460A patent/CN1196609A/en active Pending
- 1998-03-13 KR KR1019980008437A patent/KR19980080221A/en not_active Application Discontinuation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4739193A (en) * | 1986-10-30 | 1988-04-19 | Rca Corporation | Drive circuit with limited signal transition rate for RFI reduction |
US5004936A (en) * | 1989-03-31 | 1991-04-02 | Texas Instruments Incorporated | Non-loading output driver circuit |
US5418476A (en) * | 1994-07-28 | 1995-05-23 | At&T Corp. | Low voltage output buffer with improved speed |
US5748010A (en) * | 1995-03-30 | 1998-05-05 | Maxim Integrated Products | Logic signal level translation apparatus having very low dropout with respect to the powering rails |
US5635861A (en) * | 1995-05-23 | 1997-06-03 | International Business Machines Corporation | Off chip driver circuit |
US5629634A (en) * | 1995-08-21 | 1997-05-13 | International Business Machines Corporation | Low-power, tristate, off-chip driver circuit |
US5764077A (en) * | 1996-02-05 | 1998-06-09 | Texas Instruments Incorporated | 5 volt tolerant I/O buffer circuit |
Cited By (74)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6137313A (en) * | 1997-06-20 | 2000-10-24 | Altera Corporation | Resistive pull-up device for I/O pin |
US6087881A (en) * | 1998-07-23 | 2000-07-11 | International Business Machines Corporation | Integrated circuit dual level shift predrive circuit |
US6236236B1 (en) * | 1999-06-02 | 2001-05-22 | National Semiconductor Corporation | 2.5 volt input/output buffer circuit tolerant to 3.3 and 5 volts |
US6198316B1 (en) * | 1999-09-16 | 2001-03-06 | International Business Machines Corporation | CMOS off-chip driver circuit |
US6414515B1 (en) * | 1999-12-20 | 2002-07-02 | Texas Instruments Incorporated | Failsafe interface circuit with extended drain devices |
US6208178B1 (en) | 2000-02-23 | 2001-03-27 | Pericom Semiconductor Corp. | CMOS over voltage-tolerant output buffer without transmission gate |
US6329835B1 (en) | 2000-02-23 | 2001-12-11 | Pericom Semiconductor Corp. | Quiet output buffers with neighbor sensing of wide bus and control signals |
DE10031837C1 (en) * | 2000-06-30 | 2001-06-13 | Texas Instruments Deutschland | Complementary MOSFET bus driver circuit has input and output stages each provided with 2 complementary MOSFET's connected in series with diode between MOSFET's of input stage bridged by MOSFET |
US6429703B1 (en) * | 2000-09-06 | 2002-08-06 | Via Technologies, Inc. | Output circuit for high-frequency transmission applications |
US6614262B2 (en) | 2000-11-15 | 2003-09-02 | Texas Instruments Incorporated | Failsafe interface circuit with extended drain devices |
US6483346B2 (en) | 2000-11-15 | 2002-11-19 | Texas Instruments Incorporated | Failsafe interface circuit with extended drain services |
US6856176B2 (en) | 2001-01-09 | 2005-02-15 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit |
US20090224821A1 (en) * | 2001-01-09 | 2009-09-10 | Broadcom Corporation | Sub-Micron High Input Voltage Tolerant Input Output (I/O) Circuit |
US20040017229A1 (en) * | 2001-01-09 | 2004-01-29 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit |
US20040017230A1 (en) * | 2001-01-09 | 2004-01-29 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit |
US7138847B2 (en) | 2001-01-09 | 2006-11-21 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations |
US7292072B2 (en) | 2001-01-09 | 2007-11-06 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit |
US6847248B2 (en) | 2001-01-09 | 2005-01-25 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations |
US20020175743A1 (en) * | 2001-01-09 | 2002-11-28 | Ajit Janardhanan S. | Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations |
US20080068050A1 (en) * | 2001-01-09 | 2008-03-20 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit |
US20050078421A1 (en) * | 2001-01-09 | 2005-04-14 | Broadcom Corporation Pursuant | Sub-micron high input voltage tolerant input output (I/O) circuit |
US6985015B2 (en) | 2001-01-09 | 2006-01-10 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit |
US7746124B2 (en) | 2001-01-09 | 2010-06-29 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit |
US6914456B2 (en) * | 2001-01-09 | 2005-07-05 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit |
US20030094980A1 (en) * | 2001-01-09 | 2003-05-22 | Broadcom Corporation | Sub-Micron high input voltage tolerant input output (I/O) circuit |
US20050248892A1 (en) * | 2001-01-09 | 2005-11-10 | Ajit Janardhanan S | Sub-micron high input voltage tolerant input output (I/O) circuit |
US6949964B2 (en) | 2001-01-09 | 2005-09-27 | Broadcom Corporation | Sub-micron high input voltage tolerant input output (I/O) circuit |
US20050231864A1 (en) * | 2001-01-09 | 2005-10-20 | Broadcom Corporation Pursuant | Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations |
US6693469B2 (en) | 2001-05-01 | 2004-02-17 | Lucent Technologies Inc. | Buffer interface architecture |
US6885223B2 (en) * | 2003-05-09 | 2005-04-26 | Bae Systems Information And Electronic Systems Integration Inc. | Overvoltage detector |
US20040222823A1 (en) * | 2003-05-09 | 2004-11-11 | Todd Ronald C. | Overvoltage detector |
US20050189963A1 (en) * | 2003-05-28 | 2005-09-01 | Fujitsu Limited | Semiconductor device |
EP1628399A1 (en) * | 2003-05-28 | 2006-02-22 | Fujitsu Limited | Semiconductor device |
US7208978B2 (en) | 2003-05-28 | 2007-04-24 | Fujitsu Limited | Semiconductor device |
EP1628399A4 (en) * | 2003-05-28 | 2006-07-26 | Fujitsu Ltd | Semiconductor device |
US7583484B2 (en) | 2003-08-20 | 2009-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit and method for ESD protection |
US20050041346A1 (en) * | 2003-08-20 | 2005-02-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuit and method for ESD protection |
US7088126B2 (en) * | 2003-10-24 | 2006-08-08 | Nec Electronics Corporation | Output circuit |
US20050134315A1 (en) * | 2003-10-24 | 2005-06-23 | Nec Electronics Corporation | Output circuit |
US7002392B2 (en) * | 2004-02-20 | 2006-02-21 | Fujitsu Limited | Converting signals from a low voltage domain to a high voltage domain |
US20050184789A1 (en) * | 2004-02-20 | 2005-08-25 | Fujitsu Limited | Converting signals from a low voltage domain to a high voltage domain |
US20050286333A1 (en) * | 2004-06-08 | 2005-12-29 | Gupta Sushil K | High-voltage tolerant input buffer circuit |
US7164305B2 (en) * | 2004-06-08 | 2007-01-16 | Stmicroelectronics Pvt. Ltd. | High-voltage tolerant input buffer circuit |
WO2006036449A3 (en) * | 2004-09-28 | 2006-09-28 | Atmel Corp | Voltage tolerant structure for i/o cells |
US7180331B2 (en) * | 2004-09-28 | 2007-02-20 | Atmel Corporation | Voltage tolerant structure for I/O cells |
WO2006036449A2 (en) * | 2004-09-28 | 2006-04-06 | Atmel Corporation | Voltage tolerant structure for i/o cells |
US20060066355A1 (en) * | 2004-09-28 | 2006-03-30 | Vincent Gosmain | Voltage tolerant structure for I/O cells |
US7230810B1 (en) | 2004-12-09 | 2007-06-12 | Lattice Semiconductor Corporation | Dynamic over-voltage protection scheme for integrated-circuit devices |
US20060158224A1 (en) * | 2005-01-14 | 2006-07-20 | Elite Semiconductor Memory Technology, Inc. | Output driver with feedback slew rate control |
US7505752B1 (en) | 2005-07-25 | 2009-03-17 | Lattice Semiconductor Corporation | Receiver for differential and reference-voltage signaling with programmable common mode |
US7547995B1 (en) | 2006-02-02 | 2009-06-16 | Lattice Semiconductor Corporation | Dynamic over-voltage protection scheme for interface circuitry |
US20100156504A1 (en) * | 2006-06-30 | 2010-06-24 | Masleid Robert P | Cross point switch |
US9178505B2 (en) | 2006-06-30 | 2015-11-03 | Intellectual Venture Funding Llc | Cross point switch |
US9595968B2 (en) | 2006-06-30 | 2017-03-14 | Intellectual Ventures Holding 81 Llc | Cross point switch |
US20090002028A1 (en) * | 2007-06-28 | 2009-01-01 | Amazing Microelectronic Corporation | Mixed-voltage i/o buffer to limit hot-carrier degradation |
US20090104989A1 (en) * | 2007-10-23 | 2009-04-23 | Igt | Separable backlighting system |
US20100265622A1 (en) * | 2009-04-15 | 2010-10-21 | International Business Machines Corporation | Robust esd protection circuit, method and design structure for tolerant and failsafe designs |
US8760827B2 (en) * | 2009-04-15 | 2014-06-24 | International Business Machines Corporation | Robust ESD protection circuit, method and design structure for tolerant and failsafe designs |
US9793706B2 (en) | 2012-04-20 | 2017-10-17 | Vishay-Siliconix | Current limiting systems and methods |
US10630071B2 (en) | 2012-04-20 | 2020-04-21 | Vishay-Siliconix, LLC | Current limiting systems and methods |
US8836404B2 (en) * | 2012-08-02 | 2014-09-16 | Vishay-Siliconix | Circuit for preventing reverse conduction |
US9787309B2 (en) | 2012-08-02 | 2017-10-10 | Vishay-Siliconix | Methods for preventing reverse conduction |
CN104660242A (en) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Pull-up resistor circuit |
CN104660242B (en) * | 2013-11-19 | 2018-04-27 | 中芯国际集成电路制造(上海)有限公司 | Pull-up resistor circuit |
US9692398B2 (en) | 2014-08-25 | 2017-06-27 | Micron Technology, Inc. | Apparatuses and methods for voltage buffering |
US9762215B1 (en) | 2014-08-25 | 2017-09-12 | Micron Technology, Inc. | Apparatuses and methods for voltage buffering |
CN108667451A (en) * | 2017-03-31 | 2018-10-16 | 意法半导体国际有限公司 | Negative voltage tolerance I/O circuitry for I/O pad |
CN108667451B (en) * | 2017-03-31 | 2022-06-24 | 意法半导体国际有限公司 | Negative voltage tolerant IO circuitry for IO pads |
WO2019042643A1 (en) * | 2017-08-29 | 2019-03-07 | Ams Ag | High-voltage output driver for a sensor device with reverse current blocking |
CN111034048A (en) * | 2017-08-29 | 2020-04-17 | ams有限公司 | High voltage output driver for a sensor device with reverse current blocking |
US11290107B2 (en) | 2017-08-29 | 2022-03-29 | Ams Ag | High-voltage output driver for a sensor device with reverse current blocking |
EP3451537A1 (en) * | 2017-08-29 | 2019-03-06 | ams AG | High-voltage output driver for a sensor device with reverse current blocking |
CN111034048B (en) * | 2017-08-29 | 2024-06-21 | ams有限公司 | High voltage output driver for a sensor device with reverse current blocking |
US11398822B2 (en) | 2018-10-24 | 2022-07-26 | Ams International Ag | Output driver with reverse current blocking capabilities |
Also Published As
Publication number | Publication date |
---|---|
CN1196609A (en) | 1998-10-21 |
EP0865163A1 (en) | 1998-09-16 |
KR19980080221A (en) | 1998-11-25 |
TW421878B (en) | 2001-02-11 |
JPH10270649A (en) | 1998-10-09 |
US5952848A (en) | 1999-09-14 |
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