US20160233132A9 - Integrated circuit having chemically modified spacer surface - Google Patents
Integrated circuit having chemically modified spacer surface Download PDFInfo
- Publication number
- US20160233132A9 US20160233132A9 US13/427,062 US201213427062A US2016233132A9 US 20160233132 A9 US20160233132 A9 US 20160233132A9 US 201213427062 A US201213427062 A US 201213427062A US 2016233132 A9 US2016233132 A9 US 2016233132A9
- Authority
- US
- United States
- Prior art keywords
- dielectric material
- sidewall spacers
- spacers
- gate stack
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 94
- 239000003989 dielectric material Substances 0.000 claims abstract description 101
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000007704 transition Effects 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 29
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 229910052799 carbon Inorganic materials 0.000 claims description 15
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 239000004215 Carbon black (E152) Substances 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 229930195733 hydrocarbon Natural products 0.000 claims description 4
- 150000002430 hydrocarbons Chemical class 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims 4
- 230000008569 process Effects 0.000 description 17
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 239000007943 implant Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- 239000000203 mixture Substances 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- VYIRVGYSUZPNLF-UHFFFAOYSA-N n-(tert-butylamino)silyl-2-methylpropan-2-amine Chemical compound CC(C)(C)N[SiH2]NC(C)(C)C VYIRVGYSUZPNLF-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 210000002381 plasma Anatomy 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- -1 silicide ion Chemical class 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- Disclosed embodiments relate to semiconductor processing and integrated circuit (IC) devices therefrom which include metal-oxide-semiconductor (MOS) transistors, including MOS transistors having multi-layer sidewall spacers.
- MOS metal-oxide-semiconductor
- Thin silicon nitride sidewall spacers are commonly used as an implant mask to provide a space between the lightly doped drain (LDD) implants into the semiconductor surface and the gate stack.
- LDD lightly doped drain
- a typical process flow has a first spacer layer that acts first as an offset spacer, then as an underlayer/etch-stop while additional films, such as disposable second sidewall spacer comprising SiGe, is deposited on top, used, which is then subsequently removed.
- hot phosphoric acid (HPA) is used to remove the second sidewall spacer.
- etch stop characteristics can be lost resulting in inadvertent removal of the silicon nitride offset sidewall spacer, and as a result subsequent shorting between the gate and source and/or drain, such as due to a subsequently deposited silicide ion the gate, source and drain.
- semiconductor devices are shrunk in size, and the distance between the top of the gate stack and the top surface of the source/drain regions is reduced, the probability of electrical shorts due to the silicide forming on the sidewalls of the gate stack increases.
- Disclosed embodiments describe solutions to the above-described inadvertent removal of thin sidewall spacers for metal-oxide-semiconductor (MOS) transistors that use multi-layer sidewall spacers.
- MOS metal-oxide-semiconductor
- the second material can substantially increase the etch resistance compared to the first spacer material.
- the subsequent removal of a disposable second spacer on the first spacer will not remove the first spacer since the second dielectric material can act as an etch stop, or at least provide some etch protection for the first dielectric material of the first spacer.
- One disclosed embodiment comprises a method of fabricating an integrated circuit that includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric.
- the first dielectric material is etched, such as using RIE, to form sidewall spacers on sidewalls of the gate stack.
- a top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers.
- the second dielectric material is chemically bonded across a transition region to the first dielectric material.
- ion implanting can follow to form lightly doped drains (LDDs) in the semiconductor surface lateral to the gate stack.
- LDDs lightly doped drains
- Second spacers are then formed on the surface converted sidewall spacers.
- Sources and drains are then formed lateral to the gate stack.
- Ion implanting can be used to form sources and drains in the semiconductor surface lateral to the gate stack after forming the second spacers.
- the second sidewall spacers can be used for a SiGe S/D process (e.g., where recesses are formed typically in the PMOS region and replaced with SiGe).
- the second spacers can then be selective removed after the source/drain formation.
- the surface of chemically converted layer remains intact after the selective etching, as does the first dielectric material protected by the surface converted layer.
- FIG. 1 is a flow chart that shows steps in an example method for fabricating an integrated circuit (IC) device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment.
- FIG. 2A-2F are cross-sectional diagrams depicting processing progression for an example method of forming an IC device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment, while FIG. 2G shows the resulting spacer structure after a known spacer process showing the results from the inadvertent removal of the nitride offset spacer.
- FIG. 3 is a cross sectional view of a portion of an IC device including MOS transistors having sidewall spacers comprising a second dielectric material on a first dielectric material, wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material, according to an example embodiment.
- FIG. 4 shows the composition as a function of thickness for an example surface converted sidewall spacer, including a highly simplified depiction of the chemical bonding provided across the thickness of the surface converted sidewall spacer, according to an example embodiment.
- Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
- FIG. 1 is a flow chart that shows steps in an example method 100 for fabricating an IC device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment.
- Step 101 comprises depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon comprising a gate electrode on a gate dielectric.
- Step 102 comprises etching the first dielectric material to form sidewall spacers on sidewalls of the gate stack, such as using RIE.
- Step 103 comprises chemically converting a top surface of the first dielectric material to a second dielectric material by adding at least one element to provide surface converted sidewall spacers.
- the second dielectric material is chemically bonded across a transition region to the first dielectric material.
- the chemically converted top surface of the sidewall spacer becomes an etch stop by adding at least one element to form a second dielectric material, that substantially increases the wet etch resistance of the film as compared to the unconverted first dielectric material, such as to a hot phosphoric acid (HPA) etch.
- the added element is carbon. In another embodiment both carbon and oxygen are added.
- the first dielectric material comprises BTBAS-derived silicon nitride, and carbon is added to the top surface of the silicon nitride forming a thin layer, typically 10 to 20 Angstroms thick, of a second dielectric material comprising a silicon carbide (SiC), silicon carbonitride (SiCN) and/or silicon oxy-carbonitride (SiOCN) film.
- SiC silicon carbide
- SiCN silicon carbonitride
- SiOCN silicon oxy-carbonitride
- SiC, SiCN, or SiOCN were formed, which were all found to be are largely impervious to HPA etch at temperatures below 215° C. Since HPA is generally used at temperatures between 120 and 180° C., the underlying silicon nitride sidewall spacer is protected by the second dielectric material.
- the relationship of the second dielectric material to the first dielectric material for disclosed surface converted sidewall spacers being chemically bonded together is distinct from known arrangements resulting from the vapor deposition (e.g., chemical vapor deposition) of a second dielectric material on a first dielectric material, where the second dielectric material becomes attached to the first dielectric material by comparatively weak Vander walls forces.
- the area of the second dielectric material matches the area of the first dielectric material.
- the area of the second dielectric material will be different as compared to the area of the first dielectric material due to the etching process required for spacer formation.
- Step 104 comprises ion implanting to form lightly doped drains (LDDs) in the semiconductor surface lateral to the gate stack.
- LDDs lightly doped drains
- the PMOS transistors and NMOS transistors generally each receive separate LDD implants.
- Step 105 comprises forming second spacers on the surface converted sidewall spacers.
- Step 106 comprises forming sources and drains lateral to the gate stack. Ion implanting can be used to form sources and drains in the semiconductor surface lateral to the gate stack after forming the second spacers.
- the PMOS transistors and NMOS transistors each receive separate source/drain implants.
- Step 107 comprises selectively removing the second spacers after the source/drain formation (step 106 ).
- the surface of chemically converted layer remains intact after the selective etching, as does the first dielectric material protected by the surface converted layer.
- FIG. 2A-2F are cross-sectional diagrams showing processing progression for an example method of fabricating an IC device having surface converted sidewall spacers, according to an example embodiment, while FIG. 2G shows the resulting spacer structure after a known spacer process showing inadvertent removal of the sidewall spacer.
- FIG. 2A shows a gate stack comprising a gate electrode 211 on a gate dielectric 212 before any sidewall spacer is formed on a substrate 305 .
- Substrate 305 can comprise any substrate material, such as silicon, silicon-germanium, as well as II-VI and III-V substrates, as well as SOI substrates.
- the gate electrode 211 can comprise polysilicon, or a variety of other gate electrode materials.
- the gate dielectric 212 can comprise a variety of gate dielectrics, including optional high-k dielectrics defined hereon as having k>3.9, typically a k>7. In one particular embodiment, the high-k dielectric comprises silicon oxynitride.
- FIG. 2B shows the gate stack after a sidewall spacer (e.g., a nitride offset spacer) 215 is formed, such as a silicon nitride offset spacer by a RIE process.
- FIG. 2C shows the results after an ion implantation process, such as LDD ion implantation to form LDD regions 225 , that utilized implant blocking provided by the sidewall spacer 215 .
- FIG. 2D shows the resulting structure after disclosed chemical surface conversion step comprising flowing a hydrocarbon gas that forms the surface converted layer 216 shown.
- FIG. 2E shows the gate stack 211 / 212 after a subsequent disposable second spacer 235 is formed, such as by chemical deposition followed by RIE. For a typical CMOS process the PMOS transistors and NMOS transistors each then receive separate source/drain implants.
- FIG. 2F shows the gate stack 212 / 211 after the disposable second spacer 235 has been selectively removed, such as by a hot (e.g., 120 to 180° C.) HPA etch. Note the surface converted layer 216 remains intact after the etch, as does the sidewall spacer 215 protected by the surface converted layer 216 . Without a disclosed surface converted layer, the sidewall spacer 215 , such as it comprises silicon nitride, is subject to removal using the process used to remove the disposable second spacer 235 .
- FIG. 2G shows the resulting spacer structure after a known spacer process showing the results after inadvertent complete removal of the sidewall spacer 215 .
- FIG. 3 is a cross sectional view of a portion of an IC device 300 (e.g., a semiconductor die) including MOS transistors having surface converted sidewall spacers comprising a second dielectric material on a first dielectric material, wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material, according to an example embodiment.
- BEOL Back end of the line
- IC 300 includes a substrate 305 , such as a p-type silicon or p-type silicon-germanium substrate, having a semiconductor surface 306 .
- Optional trench isolation 308 is shown, such as shallow trench isolation (STI).
- An n-channel MOS (NMOS) transistor 310 is shown, along with a p-channel MOS (PMOS) transistor 320 that is within an n-well 307 .
- STI shallow trench isolation
- NMOS transistor 310 includes a gate stack including a gate electrode 311 on a gate dielectric 312 having sidewall spacers on sidewalls of the gate stack.
- the sidewall spacers comprise a second dielectric material 315 a on a first dielectric material 315 b , wherein the second dielectric material 315 a is chemically bonded across a transition region 315 c to the first dielectric material 315 b .
- the second dielectric material 315 a comprises carbon and the first dielectric material does not comprise carbon, wherein “not comprising carbon” as used herein refers to a wt. % of C ⁇ 3%.
- NMOS transistor 310 includes source 321 and drain 322 regions lateral to the sidewall spacers, and include lightly doped extensions 321 a and 322 a .
- a silicide layer 316 is shown on the gate electrode 311 and the source 321 and drain 322 .
- PMOS transistor 320 includes a gate stack including a gate electrode 331 on a gate dielectric 332 (which can be the same material as gate dielectric 312 under gate electrode 311 ) having sidewall spacers on sidewalls of the gate stack, comprising the second dielectric material 315 a on a first dielectric material 315 b , wherein the second dielectric material 315 a is chemically bonded across a transition region 315 c to the first dielectric material 315 b .
- the second dielectric material 315 a comprises carbon and the first dielectric material does not comprise carbon.
- PMOS transistor 320 includes source 341 and drain 342 regions lateral to the sidewall spacers, and include lightly doped extensions 341 a and 342 a .
- Silicide layer 316 is shown on the gate electrode 331 and on the source 341 and drain 342 .
- the total thickness of the sidewall spacer 315 a / 315 c / 315 b at its widest point at its base is generally ⁇ 100 Angstroms, such as 40 to 70 Angstroms thick.
- second dielectric material 315 a is about 5 to 10 angstroms thick
- transition region 315 c is 15 to 25 Angstroms thick
- the first dielectric material 315 b is 20 to 30 Angstroms thick.
- FIG. 4 shows the composition as a function of thickness for an example surface converted sidewall spacer 400 , including a highly simplified depiction of the chemical bonding provided across the thickness of the surface converted sidewall spacer 400 , according to an example embodiment.
- the surface converted sidewall spacer 400 includes a non-constant chemical composition profile across its thickness comprising a first dielectric material 315 b on the sidewall of a gate stack material and a chemically converted top (outer) surface comprising a second dielectric material 315 a chemically bonded across a transition region 315 c to the first dielectric material 315 b .
- the first dielectric material 315 b comprises silicon nitride (roughly Si 3 N 4 )
- the second dielectric material 315 a comprises silicon carbide (SiC)
- the transition region 315 c includes a material comprising Si, N and C, where the C content decreases and the N content increases as the distance to the second dielectric material 315 a /gate stack is reduced.
- Disclosed semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc.
- the semiconductor die can be formed from a variety of processes including bipolar, CMOS, BiCMOS and MEMS.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- This application claims the benefit of Provisional Application Ser. No. 61/463,308, entitled “Surface modification to optimize wet etch resistance” filed Mar. 28, 2011, which is herein incorporated by reference in its entirety.
- Disclosed embodiments relate to semiconductor processing and integrated circuit (IC) devices therefrom which include metal-oxide-semiconductor (MOS) transistors, including MOS transistors having multi-layer sidewall spacers.
- While processing semiconductor wafers it is often advantageous to deposit or form films that can later act as etch stop layers when subsequently deposited or formed films are removed. However, if the film does not have sufficient etch resistance during later processing, such films can be inadvertently removed.
- One example of inadvertent removal involves thin silicon nitride sidewall (or offset) spacers for MOS transistors. Thin silicon nitride sidewall spacers are commonly used as an implant mask to provide a space between the lightly doped drain (LDD) implants into the semiconductor surface and the gate stack. A typical process flow has a first spacer layer that acts first as an offset spacer, then as an underlayer/etch-stop while additional films, such as disposable second sidewall spacer comprising SiGe, is deposited on top, used, which is then subsequently removed. In one process flow hot phosphoric acid (HPA) is used to remove the second sidewall spacer. However, even silicon nitride spacers formed from bis-tertiarybutylamino-silane (BTBAS) and ammonia reagents, where BTBAS-based silicon nitride is known to be the most wet etch resistant silicon nitride film to HPA, are not always capable of stopping the HPA etch when the disposable SiGe second sidewall spacer is removed. In particular, if the silicon nitride sidewall spacer has been exposed to reducing chemistries, such as plasmas containing H2 or N2, etch stop characteristics can be lost resulting in inadvertent removal of the silicon nitride offset sidewall spacer, and as a result subsequent shorting between the gate and source and/or drain, such as due to a subsequently deposited silicide ion the gate, source and drain. Moreover, as semiconductor devices are shrunk in size, and the distance between the top of the gate stack and the top surface of the source/drain regions is reduced, the probability of electrical shorts due to the silicide forming on the sidewalls of the gate stack increases.
- Disclosed embodiments describe solutions to the above-described inadvertent removal of thin sidewall spacers for metal-oxide-semiconductor (MOS) transistors that use multi-layer sidewall spacers. By chemically converting the top surface of a first sidewall spacer comprising a first material by adding at least one element to form a second dielectric material, the second material can substantially increase the etch resistance compared to the first spacer material. As a result, the subsequent removal of a disposable second spacer on the first spacer will not remove the first spacer since the second dielectric material can act as an etch stop, or at least provide some etch protection for the first dielectric material of the first spacer.
- One disclosed embodiment comprises a method of fabricating an integrated circuit that includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched, such as using RIE, to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.
- Following forming the surface converted sidewall spacers, ion implanting can follow to form lightly doped drains (LDDs) in the semiconductor surface lateral to the gate stack. Second spacers are then formed on the surface converted sidewall spacers. Sources and drains are then formed lateral to the gate stack. Ion implanting can be used to form sources and drains in the semiconductor surface lateral to the gate stack after forming the second spacers. Alternatively, the second sidewall spacers can be used for a SiGe S/D process (e.g., where recesses are formed typically in the PMOS region and replaced with SiGe). The second spacers can then be selective removed after the source/drain formation. The surface of chemically converted layer remains intact after the selective etching, as does the first dielectric material protected by the surface converted layer.
- Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
-
FIG. 1 is a flow chart that shows steps in an example method for fabricating an integrated circuit (IC) device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment. -
FIG. 2A-2F are cross-sectional diagrams depicting processing progression for an example method of forming an IC device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment, whileFIG. 2G shows the resulting spacer structure after a known spacer process showing the results from the inadvertent removal of the nitride offset spacer. -
FIG. 3 is a cross sectional view of a portion of an IC device including MOS transistors having sidewall spacers comprising a second dielectric material on a first dielectric material, wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material, according to an example embodiment. -
FIG. 4 shows the composition as a function of thickness for an example surface converted sidewall spacer, including a highly simplified depiction of the chemical bonding provided across the thickness of the surface converted sidewall spacer, according to an example embodiment. - Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
-
FIG. 1 is a flow chart that shows steps in anexample method 100 for fabricating an IC device having MOS transistors that include surface converted sidewall spacers, according to an example embodiment.Step 101 comprises depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon comprising a gate electrode on a gate dielectric.Step 102 comprises etching the first dielectric material to form sidewall spacers on sidewalls of the gate stack, such as using RIE. -
Step 103 comprises chemically converting a top surface of the first dielectric material to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material. The chemically converted top surface of the sidewall spacer becomes an etch stop by adding at least one element to form a second dielectric material, that substantially increases the wet etch resistance of the film as compared to the unconverted first dielectric material, such as to a hot phosphoric acid (HPA) etch. In one embodiment the added element is carbon. In another embodiment both carbon and oxygen are added. - In one specific example, the first dielectric material comprises BTBAS-derived silicon nitride, and carbon is added to the top surface of the silicon nitride forming a thin layer, typically 10 to 20 Angstroms thick, of a second dielectric material comprising a silicon carbide (SiC), silicon carbonitride (SiCN) and/or silicon oxy-carbonitride (SiOCN) film. This can be accomplished by exposing a BTBAS silicon nitride film that was previously used as a gate stack sidewall to a flow of 30 to 3000 sccm of ethylene, acetylene, or similar hydrocarbon gas at a temperature generally between 300 and 800° C., and pressure between about 0.1 and 10 Torr, for 15-600 seconds or longer prior to depositing a subsequent disposable spacer film. In experiments performed, SiC, SiCN, or SiOCN were formed, which were all found to be are largely impervious to HPA etch at temperatures below 215° C. Since HPA is generally used at temperatures between 120 and 180° C., the underlying silicon nitride sidewall spacer is protected by the second dielectric material.
- Besides clear process differences, the relationship of the second dielectric material to the first dielectric material for disclosed surface converted sidewall spacers being chemically bonded together is distinct from known arrangements resulting from the vapor deposition (e.g., chemical vapor deposition) of a second dielectric material on a first dielectric material, where the second dielectric material becomes attached to the first dielectric material by comparatively weak Vander walls forces. Moreover, inherently due to the disclosed chemical conversion process, the area of the second dielectric material matches the area of the first dielectric material. In contrast, for a known arrangements resulting from the vapor deposition of a second dielectric material on a first dielectric material, the area of the second dielectric material will be different as compared to the area of the first dielectric material due to the etching process required for spacer formation.
-
Step 104 comprises ion implanting to form lightly doped drains (LDDs) in the semiconductor surface lateral to the gate stack. For a CMOS process the PMOS transistors and NMOS transistors generally each receive separate LDD implants.Step 105 comprises forming second spacers on the surface converted sidewall spacers.Step 106 comprises forming sources and drains lateral to the gate stack. Ion implanting can be used to form sources and drains in the semiconductor surface lateral to the gate stack after forming the second spacers. For a typical CMOS process the PMOS transistors and NMOS transistors each receive separate source/drain implants. However, alternatively, the second sidewall spacers can also be used for a SiGe S/D process (e.g., where recesses are formed typically in the PMOS region and replaced with SiGe).Step 107 comprises selectively removing the second spacers after the source/drain formation (step 106). The surface of chemically converted layer remains intact after the selective etching, as does the first dielectric material protected by the surface converted layer. -
FIG. 2A-2F are cross-sectional diagrams showing processing progression for an example method of fabricating an IC device having surface converted sidewall spacers, according to an example embodiment, whileFIG. 2G shows the resulting spacer structure after a known spacer process showing inadvertent removal of the sidewall spacer.FIG. 2A shows a gate stack comprising agate electrode 211 on agate dielectric 212 before any sidewall spacer is formed on asubstrate 305.Substrate 305 can comprise any substrate material, such as silicon, silicon-germanium, as well as II-VI and III-V substrates, as well as SOI substrates. Thegate electrode 211 can comprise polysilicon, or a variety of other gate electrode materials. Thegate dielectric 212 can comprise a variety of gate dielectrics, including optional high-k dielectrics defined hereon as having k>3.9, typically a k>7. In one particular embodiment, the high-k dielectric comprises silicon oxynitride. -
FIG. 2B shows the gate stack after a sidewall spacer (e.g., a nitride offset spacer) 215 is formed, such as a silicon nitride offset spacer by a RIE process.FIG. 2C shows the results after an ion implantation process, such as LDD ion implantation to formLDD regions 225, that utilized implant blocking provided by thesidewall spacer 215.FIG. 2D shows the resulting structure after disclosed chemical surface conversion step comprising flowing a hydrocarbon gas that forms the surface convertedlayer 216 shown.FIG. 2E shows thegate stack 211/212 after a subsequent disposablesecond spacer 235 is formed, such as by chemical deposition followed by RIE. For a typical CMOS process the PMOS transistors and NMOS transistors each then receive separate source/drain implants. - The disposable
second spacer 235 is then selectively removed after source/drain formation.FIG. 2F shows thegate stack 212/211 after the disposablesecond spacer 235 has been selectively removed, such as by a hot (e.g., 120 to 180° C.) HPA etch. Note the surface convertedlayer 216 remains intact after the etch, as does thesidewall spacer 215 protected by the surface convertedlayer 216. Without a disclosed surface converted layer, thesidewall spacer 215, such as it comprises silicon nitride, is subject to removal using the process used to remove the disposablesecond spacer 235.FIG. 2G shows the resulting spacer structure after a known spacer process showing the results after inadvertent complete removal of thesidewall spacer 215. -
FIG. 3 is a cross sectional view of a portion of an IC device 300 (e.g., a semiconductor die) including MOS transistors having surface converted sidewall spacers comprising a second dielectric material on a first dielectric material, wherein the second dielectric material is chemically bonded across a transition region to the first dielectric material, according to an example embodiment. Back end of the line (BEOL) metallization is not shown for simplicity.IC 300 includes asubstrate 305, such as a p-type silicon or p-type silicon-germanium substrate, having asemiconductor surface 306.Optional trench isolation 308 is shown, such as shallow trench isolation (STI). An n-channel MOS (NMOS)transistor 310 is shown, along with a p-channel MOS (PMOS)transistor 320 that is within an n-well 307. -
NMOS transistor 310 includes a gate stack including agate electrode 311 on agate dielectric 312 having sidewall spacers on sidewalls of the gate stack. The sidewall spacers comprise a seconddielectric material 315 a on a firstdielectric material 315 b, wherein the seconddielectric material 315 a is chemically bonded across atransition region 315 c to the firstdielectric material 315 b. The seconddielectric material 315 a comprises carbon and the first dielectric material does not comprise carbon, wherein “not comprising carbon” as used herein refers to a wt. % of C<3%. -
NMOS transistor 310 includessource 321 and drain 322 regions lateral to the sidewall spacers, and include lightly dopedextensions silicide layer 316 is shown on thegate electrode 311 and thesource 321 and drain 322. - Similarly,
PMOS transistor 320 includes a gate stack including agate electrode 331 on a gate dielectric 332 (which can be the same material asgate dielectric 312 under gate electrode 311) having sidewall spacers on sidewalls of the gate stack, comprising the seconddielectric material 315 a on a firstdielectric material 315 b, wherein the seconddielectric material 315 a is chemically bonded across atransition region 315 c to the firstdielectric material 315 b. The seconddielectric material 315 a comprises carbon and the first dielectric material does not comprise carbon.PMOS transistor 320 includessource 341 and drain 342 regions lateral to the sidewall spacers, and include lightly dopedextensions Silicide layer 316 is shown on thegate electrode 331 and on thesource 341 and drain 342. - The total thickness of the
sidewall spacer 315 a/315 c/315 b at its widest point at its base is generally ≦100 Angstroms, such as 40 to 70 Angstroms thick. For example, in one particular embodiment seconddielectric material 315 a is about 5 to 10 angstroms thick,transition region 315 c is 15 to 25 Angstroms thick, and the firstdielectric material 315 b is 20 to 30 Angstroms thick. -
FIG. 4 shows the composition as a function of thickness for an example surface convertedsidewall spacer 400, including a highly simplified depiction of the chemical bonding provided across the thickness of the surface convertedsidewall spacer 400, according to an example embodiment. The surface convertedsidewall spacer 400 includes a non-constant chemical composition profile across its thickness comprising a firstdielectric material 315 b on the sidewall of a gate stack material and a chemically converted top (outer) surface comprising a seconddielectric material 315 a chemically bonded across atransition region 315 c to the firstdielectric material 315 b. In the embodiment shown the firstdielectric material 315 b comprises silicon nitride (roughly Si3N4), the seconddielectric material 315 a comprises silicon carbide (SiC), and thetransition region 315 c includes a material comprising Si, N and C, where the C content decreases and the N content increases as the distance to the seconddielectric material 315 a/gate stack is reduced. - Disclosed semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, CMOS, BiCMOS and MEMS.
- Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.
Claims (14)
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/427,062 US9496359B2 (en) | 2011-03-28 | 2012-03-22 | Integrated circuit having chemically modified spacer surface |
JP2014502758A JP2014514757A (en) | 2011-03-28 | 2012-03-28 | Integrated circuits having chemically modified spacer surfaces |
PCT/US2012/030977 WO2012135363A2 (en) | 2011-03-28 | 2012-03-28 | Integrated circuit having chemically modified spacer surface |
US13/442,192 US8463054B2 (en) | 2011-08-11 | 2012-04-09 | Hierarchical OCR using decision tree and nonparametric classifier |
BE201200548A BE1020588A5 (en) | 2011-08-11 | 2012-08-13 | METHOD OF RECOGNIZING FORMS, COMPUTER PROGRAM PRODUCT, AND MOBILE TERMINAL. |
US14/878,553 US9620423B2 (en) | 2011-03-28 | 2015-10-08 | Integrated circuit having chemically modified spacer surface |
US15/447,795 US10483261B2 (en) | 2011-03-28 | 2017-03-02 | Integrated circuit having chemically modified spacer surface |
JP2017088445A JP6534163B2 (en) | 2011-03-28 | 2017-04-27 | Integrated circuit having a chemically modified spacer surface |
JP2019079500A JP6916430B2 (en) | 2011-03-28 | 2019-04-18 | Integrated circuit with chemically modified spacer surface |
JP2021017147A JP7157835B2 (en) | 2011-03-28 | 2021-02-05 | Integrated circuit with chemically modified spacer surface |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161468308P | 2011-03-28 | 2011-03-28 | |
US13/427,062 US9496359B2 (en) | 2011-03-28 | 2012-03-22 | Integrated circuit having chemically modified spacer surface |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/442,192 Continuation US8463054B2 (en) | 2011-08-11 | 2012-04-09 | Hierarchical OCR using decision tree and nonparametric classifier |
US14/878,553 Division US9620423B2 (en) | 2011-03-28 | 2015-10-08 | Integrated circuit having chemically modified spacer surface |
Publications (3)
Publication Number | Publication Date |
---|---|
US20130248949A1 US20130248949A1 (en) | 2013-09-26 |
US20160233132A9 true US20160233132A9 (en) | 2016-08-11 |
US9496359B2 US9496359B2 (en) | 2016-11-15 |
Family
ID=49210966
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/427,062 Active 2033-02-13 US9496359B2 (en) | 2011-03-28 | 2012-03-22 | Integrated circuit having chemically modified spacer surface |
US14/878,553 Active US9620423B2 (en) | 2011-03-28 | 2015-10-08 | Integrated circuit having chemically modified spacer surface |
US15/447,795 Active US10483261B2 (en) | 2011-03-28 | 2017-03-02 | Integrated circuit having chemically modified spacer surface |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/878,553 Active US9620423B2 (en) | 2011-03-28 | 2015-10-08 | Integrated circuit having chemically modified spacer surface |
US15/447,795 Active US10483261B2 (en) | 2011-03-28 | 2017-03-02 | Integrated circuit having chemically modified spacer surface |
Country Status (1)
Country | Link |
---|---|
US (3) | US9496359B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9576894B2 (en) * | 2015-06-03 | 2017-02-21 | GlobalFoundries, Inc. | Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8883033B2 (en) * | 2013-03-05 | 2014-11-11 | United Microelectronics Corp. | Method for removing nitride material |
CN105322013B (en) * | 2014-07-17 | 2020-04-07 | 联华电子股份有限公司 | Semiconductor device and method for forming the same |
US9368343B1 (en) | 2015-01-07 | 2016-06-14 | International Business Machines Corporation | Reduced external resistance finFET device |
KR102396111B1 (en) * | 2015-06-18 | 2022-05-10 | 삼성전자주식회사 | Semiconductor devices and methods of manufacturing the same |
US10026837B2 (en) * | 2015-09-03 | 2018-07-17 | Texas Instruments Incorporated | Embedded SiGe process for multi-threshold PMOS transistors |
US10636797B2 (en) * | 2018-04-12 | 2020-04-28 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5149669A (en) * | 1987-03-06 | 1992-09-22 | Seiko Instruments Inc. | Method of forming an isolation region in a semiconductor device |
US6140192A (en) | 1999-06-30 | 2000-10-31 | United Microelectronics Corp. | Method for fabricating semiconductor device |
US6483154B1 (en) * | 2000-10-05 | 2002-11-19 | Advanced Micro Devices, Inc. | Nitrogen oxide plasma treatment for reduced nickel silicide bridging |
EP1598858B1 (en) | 2003-02-28 | 2014-04-09 | Fujitsu Limited | Process for producing etching resistant film, surface cured resist pattern, process for producing surface modified resist pattern, and process for producing semiconductor device |
US7064027B2 (en) | 2003-11-13 | 2006-06-20 | International Business Machines Corporation | Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance |
JP2007157870A (en) | 2005-12-02 | 2007-06-21 | Renesas Technology Corp | Semiconductor device and method of manufacturing same |
US20070275532A1 (en) * | 2006-05-24 | 2007-11-29 | International Business Machines Corporation | Optimized deep source/drain junctions with thin poly gate in a field effect transistor |
KR100800675B1 (en) * | 2006-12-21 | 2008-02-01 | 동부일렉트로닉스 주식회사 | Method for fabricating flash memory device |
DE102008016426B4 (en) * | 2008-03-31 | 2012-04-19 | Globalfoundries Inc. | A method of creating a tensile strain by applying strain memory techniques in close proximity to the gate electrode |
US8482073B2 (en) * | 2010-03-25 | 2013-07-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit including FINFETs and methods for forming the same |
US20120004924A1 (en) * | 2010-06-30 | 2012-01-05 | Mckesson Specialty Arizona Inc. | Method and apparatus for providing improved outcomes of communications intended to improve behaviors of the recipient |
US8329546B2 (en) * | 2010-08-31 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Modified profile gate structure for semiconductor device and methods of forming thereof |
US8664125B2 (en) * | 2011-12-23 | 2014-03-04 | Tokyo Electron Limited | Highly selective spacer etch process with reduced sidewall spacer slimming |
-
2012
- 2012-03-22 US US13/427,062 patent/US9496359B2/en active Active
-
2015
- 2015-10-08 US US14/878,553 patent/US9620423B2/en active Active
-
2017
- 2017-03-02 US US15/447,795 patent/US10483261B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9576894B2 (en) * | 2015-06-03 | 2017-02-21 | GlobalFoundries, Inc. | Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
US9496359B2 (en) | 2016-11-15 |
US9620423B2 (en) | 2017-04-11 |
US10483261B2 (en) | 2019-11-19 |
US20160027884A1 (en) | 2016-01-28 |
US20130248949A1 (en) | 2013-09-26 |
US20170179126A1 (en) | 2017-06-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10483261B2 (en) | Integrated circuit having chemically modified spacer surface | |
US8557659B2 (en) | Spacer structures of a semiconductor device | |
US8202773B2 (en) | Engineered oxygen profile in metal gate electrode and nitrided high-k gate dielectrics structure for high performance PMOS devices | |
US8450834B2 (en) | Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers | |
US8237231B2 (en) | Device with aluminum surface protection | |
US10002878B2 (en) | Complementary SONOS integration into CMOS flow | |
US7696578B2 (en) | Selective CESL structure for CMOS application | |
US20080064176A1 (en) | Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device | |
JP5569173B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
US8802523B2 (en) | CMOS device and fabrication method | |
US8569185B2 (en) | Method of fabricating gate electrode using a treated hard mask | |
US7190033B2 (en) | CMOS device and method of manufacture | |
JP7157835B2 (en) | Integrated circuit with chemically modified spacer surface | |
US7741168B2 (en) | Systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks | |
US7148130B2 (en) | Semiconductor device and method of manufacturing the same | |
US9147613B2 (en) | Method of forming an insulator layer in a semiconductor structure and structures resulting therefrom |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIRKPATRICK, BRIAN K.;JAIN, AMITABH;REEL/FRAME:027924/0964 Effective date: 20120321 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |