US20110066798A1 - Semiconductor device having calibration circuit that adjusts an impedance of output buffer and data processing system including the same - Google Patents
Semiconductor device having calibration circuit that adjusts an impedance of output buffer and data processing system including the same Download PDFInfo
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- US20110066798A1 US20110066798A1 US12/923,261 US92326110A US2011066798A1 US 20110066798 A1 US20110066798 A1 US 20110066798A1 US 92326110 A US92326110 A US 92326110A US 2011066798 A1 US2011066798 A1 US 2011066798A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40626—Temperature related aspects of refresh operations
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4061—Calibration or ate or cycle tuning
Definitions
- the present invention relates to a semiconductor device and a data processing system including the same, and more particularly relates to a semiconductor device including a calibration circuit that adjusts an impedance of an output buffer and to a data processing system including the semiconductor device.
- a semiconductor device such as a DRAM (Dynamic Random Access Memory) sometimes includes a calibration circuit that adjusts an impedance of an output buffer (see Japanese Patent Application Laid-open No. 2008-48361).
- the calibration circuit is activated by a calibration command issued from a controller.
- the calibration command includes a long calibration command (ZQCL) and a short calibration command (ZQCS).
- the long calibration command (ZQCL) is issued at a time of returning from an initialization period after power activation or from a self-refresh mode, and its calibration period is set relatively long.
- the short calibration command (ZQCS) is periodically issued during a normal operation, and its calibration period is set relatively short.
- the short calibration command (ZQCS) is periodically issued from a controller, a timer circuit or the like has to be provided at a controller side, and a control at the controller side becomes complex.
- a semiconductor device that automatically performs a calibration has been desired instead of semiconductor devices that issue the short calibration command (ZQCS) from a controller side.
- ZQCS short calibration command
- a calibration operation needs to be periodically performed, and thus a read operation and a write operation cannot be performed during the calibration operation. Accordingly, when automatically performing a calibration operation at a semiconductor device side, designing needs to be made taking these factors into consideration.
- a semiconductor device comprising: an output buffer; a calibration circuit that adjusts an impedance of the output buffer; and a start-up circuit that activates the calibration circuit when an auto refresh command has been issued for a predetermined number of times.
- a data processing system comprising: the semiconductor device described above; and a controller that issues the auto refresh command to the semiconductor device.
- a calibration can be performed automatically at a semiconductor device side without issuing a calibration command from a controller side. Furthermore, because a calibration operation is performed in response to a fact that an auto refresh command has been issued for a predetermined number of times, a periodical calibration operation can be secured, and a read operation or a write operation is not requested from the controller during a calibration operation.
- FIG. 1 is a block diagram showing an overall configuration of a semiconductor device according to a first embodiment of the present invention
- FIG. 2 is a circuit diagram of the calibration start-up circuit
- FIG. 3 is a circuit diagram of the output buffer
- FIG. 4 is a circuit diagram of the calibration circuit
- FIG. 5 is a circuit diagram of the pull-up circuit
- FIG. 6 is a circuit diagram of the pull-down circuit
- FIG. 7 is an operation waveform diagram for explaining an operation of the semiconductor device according to the first embodiment
- FIG. 8 is another operation waveform diagram for explaining an operation of the semiconductor device according to the first embodiment.
- FIG. 9 is a circuit diagram of the comparator that activates the internal calibration command each time when the refresh counter makes four cycles;
- FIG. 10 is a diagram of the comparator constituted as the AND gate
- FIG. 11 is a block diagram showing an overall configuration of a semiconductor device according to the second embodiment.
- FIG. 12 is a circuit diagram of an example of the comparator
- FIG. 13 is a circuit diagram showing another example of the comparator
- FIGS. 14A and 14B are a block diagram of examples of the configuration of the switching circuit
- FIG. 15 is a block diagram showing an overall configuration of a semiconductor device according to the third embodiment.
- FIG. 16 is a circuit diagram of the calibration circuit
- FIG. 17 is a block diagram showing an overall configuration of a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 18 is a circuit diagram of the calibration start-up circuit according to the fourth embodiment.
- FIG. 19 is an operation waveform diagram for explaining an operation of the semiconductor device according to the fourth embodiment.
- FIG. 20 is a block diagram of a data processing system including the semiconductor device.
- FIG. 21 is a circuit diagram of the modification of the calibration start-up circuit according.
- FIG. 1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a first embodiment of the present invention.
- the semiconductor device 10 is a DDR SDRAM, and includes clock terminals 11 a and lib, command terminals 12 a to 12 e , an address terminal 13 , a data input/output terminal DQ, and a calibration terminal ZQ, as external terminals.
- the semiconductor device 10 a also includes a power source terminal, a data strobe terminal or the like, these terminals are not shown in FIG. 1 .
- the clock terminals 11 a and 11 b are supplied with external clock signals CK and /CK, respectively, and supply the supplied external clock signals CK and /CK to a clock input circuit 21 .
- a signal having “/” attached to the head of a signal name means an inverted signal of a corresponding signal or a low active signal. Therefore, the external clock signals CK and /CK are mutually complementary signals.
- An output of the clock input circuit 21 is supplied to an internal-clock generating circuit 22 .
- the internal-clock generating circuit 22 generates an internal clock signal ICLK.
- the internal clock signal ICLK is supplied to various internal circuits that include a calibration circuit 100 , and is used as a synchronization signal.
- the command terminals 12 a to 12 e are supplied with a row-address strobe signal /RAS, a column-address strobe signal /CAS, a write enable signal /WE, a chip select signal /CS, and an on-die termination signal ODT, respectively.
- These command signals CMD are supplied to a command input circuit 31 .
- These command signals CMD input to the command input circuit 31 are supplied to a command decoder 32 .
- the command decoder 32 generates various internal commands ICMD by holding, decoding, and counting command signals.
- an internal long-calibration command IZQCL is supplied to at least the calibration circuit 100
- an internal refresh command REF 1 is supplied to at least a calibration start-up circuit 200 .
- the internal long-calibration command IZQCL is an internal command activated when along calibration command ZQCL is issued via the command terminals 12 a to 12 e .
- the internal refresh command REF 1 is an internal command activated when an auto refresh command AR is issued via the command terminals 12 a to 12 e .
- Other internal commands ICMD are supplied to a row control circuit 51 , a column control circuit 52 , and a mode register 53 .
- the long calibration command ZQCL is issued at a time of returning from an initialization period after power activation or from a self-refresh mode. For example, 512 tCK is allocated for a calibration period (tCK is one clock cycle of an external clock signal CK). In the first embodiment, a short calibration command (ZQCS) does not need to be issued from outside.
- the auto refresh command AR is issued from outside at a predetermined frequency.
- a count value of a refresh counter 54 is incremented each time when the auto refresh command AR is issued.
- the refresh counter 54 shows a row address (a refresh address REFA) to be refreshed.
- the address terminal 13 is supplied with address signals ADD, and supplies the supplied address signals ADD to an address input circuit 41 .
- An output of the address input circuit 41 is supplied to an address latch circuit 42 .
- Out of address signals ADD latched by the address latch circuit 42 a row address is supplied to the row control circuit 51 , and a column address is supplied to the column control circuit 52 .
- the address signals ADD are supplied to the mode register 53 , thereby updating a content of the mode register 53 .
- An output of the row control circuit 51 is supplied to a row decoder 61 .
- the row decoder 61 selects a word line WL included in a memory cell array 60 .
- plural word lines WL and plural bit lines BL cross each other.
- Memory cells MC are arranged at intersections of these lines (only one word line WL, one bit line BL, and one memory cell MC are shown in FIG. 1 ).
- Bit lines BL are connected to corresponding sense amplifiers SA within a sense circuit 63 .
- An output of the column control circuit 52 is supplied to a column decoder 62 .
- the column decoder 62 selects a sense amplifier SA included in the sense circuit 63 .
- a sense amplifier SA selected by the column decoder 62 is connected to a data input/output circuit 70 .
- the data input/output circuit 70 is connected to the data input/output terminal DQ, and includes an output buffer 71 and an impedance adjusting circuit 72 as shown in FIG. 1 .
- the output buffer 71 outputs read data via the data input/output terminal DQ
- the impedance adjusting circuit adjusts an output impedance of the output buffer 71 .
- the data input/output circuit 70 also includes input buffers. With this arrangement, in a read operation, data read from the memory cell array 60 via the sense circuit 63 and a data input/output circuit 70 is output from the data input/output terminal DQ in a predetermined impedance. On the other hand, in a write operation, write data input to the data input/output terminal DQ is written into the memory cell array 60 via the data input/output circuit 70 and the sense circuit 63 .
- Adjustment of an impedance by the impedance adjusting circuit 72 is designated by an impedance code DRZQ supplied from the calibration circuit 100 .
- the calibration circuit 100 performs a calibration operation by referencing a resistance value of an external resistor Re connected to the calibration terminal ZQ, thereby generating the impedance code DRZQ.
- An calibration operation of the calibration circuit 100 is started in response to an internal calibration command IZQ or the internal long-calibration command IZQCL supplied from the calibration start-up circuit 200 .
- the calibration circuit 100 is described in detail later.
- the calibration start-up circuit 200 generates the internal calibration command IZQ, and includes an address register 210 and a comparator 220 as shown in FIG. 1 .
- the internal calibration command IZQ is used to perform a short calibration.
- the calibration start-up circuit 200 also generates an internal refresh command REF 2 .
- the calibration start-up circuit 200 is also described in detail later.
- the internal refresh command REF 2 is supplied to the refresh counter 54 and the row control circuit 51 .
- a count value of the refresh counter 54 is incremented in response to the internal refresh command REF 2 .
- This count value shows a row address (the refresh address REFA) to be refreshed.
- the refresh address REFA is supplied to the row control circuit 51 together with the internal refresh command REF 2 .
- the row control circuit 51 activates a word line shown by the refresh address REFA when the internal refresh command REF 2 is activated. Accordingly, all memory cells MC connected to this word line are refreshed.
- the overall configuration of the semiconductor device 10 according to the first embodiment is as described above.
- FIG. 2 is a circuit diagram of the calibration start-up circuit 200 .
- the calibration start-up circuit 200 includes the address register 210 that stores a row address, and the comparator 220 that compares a row address SETA held in the address register 210 with the refresh address REFA.
- the address register 210 stores an arbitrary row address SETA, and the number of bits of this address matches that of bits of the refresh address REFA in the first embodiment.
- a value of the row address SETA is not particularly limited.
- a circuit configuration of the address register 210 is not particularly limited, and a fuse circuit and a latch circuit can be used for this circuit.
- the comparator 220 compares these addresses and activates a hit signal HIT 1 at a high level when both addresses match.
- a hit signal HIT is supplied to a one-shot pulse generating circuit 230 that is constituted by a NAND gate 231 and a delay circuit 232 . Accordingly, when the hit signal HIT 1 changes to a high level, a set pulse SET as an output of the one-shot pulse generating circuit 230 is temporarily activated at a low level.
- the set pulse SET is supplied to a set input end S of an SR latch circuit 240 .
- the SR latch circuit 240 has a configuration having NAND gates 241 and 242 connected in cascade. An input end at a NAND gate 241 is the set input end S, and an input end at a NAND gate 242 is a reset input end R. A hit signal HIT 2 as an output of the SR latch circuit 240 is supplied to one input end (an inverted input end) of an AND gate 251 , and is also input to one input end of an AND gate 252 .
- the internal refresh command REF 1 is supplied to the other input end of the AND gates 251 and 252 , respectively. Accordingly, the internal refresh command REF 2 as an output of the AND gate 251 is activated linked to the internal refresh command REF 1 in case the SR latch circuit 240 is reset. On the other hand, in case the SR latch circuit 240 is set, the internal refresh command REF 2 is not activated even when the internal refresh command REF 1 is activated. On the other hand, the internal calibration command IZQ as an output of the AND gate 252 is activated linked to the internal refresh command REF 1 in case the SR latch circuit 240 is set. On the other hand, in case the SR latch circuit 240 is reset, the internal calibration command IZQ is not activated even when the internal refresh command REF 1 is activated.
- the internal calibration command IZQ is input to the reset input end R of the SR latch circuit 240 via an inverter 253 . Accordingly, the SR latch circuit 240 returns to a reset state when the internal calibration command IZQ is activated.
- the calibration start-up circuit 200 outputs the internal refresh command REF 1 directly as the internal refresh command REF 2 when the refresh address REFA does not match the row address SETA.
- the internal calibration command IZQ is not activated.
- the internal calibration command IZQ is activated in response to the internal refresh command REF 1 when the refresh address REFA matches the row address SETA.
- the internal refresh command REF 2 is not activated. That is, the internal refresh command REF 1 is converted to the internal calibration command IZQ each time when the refresh counter 54 makes one cycle.
- the internal refresh command REF 2 generated by the calibration start-up circuit 200 is supplied to the refresh counter 54 shown in FIG. 1 in this way. Consequently, a count value of the refresh counter 54 is incremented each time when the auto refresh command AR is issued except when the refresh address REFA matches the row address SETA. On the other hand, even when the auto refresh command AR is issued, an increment of a count value of the refresh counter 54 is suspended when the refresh address REFA matches the row address SETA.
- the internal calibration command IZQ generated by the calibration start-up circuit 200 is supplied to the calibration circuit 100 shown in FIG. 1 .
- the calibration circuit 100 adjusts an output impedance of the output buffer by updating the impedance code DRZQ supplied to the impedance adjusting circuit 72 .
- the impedance code DRZQ is updated by a calibration operation in response to activation of the internal calibration command IZQ or the internal long-calibration command IZQCL.
- FIG. 3 is a circuit diagram of the output buffer 71 .
- the output buffer 71 includes plural (five in this embodiment) P-channel MOS transistors (output transistors) 311 to 315 connected in parallel between a power source terminal VDDQ and the data input/output terminal DQ, plural (five in this embodiment) N-channel MOS transistors (output transistors) 321 to 325 connected in parallel between a power source terminal VSSQ and the data input/output terminal DQ, and two resistors R connected in series between the output transistors 311 to 315 and the output transistors 321 to 325 . A contact point of the two resistors R is connected to the data input/output terminal DQ.
- the output buffer 71 apart including the P-channel MOS transistors 311 to 315 and the resistor R constitute a pull-up circuit PU, and a part including the N-channel MOS transistors 321 to 325 and the resistor R constitutes a pull-down circuit PD.
- Corresponding bits of an ON signal on P are supplied to gates of the output transistors 311 to 315 , respectively.
- Corresponding bits of an ON signal on N are supplied to gates of the output transistors 321 to 325 , respectively. Accordingly, ten output transistors included in the output buffer 71 are individually ON/OFF controlled.
- the pull-up circuit PU and the pull-down circuit PD are designed to become in a predetermined impedance (120 ⁇ , for example) in a conduction state.
- a predetermined impedance 120 ⁇ , for example
- an ON resistance of an output transistor varies depending on a manufacturing condition and changes depending on an environmental temperature and a power source voltage at an operation time
- a desired impedance is not necessarily obtained. Therefore, to set an actual impedance at a designed value, the number of output transistors to be turned ON needs to be adjusted.
- a parallel circuit that is constituted by plural output transistors is used.
- W/L ratios (a gate width/a gate length ratio) of plural output transistors constituting the pull-up circuit PU and the pull-down circuit PD are mutually differentiated.
- a weight of a power of two is attached to the W/L ratios. That is, when a W/L ratio of the output transistor 311 is “1WLp”, it is particularly preferable to set W/L ratios of the output transistors 312 to 315 at “2WLp”, “4WLp”, “8WLp”, and “16WLp”, respectively.
- W/L ratio of the output transistor 321 is “1WLn”
- W/L ratios of the output transistors 322 are set at “2WLn”, “4WLn”, “8WLn”, and “16WLn”, respectively.
- a diffusion layer and a high resistance wiring using tungsten (W), titanium nitride (TiN) or the like can be used for the resistor R.
- FIG. 4 is a circuit diagram of the calibration circuit 100 .
- the calibration circuit 100 includes pull-up circuits 101 and 102 , a pull-down circuit 103 , a counter 110 that designates an impedance of the pull-up circuits 101 and 102 , a counter 120 that designates an impedance of the pull-down circuit 103 , and a control circuit 130 that controls operations of the counters 110 and 120 .
- FIG. 5 is a circuit diagram of the pull-up circuit 101 .
- the pull-up circuit 101 has substantially the same circuit configuration as that of the pull-up circuit PU included in the output buffer 71 . That is, the pull-up circuit 101 includes five P-channel MOS transistors 411 to 415 connected in parallel to the power source terminal VDDQ, and the resistor R of which one end is connected to drains of these transistors. The other end of the resistor R is connected to the calibration terminal ZQ.
- the transistors 411 to 415 included in the pull-up circuit 101 correspond to the output transistors 311 to 315 shown in FIG. 3 , and these transistors have the same impedance. Therefore, W/L ratios of the transistors 411 to 415 are set at “1WLp”, “2WLp”, “4WLp”, “8WLp”, and “16WLp”, respectively like the W/L ratios of the transistors 311 to 315 . However, so long as the impedances are substantially the same, the transistors 411 to 415 included in the pull-up circuit 101 and the output transistors 311 to 315 shown in FIG. 3 do not need to have exactly the same transistor size, and shrunk transistors can be used.
- the resistor R also corresponds to the resistor R shown in FIG. 3 . Therefore, a resistance value of the resistor R is designed at substantially the same value as that of parallel ON resistors of the transistors 411 to 415 , such as 120 ⁇ .
- Corresponding bits of an impedance code DRZQP are supplied to gates of the transistors 411 to 415 , respectively from the counter 110 , thereby designating an impedance of the pull-up circuit 101 .
- the pull-up circuit 102 also has the same circuit configuration as that of the pull-up circuit 101 shown in FIG. 5 except that the other end of the resistor R is connected to a contact point A. Therefore, corresponding bits of the impedance code DRZQP are supplied to gates of five transistors, respectively included in the pull-up circuit 102 .
- FIG. 6 is a circuit diagram of the pull-down circuit 103 .
- the pull-down circuit 103 has substantially the same circuit configuration as that of the pull-down circuit PD included in the output buffer 71 . That is, the pull-down circuit 103 includes five N-channel MOS transistors 421 to 425 connected in parallel to the power source terminal VSSQ, and the resistor R of which one end is connected to drains of these transistors.
- the transistors 421 to 425 included in the pull-down circuit 103 correspond to the transistors 321 to 325 shown in FIG. 3 , and have the same impedance.
- the pull-down circuit 103 is similar to the pull-up circuit 101 in this point.
- the resistor R also corresponds to the resistor R shown in FIG. 3 . Therefore, a resistance value of this resistor R is designed at substantially the same value as that of parallel ON resistors of the transistors 421 to 425 , such as 120 ⁇ .
- Corresponding bits of an impedance code DRZQN are supplied to gates of the transistors 421 to 425 , respectively from the counter 120 , thereby designating an impedance of the pull-down circuit 103 .
- the pull-up circuits 101 and 102 have substantially the same circuit configurations as that of the pull-up circuit PU included in the output buffer 71
- the pull-down circuit 103 has substantially the same circuit configuration as that of the pull-down circuit PD included in the output buffer 71 . Therefore, impedances of the pull-up circuits 101 and 102 and the pull-down circuit 103 are adjusted at 2400, for example.
- the pull-up circuit 102 and the pull-down circuit 103 constitute a replica buffer RepB having substantially the same circuit configuration as that of the output buffer 71 .
- “substantially the same” means that even when transistors included in the replica buffer RepB are shrunk, these transistors are regarded the same.
- the contact point A as an output end of the replica buffer RepB is connected to a non-inverting input terminal (+) of the comparator 121 as shown in FIG. 4 .
- the counter 110 counts up or counts down when a control signal ACT 1 is activated.
- the counter 110 counts up synchronously with the control signal ACT 1 when a comparison signal COMP 1 as an output of a comparator 111 is at a high level, and counts down synchronously with the control signal ACT 1 when the comparison signal COMP 1 is at a low level.
- a non-inverting input terminal (+) of the comparator 111 is connected to the calibration terminal ZQ, and an inverting input terminal ( ⁇ ) is connected to an intermediate point of resistors 141 and 142 connected between a power source potential (VDD) and a ground potential (GND).
- VDD power source potential
- GND ground potential
- the comparator 111 compares a potential of the calibration terminal ZQ with an intermediate voltage (VDD/2).
- the comparator 111 sets the comparison signal COMP 1 as an output of comparison at a high level when the potential of the calibration terminal ZQ is higher, and sets the comparison signal COMP 1 at a low level when the intermediate voltage (VDD/
- the counter 120 counts up or counts down when a control signal ACT 2 is activated.
- the counter 120 counts up synchronously with the control signal ACT 2 when a comparison signal COMP 2 as an output of the comparator 121 is at a high level, and counts down synchronously with the control signal ACT 2 when the comparison signal COMP 2 is at a low level.
- a non-inverting input terminal (+) of the comparator 121 is connected to the connection point A as an output end of a replica buffer, and an inverting input terminal ( ⁇ ) is connected to an intermediate point of the resistors 141 and 142 .
- the comparator 121 compares an output potential of the replica buffer with the intermediate voltage (VDD/2).
- the comparator 121 sets the comparison signal COMP 2 as an output of comparison at a high level when the output potential of the replica buffer is higher, and sets the comparison signal COMP 2 at a low level when the intermediate voltage (VDD/2) is higher.
- the counters 110 and 120 stop counting operations when the control signals ACT 1 and ACT 2 are inactivated, and hold current count values, respectively.
- a count value of the counter 110 is used for the impedance code DRZQP
- a count value of the counter 120 is used for the impedance code DRZQN.
- the impedance code DRZQ as a collective term of these codes is supplied to an impedance adjusting circuit 72 shown in FIG. 1 .
- the control signals ACT 1 and ACT 2 are supplied from the control circuit 130 .
- the control circuit 130 is started by activation of the internal calibration command IZQ or the internal long-calibration command IZQCL, and activates the control signals ACT 1 and ACT 2 synchronously with the internal clock signal ICLK. Specifically, the control circuit 130 counts the internal clock signal ICLK corresponding to 1 ⁇ 2 of a calibration period or continuously activates the control signal ACT 1 until an end signal END 1 is activated, after the internal calibration command IZQ or the internal long-calibration command IZQCL is activated.
- the control circuit 130 counts the internal clock signal ICLK corresponding to 1 ⁇ 2 of a calibration period or continuously activates the control signal ACT 2 until an end signal END 2 is activated, after the control signal ACT 1 is inactivated.
- An activation cycle of the control signals ACT 1 and ACT 2 is set at 2n times (n is a natural number) a clock cycle of the internal clock signal ICLK.
- the end signal END 1 is generated by an end determining circuit 131 , and is activated when the comparison signal COMP 1 as an output of the comparator 111 changes in a predetermined pattern.
- the end signal END 2 is generated by an end determining circuit 132 , and is activated when the comparison signal COMP 2 as an output of the comparator 121 changes in a predetermined pattern.
- the “predetermined pattern” is a change pattern that appears when an impedance of the pull-up circuits 101 and 102 or the pull-down circuit 103 has reached a target value.
- a detailed pattern is that the logic level of the comparison signal COMP 1 or COMP 2 is inverted once or repeatedly, for example.
- an impedance adjustment of the pull-up circuit 101 is performed in a first half period and an impedance adjustment of the pull-down circuit 103 is performed in a latter half period.
- a calibration method is not limited thereto.
- a method that only either one of the pull-up circuit 101 and the pull-down circuit 103 is impedance-adjusted during one calibration period and that a circuit to be calibrated is switched each time when the internal calibration command IZQ is issued. This method is effective when a frequency of the internal clock signal ICLK is high and also when it is difficult to adjust both impedances of the pull-up circuit 101 and the pull-down circuit 103 , during one calibration period in response to the internal calibration command IZQ.
- a circuit configuration and an operation of the calibration circuit 100 are as described above.
- the impedance code DRZQ generated by the calibration circuit 100 in this way is supplied to the impedance adjusting circuit 72 shown in FIG. 1 , thereby causing an impedance of the output buffer 71 to match an impedance of the replica buffer RepB. Therefore, by periodically performing a calibration operation, the impedance of the output buffer 71 can be set closer to a designed value regardless of a temperature change and a voltage variation.
- FIG. 7 is an operation waveform diagram for explaining an operation of the semiconductor device 10 according to the first embodiment.
- the internal calibration command IZQ is activated instead. That is, in this example, the auto refresh command AR at an 8K-th time is handled as the short calibration command ZQCS, and a calibration operation is performed instead of a refresh operation.
- the SR latch circuit 240 is reset in response to the next auto refresh command AR. Accordingly, thereafter, when the auto refresh command AR is issued, the internal refresh command REF 2 is activated as usual.
- FIG. 8 is another operation waveform diagram for explaining an operation of the semiconductor device 10 according to the first embodiment.
- the internal calibration command IZQ is activated and a short calibration operation is performed each time when the refresh counter 54 makes one cycle by issuing the auto refresh command AR 8K times.
- the internal refresh command REF 2 is not activated when the internal calibration command IZQ is generated, and therefore a count value of the refresh counter 54 is not incremented at this time.
- a cycle of issuing the auto refresh command AR is very short of an average 7.8 ⁇ s. As, and an information holding time of the memory cells MC is a minimum guaranteed value. Considering the fact that the information holding time is longer in practice, no actual inconvenience occurs.
- the internal calibration command IZQ is activated each time when the refresh counter 54 makes one cycle, thereby starting a short calibration operation.
- an activation cycle of the internal calibration command IZQ is not limited to this cycle so long the cycle is based on the number of times that the auto refresh command AR is issued. Therefore, the internal calibration command IZQ can be activated each time when the refresh counter 54 makes a 1 ⁇ 2 cycle, or the internal calibration command IZQ can be activated each time when the refresh counter 54 makes four cycles, for example.
- the number of bits of the row address SETA stored in the address register 210 can be set smaller than that of the refresh address REFA by omitting a highest-order bit, for example.
- a gate circuit XNOR that compares each bit of the refresh address REFA with each bit of the row address SETA is provided in the comparator 220 , and a two-bit ripple counter C counting a highest-order bit REFAmax of the refresh address REFA is provided.
- an AND gate 220 a is used which activates the hit signal HIT 1 when an output of the gate circuit XNOR and an output of the ripple counter C all become a high level.
- the address register 210 that stores an arbitrary row address SETA is used in the first embodiment, it is not essential in the present invention.
- the comparator 220 can be configured by an AND gate 220 b that receives each bit of the refresh address REFA, as shown in FIG. 10 .
- FIG. 11 is a block diagram showing an overall configuration of a semiconductor device 10 a according to the second embodiment.
- the semiconductor device 10 a according to the second embodiment is different from the semiconductor device 10 shown in FIG. 1 in that the calibration start-up circuit 200 is replaced by a calibration start-up circuit 500 .
- Other configurations of the semiconductor device 10 a according to the second embodiment are identical to those of the semiconductor device 10 shown in FIG. 1 , and thus like elements are denoted by like reference numerals and explanations thereof will be omitted.
- the calibration start-up circuit 500 includes a comparator 520 and a switching circuit 530 .
- the comparator 520 compares the row address SETA stored in the address register 210 with the refresh address REFA, and is different from the comparator 220 described above in that the comparator 520 can switch a cycle of outputting the hit signal HIT 1 .
- the switching circuit 530 switches the cycle of the comparator 520 .
- FIG. 12 is a circuit diagram of an example of the comparator 520 .
- the comparator 520 includes the gate circuit XNOR that compares each bit of the refresh address REFA with each bit of the row address SETA, an AND gate 520 a that receives each output of the XNOR, and switches SW 1 and SW 2 that validate or invalidate a gate circuit XNORi corresponding to a predetermined bit.
- a control of the switches SW 1 and SW 2 is performed by a selection signal SEL 1 supplied from the switching circuit 530 .
- the switch SW 1 is set ON, and the switch SW 2 is switched to a node a.
- the node a is an output end of the gate circuit XNORi. Accordingly, the AND gate 520 a activates the hit signal HIT 1 when all bits of the refresh address REFA and the row address SETA match together. That is, an activation cycle of the hit signal HIT 1 matches one cycle of the refresh counter 54 .
- the switch SW 1 is set OFF, and the switch SW 2 is switched to a node b.
- the node b is fixed at a high level. Accordingly, a bit corresponding to the gate circuit XNORi becomes a don't-care bit, and the AND gate 520 a activates the hit signal HIT 1 when other bits of the refresh address REFA and the row address SETA match together. That is, an activation cycle of the hit signal HIT 1 matches a 1 ⁇ 2 cycle of the refresh counter 54 .
- an activation cycle of the hit signal HIT 1 that is, a generation cycle of the internal calibration command IZQ, can be set to either one cycle or a 1 ⁇ 2 cycle of the refresh counter 54 .
- FIG. 13 is a circuit diagram showing another example of the comparator 520 .
- the comparator 520 includes the gate circuit XNOR that compares each bit of the refresh address REFA with each bit of the row address SETA, the two-bit ripple counter C that counts a highest-order bit REFAmax of the refresh address REFA, an AND gate 521 that receives each output of the gate circuit XNOR and a lowest-order bit Cmin of the ripple counter C, an AND gate 522 that receives each output of the gate circuit XNOR and all output bits of the ripple counter C, and a selector 523 that selects one of outputs of the AND gates 521 and 522 .
- a control of the selector 523 is performed by a selection signal SEL 2 supplied by the switching circuit 530 .
- the selector 523 activates the hit signal HIT 1 when all bits of the refresh address REFA and the row address SETA match together and also when all outputs of the ripple counter C become a high level. In this case, an activation cycle of the hit signal HIT 1 matches four cycles of the refresh counter 54 .
- the selector 523 activates the hit signal HIT 1 when all bits of the refresh address REFA and the row address SETA match together and also when a lowest-order bit of the ripple counter C becomes a high level. In this case, an activation cycle of the hit signal HIT 1 matches two cycles of the refresh counter 54 .
- an activation cycle of the hit signal HIT 1 that is, a generation cycle of the internal calibration command IZQ, can be set to two cycles or four cycles of the refresh counter 54 .
- the configuration of the switching circuit 530 is not particularly limited, and the switching circuit 530 can be configured such that the selection signals SEL 1 and SEL 2 are fixed at a manufacturing time or such that the selection signals SEL 1 and SEL 2 dynamically change based on an operation environment.
- the switching circuit 530 can be configured by an antifuse circuit as shown in FIG. 14A .
- the switching circuit 530 can be configured by a temperature detecting circuit as shown in FIG. 14B .
- the selection signals SEL 1 and SEL 2 are output such that a generation cycle of the internal calibration command IZQ is shortened when the temperature detecting circuit detects a temperature change of a predetermined value or above. Because a property (a resistance, for example) of an element changes greatly according to the temperature, the frequency of performing a calibration operation needs to be increased when there is a large temperature change.
- FIG. 15 is a block diagram showing an overall configuration of a semiconductor device 10 b according to the third embodiment.
- the semiconductor device 10 b according to the third embodiment is different from the semiconductor device 10 a shown in FIG. 11 in that the calibration circuit 100 is replaced by a calibration circuit 600 .
- Other configurations of the semiconductor device 10 b according to the third embodiment are identical to those of the semiconductor device 10 a shown in FIG. 11 , and thus like elements are denoted by like reference numerals and explanations thereof will be omitted.
- the calibration circuit 600 includes a timer circuit 610 .
- the timer circuit 610 forcibly terminates a short calibration operation started by the internal calibration command IZQ.
- FIG. 16 is a circuit diagram of the calibration circuit 600 .
- the timer circuit 610 is included in the control circuit 130 , and starts time counting in response to activation of the internal calibration command IZQ.
- the timer circuit 610 forcibly causes a calibration operation to be finished when a predetermined time has passed after the internal calibration command IZQ is activated.
- a counting time by the timer circuit 610 is set equal to or shorter than a time (for example, 110 ns) allocated to a refresh operation.
- the control circuit 130 forcibly finishes a calibration operation when the timer circuit 610 finishes time counting, even before a calibration period is over based on a count of the internal clock signal ICLK, after generation of the control signals ACT 1 and ACT 2 is started in response to the internal calibration command IZQ. Consequently, because the calibration operation can be finished within a time range allocated to a refresh operation, the control circuit 130 can receive the next command immediately after the time range allocated to the refresh operation has passed.
- FIG. 17 is a block diagram showing an overall configuration of a semiconductor device 10 c according to a fourth embodiment of the present invention.
- the semiconductor device 10 c according to the fourth embodiment is different from the semiconductor device 10 shown in FIG. 1 in that the calibration start-up circuit 200 is replaced by a calibration start-up circuit 602 .
- Other configurations of the semiconductor device 10 c according to the fourth embodiment are identical to those of the semiconductor device 10 shown in FIG. 1 , and thus like elements are denoted by like reference numerals and explanations thereof will be omitted.
- the calibration start-up circuit 602 includes a temperature detecting circuit 222 in addition to the address register 210 and the comparator 220 .
- the temperature detecting circuit 222 measures a temperature at the inside of the semiconductor device 10 c , and shows temperature information of this measurement by signals T 0 and T 1 . Details thereof will be described later.
- FIG. 18 is a circuit diagram of the calibration start-up circuit 602 according to the fourth embodiment.
- the calibration start-up circuit 602 has a configuration having a temperature detection function added to the calibration start-up circuit 200 according to the first embodiment.
- a temperature detecting circuit 224 shows a temperature at the inside of the semiconductor device 10 c by two-bit signals of the signals T 0 and T 1 .
- the temperature detecting circuit 224 detects a temperature change by using temperature dependency of a voltage of a PN junction of transistors Q 1 and Q 2 .
- operational amplifiers 270 and 272 generate a potential VF having no temperature dependency from a base-emitter voltage of the transistors Q 1 and Q 2 of the same size, and resistively divide the potential VF to generate potentials V 1 and V 2 (V 1 >V 2 ).
- an inter-base-emitter voltage VBE of the transistor Q 2 becomes lower when a temperature becomes higher. Therefore, a temperature change can be detected by comparing the potentials V 1 and V 2 with the voltage VBE.
- VBE inter-base-emitter voltage
- (T 1 , T 0 ) (L, L).
- (T 1 , T 0 ) (H, L).
- (T 1 , T 0 ) (H, H).
- the temperature detecting circuit 224 can take various configurations, and the configuration shown in FIG. 18 is only an example.
- the internal refresh command REF 1 periodically becomes highly active in response to a periodical input of the auto refresh command AR.
- the internal refresh command REF 1 is input to the AND gate 251 .
- the internal refresh command REF 1 directly passes through the AND gate 251 , and becomes the internal refresh command REF 2 . Therefore, a refresh operation is performed each time when the internal refresh command REF 1 becomes highly active.
- the internal calibration command IZQ is issued under a condition that there is a temperature change. That is, in the fourth embodiment, even when the refresh address REFA matches the row address SETA, a calibration is not performed when there is no temperature change since the addresses have matched last time. A refresh operation is performed when there is no temperature change.
- the SR latch 240 is not set, a signal IZQEN becomes a low level, and issuance of the internal calibration command IZQ is blocked. According to this control method, a calibration is omitted when a temperature change does not occur, that is, when a calibration is not really necessary. Therefore, power consumption of the semiconductor device 10 c can be reduced.
- the internal calibration command IZQ When there is a temperature change, the internal calibration command IZQ is issued.
- the number of times that the internal calibration command IZQ is issued depends on the scale of a temperature change. In the fourth embodiment, when the scale of a temperature change is equal to or smaller than a predetermined value, the internal calibration command IZQ is issued twice. When the scale of a temperature change is larger than the predetermined value, the internal calibration command IZQ is issued four times. According to this control method, the number of calibration times can be flexibly adjusted according to the necessity of a calibration.
- the internal long-calibration command IZQCL and the hit signal HIT as an output of the one-shot pulse generating circuit 230 are input to an OR gate 238 of two inputs.
- the hit signal HIT is a one-shot pulse that becomes highly active when the refresh address REFA matches the row address SETA.
- latch circuits 224 , 226 , 228 , 233 , 234 , and 236 latch a level of an input node D, respectively.
- the signals T 1 and T 0 as temperature information are input to the input nodes D of the latch circuits 224 and 226 .
- the signals T 1 and T 0 are latched by the latch circuits 224 and 226 .
- the signal TMON becomes highly active again, these latched signals are shifted to the latch circuits 233 and 234 .
- the signal TMON is activated by the internal long-calibration command IZQCL or the hit signal HIT.
- the latch circuit 228 latches a high-level signal (a fixed signal) by activation of the internal long-calibration command IZQCL or the hit signal HIT.
- the high-level signal is shifted to the latch circuit 236 by the next activation of the signal TMON.
- the XOR gate 242 compares a signal TB 1 signal output from an output node Q of the latch circuit 233 with a signal TN 1 output from the output node Q of the latch circuit 224 , and outputs a signal D 1 .
- the XOR gate 244 compares a signal TB 0 output from the output node Q of the latch circuit 234 with a signal TN 0 output from the output node Q of the latch circuit 226 , and outputs a signal D 2 . That is, the signal D 1 becomes a high level when there is a change between the signal TB 1 as past temperature information and the signal TN 1 as subsequent temperature information. Similarly, the signal D 2 becomes a high level when there is a change between the signals TB 0 and TN 0 . Accordingly, the temperature change is specified by the signals D 1 and D 2 .
- the signals D 1 and D 2 are input to an OR gate 246 .
- the output of the OR gate 246 is input to an AND gate 248 of three inputs. Remaining two inputs of the AND gate are the signal TMON and a signal GRDB as an output of the latch circuit 236 .
- the hit signal HIT becomes highly active, all the three inputs of the AND gate become a high level, and the one-shot pulse circuit 252 generates a low-level one-shot pulse, and the SR latch circuit 240 is set.
- the signal IZQEN as an output of the SR latch circuit 240 becomes highly active.
- the latch circuit 236 is reset when the internal long-calibration command IZQCL becomes highly active. Therefore the SR latch circuit 240 is not set.
- the internal calibration command IZQ is issued instead of the internal refresh command REF 2 , and a calibration is performed.
- an output of the AND gate 248 becomes a low level. Therefore, the signal IZQEN becomes a low level, and the internal refresh command REF 2 is issued.
- the internal long-calibration command IZQCL is highly active, the signal IZQEN becomes a low level and the internal calibration command IZQ is not issued because the signal GRDB as an output of the latch circuit 236 becomes a low level although the signals T 1 and T 0 are latched.
- the calibration circuit 100 is directly activated by the internal long-calibration command IZQCL (see FIG. 17 ). By latching the signals T 0 and T 1 when the command IZQCL is active, temperature information when the command IZQCL is highly active is updated. Accordingly, unnecessary calibrations can be prevented when there is no temperature change after the command IZQCL.
- the signals D 1 and D 2 are also input to a decoder 256 .
- the decoder 256 activates S 1 when both the signals D 1 and D 2 are at a high level, and activates S 0 when one of the signals D 1 and D 2 is at a high level.
- S 1 and S 0 are input to a selector 258 .
- a counter circuit 260 When the signal IZQEN is activated at a high level, a counter circuit 260 is reset via a one-shot pulse generating circuit 254 . Thereafter, the counter circuit 260 updates a count value each time when the internal calibration command IZQ is activated. The count value is supplied to the selector circuit 258 as two-bit signals (00 to 11) of C 0 and C 1 . In case S 1 is at a high level, the selector circuit 258 activates a one-shot pulse circuit 262 when a count value reaches “00” after counting up from 00. At this time, the SR latch circuit 240 is reset, and the signal IZQEN becomes a low level. Thereafter, the internal refresh command REF 2 is issued instead of the internal calibration command IZQ.
- the selector circuit 258 activates the one-shot pulse circuit 262 when a count value reaches “10” after counting up from 00.
- the internal calibration command IZQ is issued four times.
- the internal calibration command IZQ is issued twice.
- FIG. 19 is an operation waveform diagram for explaining an operation of the semiconductor device 10 c according to the fourth embodiment.
- the power ON signal PON is activated by one shot at a time t 0
- the internal long-calibration command IZQCL is activated by one shot at a time t 1 .
- the latch circuits 224 and 226 latch the signals T 0 and T 1 .
- the latched signals T 0 and T 1 are output from the latch circuits 224 and 226 as the signals TN 1 and TN 0 .
- the latch circuit 228 latches a fixed high-level signal, and outputs the signal from a Q terminal to the latch circuit 236 .
- the internal refresh command REF 1 periodically becomes highly active by the auto refresh command AR.
- the refresh address REFA is sequentially designated while being linked to this periodical highly active state.
- the signal TMON becomes highly active.
- the latch circuits 224 , 226 , 228 , 233 , 234 , and 236 latch data, respectively.
- the signals TN 1 and TN 0 latched and output by the latch circuits 224 and 226 at the time t 1 are shifted to the latch circuits 233 and 234 .
- the latch circuits 224 and 226 latch the signals T 0 and T 1 showing a temperature at the time t 2 .
- the latch circuit 236 latches a fixed high-level signal, and outputs the signal GRDB at a high level from an output node Q. Because there is no temperature change during a period from the time t 1 to the time t 2 , the signals D 1 and D 2 remain at a low level. Therefore, an output of the AND gate 248 remains at a low level, and the SR latch 240 is not set. Because the signal IZQEN becomes inactive, the internal calibration command IZQ is not issued, and the internal refresh command REF 2 is issued. That is, a calibration is not performed although the refresh address REFA matches the row address SETA.
- the refresh address REFA matches the row address SETA again.
- the signal T 1 changes from H to L
- the signal T 0 changes from H to L. Because both the signals T 0 and T 1 change, it is determined that there is a large temperature change.
- the signal TMON becomes highly active based on a match of addresses, and new temperature information (T 1 : L, T 0 : L) is latched by the latch circuits 224 and 226 .
- the latch circuits 233 and 234 latch temperature information (T 1 : H, T 1 : H) at the time t 2 . Because both the signals T 1 and T 0 change, the signals D 1 and D 2 become a high level.
- the one-shot pulse generating circuit 254 resets the counter circuit 260 .
- the decoder 256 sets S 1 highly active. Because S 1 is activated, the selector 258 does not reset the SR latch circuit 240 until when a count value output by the counter circuit 260 reaches “00”. Therefore, the internal calibration command IZQ is thereafter kept to be issued while being linked to the refresh command REF 1 .
- the counter circuit 260 counts up each time when the command IZQ is issued.
- the SR latch circuit 240 When a count value becomes “00”, the SR latch circuit 240 is reset, and thereafter the refresh command REF 2 is kept to be issued synchronized with the refresh command REF 1 . That is, the internal calibration command IZQ is issued four times, and thereafter the refresh command REF 2 is kept to be issued.
- the refresh address REFA matches the row address SETA again.
- the signal T 1 changes from L to H, but the signal T 0 does not change. Although there is a temperature change, this change is small.
- the latch circuits 224 and 226 latch new temperature information (T 1 : H, T 0 : L), and the latch circuits 233 and 234 latch temperature information (T 1 : H, T 1 : H) of the time t 3 . Because the signal T 1 only changes, the signal D 1 only becomes a high level.
- the signal IZQEN is activated, the internal calibration command IZQ is issued, and the counter circuit 260 is reset. Because only the signal D 1 is at a high level, the decoder 256 sets S 0 highly active. Because S 0 is activated, the selector 258 does not reset the SR latch circuit 240 until when a count value output by the counter circuit 260 reaches “10”. Accordingly, thereafter, the internal calibration command IZQ is kept to be issued synchronized with the refresh command REF 1 . When a count value becomes “10”, the SR latch circuit 240 is reset, and thereafter the refresh command REF 2 is kept to be issued synchronized with the refresh command REF 1 . As a result, the internal calibration command IZQ is issued twice.
- a calibration is skipped when there is no temperature change, that is, when a calibration is not really necessary. Power consumption can be reduced by omitting unnecessary calibrations.
- a control is performed such that a calibration is performed for a necessary number of times when the calibration is particularly necessary. In this manner, an effective calibration can be performed.
- FIG. 20 is a block diagram of a data processing system including the semiconductor device 10 ( 10 a , 10 b , 10 c ).
- the data processing system shown in FIG. 20 is configured by the semiconductor device 10 ( 10 a , 10 b , 10 c ) and a controller 700 , and both are connected to each other by a command bus 701 , an address bus 702 , and a data bus 703 .
- the controller 700 inputs the auto refresh command AR to the semiconductor device 10 ( 10 a , 10 b , 10 c ) via the command bus 701 . Consequently, the semiconductor device 10 ( 10 a , 10 b , 10 c ) performs a refresh operation or a short calibration operation.
- the controller 700 does not need to perform a short calibration command (ZQCS). That is, the controller 700 does not need to have a timer circuit to periodically issue the short calibration command (ZQCS).
- the controller 700 can also issue the short calibration command (ZQCS), and the semiconductor device 10 ( 10 a , 10 b , 10 c ) can perform a short calibration operation in response to the short calibration command (ZQCS).
- ZQCS short calibration command
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device and a data processing system including the same, and more particularly relates to a semiconductor device including a calibration circuit that adjusts an impedance of an output buffer and to a data processing system including the semiconductor device.
- 2. Description of Related Art
- A semiconductor device such as a DRAM (Dynamic Random Access Memory) sometimes includes a calibration circuit that adjusts an impedance of an output buffer (see Japanese Patent Application Laid-open No. 2008-48361). The calibration circuit is activated by a calibration command issued from a controller.
- The calibration command includes a long calibration command (ZQCL) and a short calibration command (ZQCS). The long calibration command (ZQCL) is issued at a time of returning from an initialization period after power activation or from a self-refresh mode, and its calibration period is set relatively long. On the other hand, the short calibration command (ZQCS) is periodically issued during a normal operation, and its calibration period is set relatively short.
- As described above, because the short calibration command (ZQCS) is periodically issued from a controller, a timer circuit or the like has to be provided at a controller side, and a control at the controller side becomes complex.
- Further, because an active command and a read command cannot be issued during a calibration operation, utilization efficiency of a command bus is degraded. In addition, while a resistance value of an external resistor connected to a semiconductor device is referred during a calibration operation, when one external resistor is shared by plural semiconductor devices to reduce the number of elements, calibration operation periods of these semiconductor devices need to be shifted from each other, and thus a control becomes complex.
- Therefore, a semiconductor device that automatically performs a calibration has been desired instead of semiconductor devices that issue the short calibration command (ZQCS) from a controller side. However, a calibration operation needs to be periodically performed, and thus a read operation and a write operation cannot be performed during the calibration operation. Accordingly, when automatically performing a calibration operation at a semiconductor device side, designing needs to be made taking these factors into consideration.
- In one embodiment, there is provided a semiconductor device comprising: an output buffer; a calibration circuit that adjusts an impedance of the output buffer; and a start-up circuit that activates the calibration circuit when an auto refresh command has been issued for a predetermined number of times.
- In another embodiment, there is provided a data processing system comprising: the semiconductor device described above; and a controller that issues the auto refresh command to the semiconductor device.
- According to the present invention, a calibration can be performed automatically at a semiconductor device side without issuing a calibration command from a controller side. Furthermore, because a calibration operation is performed in response to a fact that an auto refresh command has been issued for a predetermined number of times, a periodical calibration operation can be secured, and a read operation or a write operation is not requested from the controller during a calibration operation.
- The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a block diagram showing an overall configuration of a semiconductor device according to a first embodiment of the present invention; -
FIG. 2 is a circuit diagram of the calibration start-up circuit; -
FIG. 3 is a circuit diagram of the output buffer; -
FIG. 4 is a circuit diagram of the calibration circuit; -
FIG. 5 is a circuit diagram of the pull-up circuit; -
FIG. 6 is a circuit diagram of the pull-down circuit; -
FIG. 7 is an operation waveform diagram for explaining an operation of the semiconductor device according to the first embodiment; -
FIG. 8 is another operation waveform diagram for explaining an operation of the semiconductor device according to the first embodiment; -
FIG. 9 is a circuit diagram of the comparator that activates the internal calibration command each time when the refresh counter makes four cycles; -
FIG. 10 is a diagram of the comparator constituted as the AND gate; -
FIG. 11 is a block diagram showing an overall configuration of a semiconductor device according to the second embodiment; -
FIG. 12 is a circuit diagram of an example of the comparator; -
FIG. 13 is a circuit diagram showing another example of the comparator; -
FIGS. 14A and 14B are a block diagram of examples of the configuration of the switching circuit; -
FIG. 15 is a block diagram showing an overall configuration of a semiconductor device according to the third embodiment; -
FIG. 16 is a circuit diagram of the calibration circuit; -
FIG. 17 is a block diagram showing an overall configuration of a semiconductor device according to a fourth embodiment of the present invention; -
FIG. 18 is a circuit diagram of the calibration start-up circuit according to the fourth embodiment; -
FIG. 19 is an operation waveform diagram for explaining an operation of the semiconductor device according to the fourth embodiment; -
FIG. 20 is a block diagram of a data processing system including the semiconductor device; and -
FIG. 21 is a circuit diagram of the modification of the calibration start-up circuit according. - Preferred embodiments of the present invention will be explained below in detail with reference to the accompanying drawings.
-
FIG. 1 is a block diagram showing an overall configuration of asemiconductor device 10 according to a first embodiment of the present invention. - The
semiconductor device 10 according to the first embodiment is a DDR SDRAM, and includesclock terminals 11 a and lib,command terminals 12 a to 12 e, anaddress terminal 13, a data input/output terminal DQ, and a calibration terminal ZQ, as external terminals. Although thesemiconductor device 10 a also includes a power source terminal, a data strobe terminal or the like, these terminals are not shown inFIG. 1 . - The
clock terminals clock input circuit 21. In the present specification, a signal having “/” attached to the head of a signal name means an inverted signal of a corresponding signal or a low active signal. Therefore, the external clock signals CK and /CK are mutually complementary signals. An output of theclock input circuit 21 is supplied to an internal-clock generating circuit 22. The internal-clock generatingcircuit 22 generates an internal clock signal ICLK. The internal clock signal ICLK is supplied to various internal circuits that include acalibration circuit 100, and is used as a synchronization signal. - The
command terminals 12 a to 12 e are supplied with a row-address strobe signal /RAS, a column-address strobe signal /CAS, a write enable signal /WE, a chip select signal /CS, and an on-die termination signal ODT, respectively. These command signals CMD are supplied to acommand input circuit 31. These command signals CMD input to thecommand input circuit 31 are supplied to acommand decoder 32. Thecommand decoder 32 generates various internal commands ICMD by holding, decoding, and counting command signals. - As shown in
FIG. 1 , among the internal commands ICMD, an internal long-calibration command IZQCL is supplied to at least thecalibration circuit 100, and an internal refresh command REF1 is supplied to at least a calibration start-up circuit 200. The internal long-calibration command IZQCL is an internal command activated when along calibration command ZQCL is issued via thecommand terminals 12 a to 12 e. The internal refresh command REF1 is an internal command activated when an auto refresh command AR is issued via thecommand terminals 12 a to 12 e. Other internal commands ICMD are supplied to arow control circuit 51, acolumn control circuit 52, and amode register 53. - The long calibration command ZQCL is issued at a time of returning from an initialization period after power activation or from a self-refresh mode. For example, 512 tCK is allocated for a calibration period (tCK is one clock cycle of an external clock signal CK). In the first embodiment, a short calibration command (ZQCS) does not need to be issued from outside.
- Meanwhile, the auto refresh command AR is issued from outside at a predetermined frequency. In principle, a count value of a
refresh counter 54 is incremented each time when the auto refresh command AR is issued. Therefresh counter 54 shows a row address (a refresh address REFA) to be refreshed. The auto refresh command AR is cyclically issued such that a count value makes one cycle within a predetermined period (64 ms according to the specification set for the first embodiment). For example, the auto refresh command AR is issued at a frequency of about 7.8 μs (=64 ms/8196) on average when row addresses are present by 8K (=8196). - The
address terminal 13 is supplied with address signals ADD, and supplies the supplied address signals ADD to anaddress input circuit 41. An output of theaddress input circuit 41 is supplied to anaddress latch circuit 42. Out of address signals ADD latched by theaddress latch circuit 42, a row address is supplied to therow control circuit 51, and a column address is supplied to thecolumn control circuit 52. When entered in a mode register set, the address signals ADD are supplied to themode register 53, thereby updating a content of themode register 53. - An output of the
row control circuit 51 is supplied to arow decoder 61. Therow decoder 61 selects a word line WL included in amemory cell array 60. In thememory cell array 60, plural word lines WL and plural bit lines BL cross each other. Memory cells MC are arranged at intersections of these lines (only one word line WL, one bit line BL, and one memory cell MC are shown inFIG. 1 ). Bit lines BL are connected to corresponding sense amplifiers SA within asense circuit 63. - An output of the
column control circuit 52 is supplied to acolumn decoder 62. Thecolumn decoder 62 selects a sense amplifier SA included in thesense circuit 63. A sense amplifier SA selected by thecolumn decoder 62 is connected to a data input/output circuit 70. - The data input/
output circuit 70 is connected to the data input/output terminal DQ, and includes anoutput buffer 71 and animpedance adjusting circuit 72 as shown inFIG. 1 . Theoutput buffer 71 outputs read data via the data input/output terminal DQ, and the impedance adjusting circuit adjusts an output impedance of theoutput buffer 71. Although not shown, the data input/output circuit 70 also includes input buffers. With this arrangement, in a read operation, data read from thememory cell array 60 via thesense circuit 63 and a data input/output circuit 70 is output from the data input/output terminal DQ in a predetermined impedance. On the other hand, in a write operation, write data input to the data input/output terminal DQ is written into thememory cell array 60 via the data input/output circuit 70 and thesense circuit 63. - Adjustment of an impedance by the
impedance adjusting circuit 72 is designated by an impedance code DRZQ supplied from thecalibration circuit 100. Thecalibration circuit 100 performs a calibration operation by referencing a resistance value of an external resistor Re connected to the calibration terminal ZQ, thereby generating the impedance code DRZQ. An calibration operation of thecalibration circuit 100 is started in response to an internal calibration command IZQ or the internal long-calibration command IZQCL supplied from the calibration start-upcircuit 200. Thecalibration circuit 100 is described in detail later. - The calibration start-up
circuit 200 generates the internal calibration command IZQ, and includes anaddress register 210 and acomparator 220 as shown inFIG. 1 . The internal calibration command IZQ is used to perform a short calibration. The calibration start-upcircuit 200 also generates an internal refresh command REF2. The calibration start-upcircuit 200 is also described in detail later. - The internal refresh command REF2 is supplied to the
refresh counter 54 and therow control circuit 51. A count value of therefresh counter 54 is incremented in response to the internal refresh command REF2. This count value shows a row address (the refresh address REFA) to be refreshed. The refresh address REFA is supplied to therow control circuit 51 together with the internal refresh command REF2. Therow control circuit 51 activates a word line shown by the refresh address REFA when the internal refresh command REF2 is activated. Accordingly, all memory cells MC connected to this word line are refreshed. - The overall configuration of the
semiconductor device 10 according to the first embodiment is as described above. -
FIG. 2 is a circuit diagram of the calibration start-upcircuit 200. - As shown in
FIG. 2 , the calibration start-upcircuit 200 includes theaddress register 210 that stores a row address, and thecomparator 220 that compares a row address SETA held in theaddress register 210 with the refresh address REFA. The address register 210 stores an arbitrary row address SETA, and the number of bits of this address matches that of bits of the refresh address REFA in the first embodiment. A value of the row address SETA is not particularly limited. A circuit configuration of theaddress register 210 is not particularly limited, and a fuse circuit and a latch circuit can be used for this circuit. Thecomparator 220 compares these addresses and activates a hit signal HIT1 at a high level when both addresses match. - A hit signal HIT is supplied to a one-shot
pulse generating circuit 230 that is constituted by aNAND gate 231 and adelay circuit 232. Accordingly, when the hit signal HIT1 changes to a high level, a set pulse SET as an output of the one-shotpulse generating circuit 230 is temporarily activated at a low level. The set pulse SET is supplied to a set input end S of anSR latch circuit 240. - The
SR latch circuit 240 has a configuration havingNAND gates NAND gate 241 is the set input end S, and an input end at aNAND gate 242 is a reset input end R. A hit signal HIT2 as an output of theSR latch circuit 240 is supplied to one input end (an inverted input end) of an ANDgate 251, and is also input to one input end of an ANDgate 252. - The internal refresh command REF1 is supplied to the other input end of the AND
gates gate 251 is activated linked to the internal refresh command REF1 in case theSR latch circuit 240 is reset. On the other hand, in case theSR latch circuit 240 is set, the internal refresh command REF2 is not activated even when the internal refresh command REF1 is activated. On the other hand, the internal calibration command IZQ as an output of the ANDgate 252 is activated linked to the internal refresh command REF1 in case theSR latch circuit 240 is set. On the other hand, in case theSR latch circuit 240 is reset, the internal calibration command IZQ is not activated even when the internal refresh command REF1 is activated. - The internal calibration command IZQ is input to the reset input end R of the
SR latch circuit 240 via aninverter 253. Accordingly, theSR latch circuit 240 returns to a reset state when the internal calibration command IZQ is activated. - With the above configuration, the calibration start-up
circuit 200 outputs the internal refresh command REF1 directly as the internal refresh command REF2 when the refresh address REFA does not match the row address SETA. In this case, the internal calibration command IZQ is not activated. On the other hand, the internal calibration command IZQ is activated in response to the internal refresh command REF1 when the refresh address REFA matches the row address SETA. In this case, the internal refresh command REF2 is not activated. That is, the internal refresh command REF1 is converted to the internal calibration command IZQ each time when therefresh counter 54 makes one cycle. - The internal refresh command REF2 generated by the calibration start-up
circuit 200 is supplied to therefresh counter 54 shown inFIG. 1 in this way. Consequently, a count value of therefresh counter 54 is incremented each time when the auto refresh command AR is issued except when the refresh address REFA matches the row address SETA. On the other hand, even when the auto refresh command AR is issued, an increment of a count value of therefresh counter 54 is suspended when the refresh address REFA matches the row address SETA. - The internal calibration command IZQ generated by the calibration start-up
circuit 200 is supplied to thecalibration circuit 100 shown inFIG. 1 . Thecalibration circuit 100 adjusts an output impedance of the output buffer by updating the impedance code DRZQ supplied to theimpedance adjusting circuit 72. The impedance code DRZQ is updated by a calibration operation in response to activation of the internal calibration command IZQ or the internal long-calibration command IZQCL. -
FIG. 3 is a circuit diagram of theoutput buffer 71. - As shown in
FIG. 3 , theoutput buffer 71 includes plural (five in this embodiment) P-channel MOS transistors (output transistors) 311 to 315 connected in parallel between a power source terminal VDDQ and the data input/output terminal DQ, plural (five in this embodiment) N-channel MOS transistors (output transistors) 321 to 325 connected in parallel between a power source terminal VSSQ and the data input/output terminal DQ, and two resistors R connected in series between theoutput transistors 311 to 315 and theoutput transistors 321 to 325. A contact point of the two resistors R is connected to the data input/output terminal DQ. In theoutput buffer 71, apart including the P-channel MOS transistors 311 to 315 and the resistor R constitute a pull-up circuit PU, and a part including the N-channel MOS transistors 321 to 325 and the resistor R constitutes a pull-down circuit PD. - Corresponding bits of an ON signal on P are supplied to gates of the
output transistors 311 to 315, respectively. Corresponding bits of an ON signal on N are supplied to gates of theoutput transistors 321 to 325, respectively. Accordingly, ten output transistors included in theoutput buffer 71 are individually ON/OFF controlled. - The pull-up circuit PU and the pull-down circuit PD are designed to become in a predetermined impedance (120Ω, for example) in a conduction state. However, because an ON resistance of an output transistor varies depending on a manufacturing condition and changes depending on an environmental temperature and a power source voltage at an operation time, a desired impedance is not necessarily obtained. Therefore, to set an actual impedance at a designed value, the number of output transistors to be turned ON needs to be adjusted. For this purpose, a parallel circuit that is constituted by plural output transistors is used.
- To adjust an impedance of the
output buffer 71 finely and in a broad range, preferably, W/L ratios (a gate width/a gate length ratio) of plural output transistors constituting the pull-up circuit PU and the pull-down circuit PD are mutually differentiated. Most preferably, a weight of a power of two is attached to the W/L ratios. That is, when a W/L ratio of theoutput transistor 311 is “1WLp”, it is particularly preferable to set W/L ratios of theoutput transistors 312 to 315 at “2WLp”, “4WLp”, “8WLp”, and “16WLp”, respectively. Similarly, when a W/L ratio of theoutput transistor 321 is “1WLn”, it is particularly preferable to set W/L ratios of theoutput transistors 322 to 325 at “2WLn”, “4WLn”, “8WLn”, and “16WLn”, respectively. - A resistance value of the resistor R is designed at the same value as an ON resistance of the parallel transistors, such as 120Ω. Accordingly, when at least one of the pull-up circuit PU and the pull-down circuit PD is in an ON state, an impedance of the
output buffer 71 from a viewpoint of the data input/output terminal DQ becomes 240Ω (=120Ω+120Ω). A diffusion layer and a high resistance wiring using tungsten (W), titanium nitride (TiN) or the like can be used for the resistor R. -
FIG. 4 is a circuit diagram of thecalibration circuit 100. - As shown in
FIG. 4 , thecalibration circuit 100 includes pull-upcircuits down circuit 103, acounter 110 that designates an impedance of the pull-upcircuits counter 120 that designates an impedance of the pull-down circuit 103, and acontrol circuit 130 that controls operations of thecounters -
FIG. 5 is a circuit diagram of the pull-upcircuit 101. - As shown in
FIG. 5 , the pull-upcircuit 101 has substantially the same circuit configuration as that of the pull-up circuit PU included in theoutput buffer 71. That is, the pull-upcircuit 101 includes five P-channel MOS transistors 411 to 415 connected in parallel to the power source terminal VDDQ, and the resistor R of which one end is connected to drains of these transistors. The other end of the resistor R is connected to the calibration terminal ZQ. - The
transistors 411 to 415 included in the pull-upcircuit 101 correspond to theoutput transistors 311 to 315 shown inFIG. 3 , and these transistors have the same impedance. Therefore, W/L ratios of thetransistors 411 to 415 are set at “1WLp”, “2WLp”, “4WLp”, “8WLp”, and “16WLp”, respectively like the W/L ratios of thetransistors 311 to 315. However, so long as the impedances are substantially the same, thetransistors 411 to 415 included in the pull-upcircuit 101 and theoutput transistors 311 to 315 shown inFIG. 3 do not need to have exactly the same transistor size, and shrunk transistors can be used. - The resistor R also corresponds to the resistor R shown in
FIG. 3 . Therefore, a resistance value of the resistor R is designed at substantially the same value as that of parallel ON resistors of thetransistors 411 to 415, such as 120Ω. - Corresponding bits of an impedance code DRZQP are supplied to gates of the
transistors 411 to 415, respectively from thecounter 110, thereby designating an impedance of the pull-upcircuit 101. - The pull-up
circuit 102 also has the same circuit configuration as that of the pull-upcircuit 101 shown inFIG. 5 except that the other end of the resistor R is connected to a contact point A. Therefore, corresponding bits of the impedance code DRZQP are supplied to gates of five transistors, respectively included in the pull-upcircuit 102. -
FIG. 6 is a circuit diagram of the pull-down circuit 103. - As shown in
FIG. 6 , the pull-down circuit 103 has substantially the same circuit configuration as that of the pull-down circuit PD included in theoutput buffer 71. That is, the pull-down circuit 103 includes five N-channel MOS transistors 421 to 425 connected in parallel to the power source terminal VSSQ, and the resistor R of which one end is connected to drains of these transistors. Thetransistors 421 to 425 included in the pull-down circuit 103 correspond to thetransistors 321 to 325 shown inFIG. 3 , and have the same impedance. The pull-down circuit 103 is similar to the pull-upcircuit 101 in this point. The resistor R also corresponds to the resistor R shown inFIG. 3 . Therefore, a resistance value of this resistor R is designed at substantially the same value as that of parallel ON resistors of thetransistors 421 to 425, such as 120Ω. - Corresponding bits of an impedance code DRZQN are supplied to gates of the
transistors 421 to 425, respectively from thecounter 120, thereby designating an impedance of the pull-down circuit 103. - In this manner, the pull-up
circuits output buffer 71, and the pull-down circuit 103 has substantially the same circuit configuration as that of the pull-down circuit PD included in theoutput buffer 71. Therefore, impedances of the pull-upcircuits down circuit 103 are adjusted at 2400, for example. - As shown in
FIG. 4 , the pull-upcircuit 102 and the pull-down circuit 103 constitute a replica buffer RepB having substantially the same circuit configuration as that of theoutput buffer 71. In this case, “substantially the same” means that even when transistors included in the replica buffer RepB are shrunk, these transistors are regarded the same. The contact point A as an output end of the replica buffer RepB is connected to a non-inverting input terminal (+) of thecomparator 121 as shown inFIG. 4 . - The
counter 110 counts up or counts down when a control signal ACT1 is activated. Thecounter 110 counts up synchronously with the control signal ACT1 when a comparison signal COMP1 as an output of acomparator 111 is at a high level, and counts down synchronously with the control signal ACT1 when the comparison signal COMP1 is at a low level. A non-inverting input terminal (+) of thecomparator 111 is connected to the calibration terminal ZQ, and an inverting input terminal (−) is connected to an intermediate point ofresistors comparator 111 compares a potential of the calibration terminal ZQ with an intermediate voltage (VDD/2). Thecomparator 111 sets the comparison signal COMP1 as an output of comparison at a high level when the potential of the calibration terminal ZQ is higher, and sets the comparison signal COMP1 at a low level when the intermediate voltage (VDD/2) is higher. - On the other hand, the
counter 120 counts up or counts down when a control signal ACT2 is activated. Thecounter 120 counts up synchronously with the control signal ACT2 when a comparison signal COMP2 as an output of thecomparator 121 is at a high level, and counts down synchronously with the control signal ACT2 when the comparison signal COMP2 is at a low level. A non-inverting input terminal (+) of thecomparator 121 is connected to the connection point A as an output end of a replica buffer, and an inverting input terminal (−) is connected to an intermediate point of theresistors comparator 121 compares an output potential of the replica buffer with the intermediate voltage (VDD/2). Thecomparator 121 sets the comparison signal COMP2 as an output of comparison at a high level when the output potential of the replica buffer is higher, and sets the comparison signal COMP2 at a low level when the intermediate voltage (VDD/2) is higher. - The
counters counter 110 is used for the impedance code DRZQP, and a count value of thecounter 120 is used for the impedance code DRZQN. The impedance code DRZQ as a collective term of these codes is supplied to animpedance adjusting circuit 72 shown inFIG. 1 . - The control signals ACT1 and ACT2 are supplied from the
control circuit 130. Thecontrol circuit 130 is started by activation of the internal calibration command IZQ or the internal long-calibration command IZQCL, and activates the control signals ACT1 and ACT2 synchronously with the internal clock signal ICLK. Specifically, thecontrol circuit 130 counts the internal clock signal ICLK corresponding to ½ of a calibration period or continuously activates the control signal ACT1 until an end signal END1 is activated, after the internal calibration command IZQ or the internal long-calibration command IZQCL is activated. Thecontrol circuit 130 counts the internal clock signal ICLK corresponding to ½ of a calibration period or continuously activates the control signal ACT2 until an end signal END2 is activated, after the control signal ACT1 is inactivated. An activation cycle of the control signals ACT1 and ACT2 is set at 2n times (n is a natural number) a clock cycle of the internal clock signal ICLK. - The end signal END1 is generated by an
end determining circuit 131, and is activated when the comparison signal COMP1 as an output of thecomparator 111 changes in a predetermined pattern. Similarly, the end signal END2 is generated by anend determining circuit 132, and is activated when the comparison signal COMP2 as an output of thecomparator 121 changes in a predetermined pattern. The “predetermined pattern” is a change pattern that appears when an impedance of the pull-upcircuits down circuit 103 has reached a target value. A detailed pattern is that the logic level of the comparison signal COMP1 or COMP2 is inverted once or repeatedly, for example. - Accordingly, during one calibration period, an impedance adjustment of the pull-up
circuit 101 is performed in a first half period and an impedance adjustment of the pull-down circuit 103 is performed in a latter half period. However, a calibration method is not limited thereto. In a calibration operation in response to the internal calibration command IZQ, there can be used a method that only either one of the pull-upcircuit 101 and the pull-down circuit 103 is impedance-adjusted during one calibration period and that a circuit to be calibrated is switched each time when the internal calibration command IZQ is issued. This method is effective when a frequency of the internal clock signal ICLK is high and also when it is difficult to adjust both impedances of the pull-upcircuit 101 and the pull-down circuit 103, during one calibration period in response to the internal calibration command IZQ. - A circuit configuration and an operation of the
calibration circuit 100 are as described above. The impedance code DRZQ generated by thecalibration circuit 100 in this way is supplied to theimpedance adjusting circuit 72 shown inFIG. 1 , thereby causing an impedance of theoutput buffer 71 to match an impedance of the replica buffer RepB. Therefore, by periodically performing a calibration operation, the impedance of theoutput buffer 71 can be set closer to a designed value regardless of a temperature change and a voltage variation. -
FIG. 7 is an operation waveform diagram for explaining an operation of thesemiconductor device 10 according to the first embodiment. In an example shown inFIG. 7 , a row address recorded in theaddress register 210 is set at a maximum value −1 (=8K−1) of the refresh address REFA. - As shown in
FIG. 7 , when the auto refresh command AR is issued from outside, the internal refresh command REF2 is usually activated in response to this issuance. Accordingly, a count value of therefresh counter 54 is incremented, and therow control circuit 51 performs a refresh operation. A count value of therefresh counter 54 is proceeded by the auto refresh command AR, and when the refresh address REFA as a count value matches the row address SETA (=8K−1) recorded in theaddress register 210, theSR latch circuit 240 is set in response to this match. Consequently, the internal refresh command REF2 is not activated even when the auto refresh command AR is issued next. The internal calibration command IZQ is activated instead. That is, in this example, the auto refresh command AR at an 8K-th time is handled as the short calibration command ZQCS, and a calibration operation is performed instead of a refresh operation. - When the internal calibration command IZQ is activated, the
SR latch circuit 240 is reset in response to the next auto refresh command AR. Accordingly, thereafter, when the auto refresh command AR is issued, the internal refresh command REF2 is activated as usual. -
FIG. 8 is another operation waveform diagram for explaining an operation of thesemiconductor device 10 according to the first embodiment. As shown inFIG. 8 , in the first embodiment, the internal calibration command IZQ is activated and a short calibration operation is performed each time when therefresh counter 54 makes one cycle by issuing the autorefresh command AR 8K times. A time taken by therefresh counter 54 to make one cycle is set shorter than an information holding time (tREF=64 ms) of the memory cells MC. Therefore, in this example, a calibration operation is performed in a frequency of once per about 64 ms. - The internal refresh command REF2 is not activated when the internal calibration command IZQ is generated, and therefore a count value of the
refresh counter 54 is not incremented at this time. As a result, the number of the auto refresh command AR required for therefresh counter 54 to make one cycle increases by one (=8K+1 times). This means that there is a possibility that the time required for therefresh counter 54 to make one cycle exceeds the information holding time (tREF=64 ms) of the memory cells MC. However, a cycle of issuing the auto refresh command AR is very short of an average 7.8 μs. As, and an information holding time of the memory cells MC is a minimum guaranteed value. Considering the fact that the information holding time is longer in practice, no actual inconvenience occurs. - As shown in
FIG. 8 , when the long calibration command ZQCL is issued, a long calibration operation is performed as usual. - As explained above, in the first embodiment, a calibration operation is started in response to the auto refresh command AR each time when the
refresh counter 54 makes one cycle by issuing the autorefresh command AR 8K times. Therefore, it is not necessary to issue the short calibration command ZQCS from outside. Because the time required for therefresh counter 54 to make one cycle is prescribed by the information holding time (tREF=64 ms) of the memory cells MC, a periodical calibration operation is secured. Because an active command or a read command is not issued until a predetermined time passes after the auto refresh command AR is issued, a read operation or a write operation is not necessary during a calibration. - In the first embodiment, the internal calibration command IZQ is activated each time when the
refresh counter 54 makes one cycle, thereby starting a short calibration operation. However, an activation cycle of the internal calibration command IZQ is not limited to this cycle so long the cycle is based on the number of times that the auto refresh command AR is issued. Therefore, the internal calibration command IZQ can be activated each time when therefresh counter 54 makes a ½ cycle, or the internal calibration command IZQ can be activated each time when therefresh counter 54 makes four cycles, for example. - In the former case, the number of bits of the row address SETA stored in the
address register 210 can be set smaller than that of the refresh address REFA by omitting a highest-order bit, for example. In the latter case, as shown inFIG. 9 , a gate circuit XNOR that compares each bit of the refresh address REFA with each bit of the row address SETA is provided in thecomparator 220, and a two-bit ripple counter C counting a highest-order bit REFAmax of the refresh address REFA is provided. Further, an ANDgate 220 a is used which activates the hit signal HIT1 when an output of the gate circuit XNOR and an output of the ripple counter C all become a high level. - Furthermore, although the
address register 210 that stores an arbitrary row address SETA is used in the first embodiment, it is not essential in the present invention. For example, thecomparator 220 can be configured by an ANDgate 220 b that receives each bit of the refresh address REFA, as shown inFIG. 10 . - A second embodiment of the present invention is explained next.
-
FIG. 11 is a block diagram showing an overall configuration of asemiconductor device 10 a according to the second embodiment. - The
semiconductor device 10 a according to the second embodiment is different from thesemiconductor device 10 shown inFIG. 1 in that the calibration start-upcircuit 200 is replaced by a calibration start-upcircuit 500. Other configurations of thesemiconductor device 10 a according to the second embodiment are identical to those of thesemiconductor device 10 shown inFIG. 1 , and thus like elements are denoted by like reference numerals and explanations thereof will be omitted. - As shown in
FIG. 11 , the calibration start-upcircuit 500 includes acomparator 520 and aswitching circuit 530. Thecomparator 520 compares the row address SETA stored in theaddress register 210 with the refresh address REFA, and is different from thecomparator 220 described above in that thecomparator 520 can switch a cycle of outputting the hit signal HIT1. Theswitching circuit 530 switches the cycle of thecomparator 520. -
FIG. 12 is a circuit diagram of an example of thecomparator 520. - In an example shown in
FIG. 12 , thecomparator 520 includes the gate circuit XNOR that compares each bit of the refresh address REFA with each bit of the row address SETA, an ANDgate 520 a that receives each output of the XNOR, and switches SW1 and SW2 that validate or invalidate a gate circuit XNORi corresponding to a predetermined bit. A control of the switches SW1 and SW2 is performed by a selection signal SEL1 supplied from the switchingcircuit 530. - To validate the gate circuit XNORi, the switch SW1 is set ON, and the switch SW2 is switched to a node a. The node a is an output end of the gate circuit XNORi. Accordingly, the AND
gate 520 a activates the hit signal HIT1 when all bits of the refresh address REFA and the row address SETA match together. That is, an activation cycle of the hit signal HIT1 matches one cycle of therefresh counter 54. - On the other hand, to invalidate the gate circuit XNORi, the switch SW1 is set OFF, and the switch SW2 is switched to a node b. The node b is fixed at a high level. Accordingly, a bit corresponding to the gate circuit XNORi becomes a don't-care bit, and the AND
gate 520 a activates the hit signal HIT1 when other bits of the refresh address REFA and the row address SETA match together. That is, an activation cycle of the hit signal HIT1 matches a ½ cycle of therefresh counter 54. - As explained above, in this example, an activation cycle of the hit signal HIT1, that is, a generation cycle of the internal calibration command IZQ, can be set to either one cycle or a ½ cycle of the
refresh counter 54. -
FIG. 13 is a circuit diagram showing another example of thecomparator 520. - In the example shown in
FIG. 13 , thecomparator 520 includes the gate circuit XNOR that compares each bit of the refresh address REFA with each bit of the row address SETA, the two-bit ripple counter C that counts a highest-order bit REFAmax of the refresh address REFA, an ANDgate 521 that receives each output of the gate circuit XNOR and a lowest-order bit Cmin of the ripple counter C, an ANDgate 522 that receives each output of the gate circuit XNOR and all output bits of the ripple counter C, and aselector 523 that selects one of outputs of the ANDgates selector 523 is performed by a selection signal SEL2 supplied by the switchingcircuit 530. - When an output of the AND
gate 521 is selected, theselector 523 activates the hit signal HIT1 when all bits of the refresh address REFA and the row address SETA match together and also when all outputs of the ripple counter C become a high level. In this case, an activation cycle of the hit signal HIT1 matches four cycles of therefresh counter 54. - On the other hand, when an output of the AND
gate 522 is selected, theselector 523 activates the hit signal HIT1 when all bits of the refresh address REFA and the row address SETA match together and also when a lowest-order bit of the ripple counter C becomes a high level. In this case, an activation cycle of the hit signal HIT1 matches two cycles of therefresh counter 54. - As explained above, in this example, an activation cycle of the hit signal HIT1, that is, a generation cycle of the internal calibration command IZQ, can be set to two cycles or four cycles of the
refresh counter 54. - The configuration of the
switching circuit 530 is not particularly limited, and theswitching circuit 530 can be configured such that the selection signals SEL1 and SEL2 are fixed at a manufacturing time or such that the selection signals SEL1 and SEL2 dynamically change based on an operation environment. As an example of the former case, theswitching circuit 530 can be configured by an antifuse circuit as shown inFIG. 14A . As an example of the latter case, theswitching circuit 530 can be configured by a temperature detecting circuit as shown inFIG. 14B . In the latter example, the selection signals SEL1 and SEL2 are output such that a generation cycle of the internal calibration command IZQ is shortened when the temperature detecting circuit detects a temperature change of a predetermined value or above. Because a property (a resistance, for example) of an element changes greatly according to the temperature, the frequency of performing a calibration operation needs to be increased when there is a large temperature change. - A third embodiment of the present invention is explained next.
-
FIG. 15 is a block diagram showing an overall configuration of asemiconductor device 10 b according to the third embodiment. - The
semiconductor device 10 b according to the third embodiment is different from thesemiconductor device 10 a shown inFIG. 11 in that thecalibration circuit 100 is replaced by acalibration circuit 600. Other configurations of thesemiconductor device 10 b according to the third embodiment are identical to those of thesemiconductor device 10 a shown inFIG. 11 , and thus like elements are denoted by like reference numerals and explanations thereof will be omitted. - As shown in
FIG. 15 , thecalibration circuit 600 includes atimer circuit 610. Thetimer circuit 610 forcibly terminates a short calibration operation started by the internal calibration command IZQ. -
FIG. 16 is a circuit diagram of thecalibration circuit 600. - As shown in
FIG. 16 , thetimer circuit 610 is included in thecontrol circuit 130, and starts time counting in response to activation of the internal calibration command IZQ. Thetimer circuit 610 forcibly causes a calibration operation to be finished when a predetermined time has passed after the internal calibration command IZQ is activated. A counting time by thetimer circuit 610 is set equal to or shorter than a time (for example, 110 ns) allocated to a refresh operation. - With this setting, the
control circuit 130 forcibly finishes a calibration operation when thetimer circuit 610 finishes time counting, even before a calibration period is over based on a count of the internal clock signal ICLK, after generation of the control signals ACT1 and ACT2 is started in response to the internal calibration command IZQ. Consequently, because the calibration operation can be finished within a time range allocated to a refresh operation, thecontrol circuit 130 can receive the next command immediately after the time range allocated to the refresh operation has passed. -
FIG. 17 is a block diagram showing an overall configuration of asemiconductor device 10 c according to a fourth embodiment of the present invention. - The
semiconductor device 10 c according to the fourth embodiment is different from thesemiconductor device 10 shown inFIG. 1 in that the calibration start-upcircuit 200 is replaced by a calibration start-upcircuit 602. Other configurations of thesemiconductor device 10 c according to the fourth embodiment are identical to those of thesemiconductor device 10 shown inFIG. 1 , and thus like elements are denoted by like reference numerals and explanations thereof will be omitted. - As shown in
FIG. 17 , the calibration start-upcircuit 602 includes atemperature detecting circuit 222 in addition to theaddress register 210 and thecomparator 220. Thetemperature detecting circuit 222 measures a temperature at the inside of thesemiconductor device 10 c, and shows temperature information of this measurement by signals T0 and T1. Details thereof will be described later. -
FIG. 18 is a circuit diagram of the calibration start-upcircuit 602 according to the fourth embodiment. - The calibration start-up
circuit 602 according to the fourth embodiment has a configuration having a temperature detection function added to the calibration start-upcircuit 200 according to the first embodiment. Atemperature detecting circuit 224 shows a temperature at the inside of thesemiconductor device 10 c by two-bit signals of the signals T0 and T1. Thetemperature detecting circuit 224 detects a temperature change by using temperature dependency of a voltage of a PN junction of transistors Q1 and Q2. Specifically, first,operational amplifiers temperature detecting circuit 224 can take various configurations, and the configuration shown inFIG. 18 is only an example. - An outline of the operation of the calibration start-up
circuit 602 is as follows. First, the internal refresh command REF1 periodically becomes highly active in response to a periodical input of the auto refresh command AR. The internal refresh command REF1 is input to the ANDgate 251. Normally, the internal refresh command REF1 directly passes through the ANDgate 251, and becomes the internal refresh command REF2. Therefore, a refresh operation is performed each time when the internal refresh command REF1 becomes highly active. - When the refresh address REFA matches the row address SETA, the internal calibration command IZQ is issued under a condition that there is a temperature change. That is, in the fourth embodiment, even when the refresh address REFA matches the row address SETA, a calibration is not performed when there is no temperature change since the addresses have matched last time. A refresh operation is performed when there is no temperature change. Although details are described later, when a temperature change is not detected, the
SR latch 240 is not set, a signal IZQEN becomes a low level, and issuance of the internal calibration command IZQ is blocked. According to this control method, a calibration is omitted when a temperature change does not occur, that is, when a calibration is not really necessary. Therefore, power consumption of thesemiconductor device 10 c can be reduced. - When there is a temperature change, the internal calibration command IZQ is issued. The number of times that the internal calibration command IZQ is issued depends on the scale of a temperature change. In the fourth embodiment, when the scale of a temperature change is equal to or smaller than a predetermined value, the internal calibration command IZQ is issued twice. When the scale of a temperature change is larger than the predetermined value, the internal calibration command IZQ is issued four times. According to this control method, the number of calibration times can be flexibly adjusted according to the necessity of a calibration.
- A configuration and an operation of the calibration start-up
circuit 602 are explained below in detail. First, the internal long-calibration command IZQCL and the hit signal HIT as an output of the one-shotpulse generating circuit 230 are input to anOR gate 238 of two inputs. The hit signal HIT is a one-shot pulse that becomes highly active when the refresh address REFA matches the row address SETA. - When a signal TMON as an output of the
OR gate 238 changes from a low level to a high level,latch circuits latch circuits latch circuits latch circuits 233 and 234. The signal TMON is activated by the internal long-calibration command IZQCL or the hit signal HIT. Thelatch circuit 228 latches a high-level signal (a fixed signal) by activation of the internal long-calibration command IZQCL or the hit signal HIT. The high-level signal is shifted to thelatch circuit 236 by the next activation of the signal TMON. - The
XOR gate 242 compares a signal TB1 signal output from an output node Q of the latch circuit 233 with a signal TN1 output from the output node Q of thelatch circuit 224, and outputs a signal D1. TheXOR gate 244 compares a signal TB0 output from the output node Q of thelatch circuit 234 with a signal TN0 output from the output node Q of thelatch circuit 226, and outputs a signal D2. That is, the signal D1 becomes a high level when there is a change between the signal TB1 as past temperature information and the signal TN1 as subsequent temperature information. Similarly, the signal D2 becomes a high level when there is a change between the signals TB0 and TN0. Accordingly, the temperature change is specified by the signals D1 and D2. - The signals D1 and D2 are input to an
OR gate 246. An output of theOR gate 246 becomes L when D1=D2=0, that is, when there is no temperature change, and becomes H when there is a temperature change. The output of theOR gate 246 is input to an ANDgate 248 of three inputs. Remaining two inputs of the AND gate are the signal TMON and a signal GRDB as an output of thelatch circuit 236. When the hit signal HIT becomes highly active, all the three inputs of the AND gate become a high level, and the one-shot pulse circuit 252 generates a low-level one-shot pulse, and theSR latch circuit 240 is set. As a result, the signal IZQEN as an output of theSR latch circuit 240 becomes highly active. Thelatch circuit 236 is reset when the internal long-calibration command IZQCL becomes highly active. Therefore theSR latch circuit 240 is not set. - When the signal IZQEN becomes highly active, the internal calibration command IZQ is issued instead of the internal refresh command REF2, and a calibration is performed. When there is no temperature change, an output of the AND
gate 248 becomes a low level. Therefore, the signal IZQEN becomes a low level, and the internal refresh command REF2 is issued. When the internal long-calibration command IZQCL is highly active, the signal IZQEN becomes a low level and the internal calibration command IZQ is not issued because the signal GRDB as an output of thelatch circuit 236 becomes a low level although the signals T1 and T0 are latched. However, thecalibration circuit 100 is directly activated by the internal long-calibration command IZQCL (seeFIG. 17 ). By latching the signals T0 and T1 when the command IZQCL is active, temperature information when the command IZQCL is highly active is updated. Accordingly, unnecessary calibrations can be prevented when there is no temperature change after the command IZQCL. - Meanwhile, the signals D1 and D2 are also input to a
decoder 256. Thedecoder 256 activates S1 when both the signals D1 and D2 are at a high level, and activates S0 when one of the signals D1 and D2 is at a high level. S1 and S0 are input to aselector 258. - When the signal IZQEN is activated at a high level, a
counter circuit 260 is reset via a one-shotpulse generating circuit 254. Thereafter, thecounter circuit 260 updates a count value each time when the internal calibration command IZQ is activated. The count value is supplied to theselector circuit 258 as two-bit signals (00 to 11) of C0 and C1. In case S1 is at a high level, theselector circuit 258 activates a one-shot pulse circuit 262 when a count value reaches “00” after counting up from 00. At this time, theSR latch circuit 240 is reset, and the signal IZQEN becomes a low level. Thereafter, the internal refresh command REF2 is issued instead of the internal calibration command IZQ. In case S0 is at a high level, theselector circuit 258 activates the one-shot pulse circuit 262 when a count value reaches “10” after counting up from 00. As a result, In case S1 is at a high level, the internal calibration command IZQ is issued four times. In case S0 is at a high level, the internal calibration command IZQ is issued twice. - When a power ON signal PON is activated at a power activation time, the
latch circuits -
FIG. 19 is an operation waveform diagram for explaining an operation of thesemiconductor device 10 c according to the fourth embodiment. - In
FIG. 19 , the power ON signal PON is activated by one shot at a time t0, and the internal long-calibration command IZQCL is activated by one shot at a time t1. In response to this, thelatch circuits latch circuits latch circuit 228 latches a fixed high-level signal, and outputs the signal from a Q terminal to thelatch circuit 236. - The internal refresh command REF1 periodically becomes highly active by the auto refresh command AR. The refresh address REFA is sequentially designated while being linked to this periodical highly active state. At a time t2, when the refresh address REFA matches the row address SETA designated in advance, the signal TMON becomes highly active. When the signal TMON becomes highly active, the
latch circuits latch circuits latch circuits 233 and 234. Thelatch circuits - The
latch circuit 236 latches a fixed high-level signal, and outputs the signal GRDB at a high level from an output node Q. Because there is no temperature change during a period from the time t1 to the time t2, the signals D1 and D2 remain at a low level. Therefore, an output of the ANDgate 248 remains at a low level, and theSR latch 240 is not set. Because the signal IZQEN becomes inactive, the internal calibration command IZQ is not issued, and the internal refresh command REF2 is issued. That is, a calibration is not performed although the refresh address REFA matches the row address SETA. - At a time t3, the refresh address REFA matches the row address SETA again. During a period from the time t2 to the time t3, the signal T1 changes from H to L, and the signal T0 changes from H to L. Because both the signals T0 and T1 change, it is determined that there is a large temperature change. The signal TMON becomes highly active based on a match of addresses, and new temperature information (T1: L, T0: L) is latched by the
latch circuits latch circuits 233 and 234 latch temperature information (T1: H, T1: H) at the time t2. Because both the signals T1 and T0 change, the signals D1 and D2 become a high level. - Because there is a temperature change, an output of the AND
gate 248 also becomes a high level, the signal IZQEN is activated, and the internal calibration command IZQ is issued. The one-shotpulse generating circuit 254 resets thecounter circuit 260. On the other hand, because both the signals D1 and D0 are at a high level, thedecoder 256 sets S1 highly active. Because S1 is activated, theselector 258 does not reset theSR latch circuit 240 until when a count value output by thecounter circuit 260 reaches “00”. Therefore, the internal calibration command IZQ is thereafter kept to be issued while being linked to the refresh command REF1. Thecounter circuit 260 counts up each time when the command IZQ is issued. When a count value becomes “00”, theSR latch circuit 240 is reset, and thereafter the refresh command REF2 is kept to be issued synchronized with the refresh command REF1. That is, the internal calibration command IZQ is issued four times, and thereafter the refresh command REF2 is kept to be issued. - At a time t4, the refresh address REFA matches the row address SETA again. During a period from the time t3 to the time t4, the signal T1 changes from L to H, but the signal T0 does not change. Although there is a temperature change, this change is small. The
latch circuits latch circuits 233 and 234 latch temperature information (T1: H, T1: H) of the time t3. Because the signal T1 only changes, the signal D1 only becomes a high level. - Because there is a temperature change, the signal IZQEN is activated, the internal calibration command IZQ is issued, and the
counter circuit 260 is reset. Because only the signal D1 is at a high level, thedecoder 256 sets S0 highly active. Because S0 is activated, theselector 258 does not reset theSR latch circuit 240 until when a count value output by thecounter circuit 260 reaches “10”. Accordingly, thereafter, the internal calibration command IZQ is kept to be issued synchronized with the refresh command REF1. When a count value becomes “10”, theSR latch circuit 240 is reset, and thereafter the refresh command REF2 is kept to be issued synchronized with the refresh command REF1. As a result, the internal calibration command IZQ is issued twice. - In the fourth embodiment, a calibration is skipped when there is no temperature change, that is, when a calibration is not really necessary. Power consumption can be reduced by omitting unnecessary calibrations. By changing the number of calibration times according to the scale of a temperature change, a control is performed such that a calibration is performed for a necessary number of times when the calibration is particularly necessary. In this manner, an effective calibration can be performed.
-
FIG. 20 is a block diagram of a data processing system including the semiconductor device 10 (10 a, 10 b, 10 c). - The data processing system shown in
FIG. 20 is configured by the semiconductor device 10 (10 a, 10 b, 10 c) and acontroller 700, and both are connected to each other by acommand bus 701, anaddress bus 702, and adata bus 703. When issuing the auto refresh command AR to the semiconductor device 10 (10 a, 10 b), thecontroller 700 inputs the auto refresh command AR to the semiconductor device 10 (10 a, 10 b, 10 c) via thecommand bus 701. Consequently, the semiconductor device 10 (10 a, 10 b, 10 c) performs a refresh operation or a short calibration operation. In this manner, because the semiconductor device 10 (10 a, 10 b, 10 c) performs a short calibration operation in response to an input of the auto refresh command AR of a predetermined number of times, thecontroller 700 does not need to perform a short calibration command (ZQCS). That is, thecontroller 700 does not need to have a timer circuit to periodically issue the short calibration command (ZQCS). - However, the
controller 700 can also issue the short calibration command (ZQCS), and the semiconductor device 10 (10 a, 10 b, 10 c) can perform a short calibration operation in response to the short calibration command (ZQCS). In this case, it suffices to provide an ORgate 254 that receives an output of the ANDgate 252 and an internal short-calibration command IZQCS, like a calibration start-upcircuit 200 a shown inFIG. 21 . - It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
Claims (20)
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US14/720,524 US9378799B2 (en) | 2009-09-11 | 2015-05-22 | Semiconductor device having a memory and calibration circuit that adjusts output buffer impedance dependent upon auto-refresh commands |
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US14/720,524 Expired - Fee Related US9378799B2 (en) | 2009-09-11 | 2015-05-22 | Semiconductor device having a memory and calibration circuit that adjusts output buffer impedance dependent upon auto-refresh commands |
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US20150269985A1 (en) | 2015-09-24 |
US9378799B2 (en) | 2016-06-28 |
US9043539B2 (en) | 2015-05-26 |
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