US10615593B2 - Inrush current limit circuitry and method - Google Patents
Inrush current limit circuitry and method Download PDFInfo
- Publication number
- US10615593B2 US10615593B2 US15/805,165 US201715805165A US10615593B2 US 10615593 B2 US10615593 B2 US 10615593B2 US 201715805165 A US201715805165 A US 201715805165A US 10615593 B2 US10615593 B2 US 10615593B2
- Authority
- US
- United States
- Prior art keywords
- voltage
- electronically controlled
- controlled switch
- function
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/001—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection limiting speed of change of electric quantities, e.g. soft switching on or off
Definitions
- the invention relates generally to the field of powered devices and particularly to a circuitry and method for inrush current limiting.
- Power over Ethernet provides for a power supply equipment (PSE) which supplies power over structured cabling to a remotely stationed powered device (PD).
- PSE power supply equipment
- PD remotely stationed powered device
- the port capacitor draws an inrush current from the PSE which may be very large.
- the inrush current into the powered device must be limited, under certain conditions as defined therein, to a maximum value.
- Prior art current limiters use a sense resistor to sense the value of the inrush current and control a transistor within the current path to limit the inrush current to the acceptable maximum value. Unfortunately, the inrush current flowing through the sense resistor dissipates heat which wastes power. Additionally, the sense resistor must be very accurate, which adds cost.
- an inrush current limit circuitry comprising: a first electronically controlled switch, a first terminal of the first electronically controlled switch in electrical communication with a port capacitor; a ramp voltage circuitry arranged to generate a ramped voltage at an output thereof; a first differential amplifier, a first input of the first differential amplifier arranged to receive a first function of the voltage across the port capacitor, a second input of the first differential amplifier coupled to the output of the ramp voltage circuitry and an output of the first differential amplifier coupled to a second terminal of the electronically controlled switch such that the voltage across the port capacitor is a linear function of the generated ramped voltage; a second electronically controlled switch, a first terminal of the second electronically controlled switch coupled to the output of the ramp voltage circuitry and a second terminal of the second electronically controlled switch coupled to a predetermined common voltage such that the second electronically controlled switch is arranged in a closed state to pull the output of the ramp voltage circuitry towards the predetermined
- FIG. 1 illustrates a high level schematic diagram of an inrush current limit circuitry, according to certain embodiments
- FIG. 2 illustrates a high level schematic diagram of a more detailed embodiment of the inrush current limit circuitry of FIG. 1 , according to certain embodiments.
- FIG. 3 illustrates a high level flow chart of an inrush current limiting method, according to certain embodiments.
- FIG. 1 illustrates a high level schematic diagram of an inrush current limit circuitry 10 comprising: an electronically controlled switch S 1 , implemented and described herein in one non-limiting embodiment as an n-channel metal-oxide-semiconductor field-effect-transistor (NFET); a differential amplifier 20 ; a first function circuitry 30 ; a ramp voltage circuitry 40 ; an electronically controlled switch S 2 , implemented and described herein in one non-limiting embodiment as an NFET; a comparator 50 ; and a control circuitry 60 .
- a port capacitor CP and a supply voltage VPD are further illustrated external to inrush current limit circuitry 10 .
- the inrush current charges port capacitor CP, the inrush current denoted I CP .
- a load (not shown) is provided across port capacitor CP, and thus any load current flows from supply voltage VPD through the load returning via electronically controlled switch S 1 .
- the term differential amplifier as used throughout this document, is understood to mean an amplifier whose output is proportional to the difference between the voltages applied to its two inputs. Comparators, as used throughout this document, may integrate hysteresis circuitry to increase noise immunity, without exceeding the scope.
- a first end of port capacitor CP is coupled to supply voltage VPD and a respective input of first function circuitry 30 .
- the drain of NFET S 1 is coupled to a second end of port capacitor CP and a respective input of first function circuitry 30 , the signal thereon denoted VPN_OUT.
- An output of first function circuitry 30 is coupled to an inverting input of differential amplifier 20 , the signal thereon denoted VINN_OA 2 .
- the output of differential amplifier 20 is coupled to the gate of NFET S 1 .
- a non-inverting input of differential amplifier 20 is coupled to an output of ramp voltage circuitry 40 , the signal thereon denoted VG, and to the drain of NFET S 2 .
- each of NFETs S 1 and S 2 is coupled to a common potential, illustrated without limitation as ground.
- the gate of NFET S 2 is coupled to an output of comparator 50 and an inverting input of comparator 50 is coupled to a reference voltage, denoted VREF 1 .
- a non-inverting input of comparator 50 is coupled to an output of control circuitry 60 and a first input of control circuitry 60 is coupled to the drain of NFET S 1 (connection not shown for simplicity) carrying signal VPN_OUT.
- a second input of control circuitry 60 is coupled to a predetermined voltage signal, denoted VCHARGE.
- first function circuitry 30 is arranged to output a first function of the voltage across port capacitor CP, i.e. VPD ⁇ VPN_OUT as signal VINN_OA 2 .
- ramp voltage circuitry 40 is arranged to generate a linear ramped voltage at the output thereof, the signal denoted VG as indicated above.
- Differential amplifier 20 is arranged to amplify the difference between signal VINN_OA 2 and signal VG, thereby controlling the gate voltage of NFET S 1 such that VINN_OA 2 tracks signal VG, and since input voltage VPD is fixed, voltage VPN_OUT tracks signal VG, as further described below.
- port capacitor CP is charged with current so as to exhibit a linear ramped voltage there across, ensuring that the inrush current exhibits a fixed magnitude.
- V CP the derivative thereof is a fixed value.
- the magnitude of inrush current I CP is a fixed value, the value being controlled by ramp voltage circuitry 40 and first function circuitry 30 , as will be described further below.
- comparator 50 is arranged to compare a predetermined function of drain voltage VPN_OUT, provided by control circuitry 60 , with reference voltage VREF 1 .
- reference voltage VREF 1 which is an indication of a short circuit across port capacitor CP
- comparator 50 is arranged to close NFET S 2 thereby pulling signal VG to the common potential. Responsive to signal VG being pulled to the common potential, differential amplifier 20 switches off NFET S 1 and the current flowing into port capacitor CP is cut off.
- Control circuitry 60 provides short circuit protection during 2 separate operating modes: during charge up of port capacitor CP; and during operation when port capacitor CP is assumed to be fully charged. Particularly, as will be described below, during the charge up mode, VPN_OUT is not initially coupled to the non-inverting input of comparator 50 by control circuitry 60 . When port capacitor CP is finished charging, VPN_OUT is equal to VCHARGE, or to a function thereof, and responsive thereto control circuitry 60 detects that the operation mode is initiated and responsive to the detection connects voltage VPN_OUT to the non-inverting input of comparator 50 .
- the voltage across NFET S 1 should not be higher than the maximum allowed current flowing therethrough multiplied by the on resistance thereof, which is reflected by reference voltage VREF 1 . Therefore, if the voltage thereacross, or a predetermined function thereof, exceeds VREF 1 , NFET S 1 is shut off.
- control circuitry 60 detects that the voltage across port capacitor CP is not linearly ramped. In such an event, control circuitry 60 connects voltage VPN_OUT to the non-inverting input of comparator 50 . Since port capacitor CP is not completely charged, VPN_OUT is greater than VREF 1 and differential amplifier 20 switches off NFET S 1 , as described above.
- FIG. 2 illustrates a high level schematic view of a more detailed embodiment of inrush current limiting circuitry 10 .
- first function circuitry 30 comprises: a differential amplifier 70 ; a pair of resistors R 1 ; and a pair of resistors R 2 , thus functioning as a difference amplifier, where the output voltage is a linear function of the difference between the input voltages.
- Ramp voltage circuitry comprises: a current source 80 ; and a capacitor CG.
- Control circuitry 60 comprises: a pair of resistors R 5 and R 6 ; an electronically controlled switch S 3 , implemented and described herein in one non-limiting embodiment as an NFET; a capacitor C 1 ; a latch 90 , implemented and described herein in one non-limiting embodiment as a D flip flop; a comparator 100 ; an electronically controlled switch S 4 , implemented and described herein in one non-limiting embodiment as an NFET; a comparator 110 ; and a voltage source 120 .
- the inverting input of differential amplifier 20 is coupled to a first end of first resistor R 1 and an output of differential amplifier 70 .
- a second end of first resistor R 1 is coupled to an inverting input of differential amplifier 70 and to a first end of a first resistor R 2 .
- a second end of first resistor R 2 is coupled to the drain of NFET S 1 .
- a first end of second resistor R 2 is coupled to supply voltage VPD and a second end of second resistor R 2 is coupled to a first end of second resistor R 1 and to a non-inverting input of differential amplifier 70 .
- a second end of second resistor R 1 is coupled to the common potential.
- a first end of current source 80 is coupled to the non-inverting input of differential amplifier 20 , to a first end of capacitor CG, to the drain of NFET S 2 and to a non-inverting input of comparator 110 .
- a second end of each of current source 80 and capacitor CG is coupled to the common potential.
- a first end of voltage source 120 is coupled to an inverting input of comparator 110 and a second end of voltage source 120 is coupled to the output of differential amplifier 70 .
- An output of comparator 110 is coupled to the drain of NFET S 4 and the source of NFET S 4 is coupled to the set input of D flip flop 90 .
- the gate of NFET S 4 is coupled to the inverted output of D flip flop 90 (connection not shown for simplicity).
- An inverting input of comparator 100 is coupled to the drain of NFET S 1 (connection not shown for simplicity) and a non-inverting input of comparator 100 is coupled to a charge reference voltage denoted VCHARGE.
- An output of comparator 100 is coupled to the clock input of D flip flop 90 .
- the D input of D flip flop 90 is coupled to a voltage, denoted V+, which represents a logical “1”.
- the non-inverted output of D flip flop 90 is coupled to the gate of NFET S 3 .
- the drain of NFET S 3 is coupled to a first end of resistor R 5 and a second end of resistor R 5 is coupled to the drain of NFET S 1 (connection not shown for simplicity).
- the source of NFET S 3 is coupled to a first end of resistor R 6 , to a first end of capacitor C 1 and to the non-inverting input of comparator 50 .
- a second end of each resistor R 6 and capacitor C 1 is coupled to the common potential.
- ramp voltage circuitry 40 is arranged to generate a ramped voltage VG.
- current source 80 is arranged to output a current, denoted IG, which charges capacitor CG.
- the magnitude of current IG exhibits a fixed value, thereby generating a linear ramped voltage VG across capacitor CG, as described above in relation to EQ. 1.
- Current source 80 is arranged to drive current IG as long as the voltage across capacitor CG is less than a predetermined value, e.g. less than V CC , and not drive current IG when the voltage across capacitor CG is equal to, or greater than, V CC .
- first function circuitry 30 is arranged to output a predetermined function of the voltage across port capacitor CP.
- VINN_OA 2 V CP *( R R1 /R R2 ) EQ. 2
- V CP is the voltage across port capacitor CP, i.e. VPD ⁇ VPN_OUT
- R R1 is the resistance value of each of resistors R 1
- R R2 is the resistance value of each of resistors R 2 .
- VINN_OA 2 is compared with ramped voltage VG and differential amplifier 20 is arranged to control the gate voltage of NFET S 1 such that VINN_OA 2 is equal to voltage VG.
- VINN_OA 2 is a linear function of port capacitor voltage V CP , as described in EQ. 2
- an inrush current to port capacitor CP is controlled to be equal to a predetermined function of current IG of current source 80 of ramp voltage circuitry 40 , responsive to the resistance values of resistors R 1 and R 2 and the capacitance value of port capacitor CP, specifically:
- ICP C CG C CP * IG * R R ⁇ ⁇ 2 R R ⁇ ⁇ 1 EQ . ⁇ 4
- C CP is the capacitance value of port capacitor CP
- C CG is the capacitance value of capacitor CG of ramp voltage circuitry 40 .
- I CP is controlled with an accuracy responsive to the accuracy of the values C CP and C CG .
- I CP need not be carefully controlled and is allowed a broad range of potential limits, e.g. 100 mA-240 mA.
- the inrush current of port capacitor CP is limited by inrush current limiting circuitry 10 without the use of an external sense resistor.
- the magnitude of the inrush current I CP is controlled by the capacitance values of capacitors CG and CP and the resistance ratio between resistors R 1 and R 2 .
- the resistance ratio between resistors on a chip is known and very accurate.
- Comparator 100 is arranged to compare drain voltage VPN_OUT of NFET S 1 with charge reference voltage VCHARGE in order to determine whether port capacitor CP has completely charged.
- charge reference voltage VCHARGE is selected from the range of 50-100 mV. Particularly, once port capacitor CP has completely charged the voltage value thereacross will be slightly less than supply voltage VPD and drain voltage VPN_OUT will be slightly more than the common potential. Therefore, when VPN_OUT drops below VCHARGE, port capacitor CP is considered charged and comparator 100 is arranged to output a high signal, denoted LATCH_CLK, to the clock input of D flip flop 90 .
- D flip flop 90 Responsive to high signal LATCH_CLK, D flip flop 90 is arranged to output voltage V+ to the gate of NFET S 3 .
- Voltage V+ which is a high voltage, closes NFET S 3 thereby coupling drain voltage VPN_OUT to the non-inverting input of comparator 50 .
- the voltage divider formed by resistors R 5 and R 6 , and capacitor C 1 filters VPN_OUT to reduce noise from reaching the input of comparator 50 .
- comparator 50 is arranged to close NFET S 2 whenever a short circuit condition is present across port capacitor CP.
- the maximum value of drain voltage VPN_OUT in relation to the common potential should be the maximum magnitude of the current flowing through NFET S 1 multiplied by the on resistance of NFET S 1 , the maximum voltage value reflected by reference voltage VREF 1 .
- voltage function VPN_OUT will be greater than VREF 1 and comparator 50 closes NFET S 2 .
- the closing of NFET S 2 rapidly discharges capacitor CG and sinks current IG to the common potential.
- comparator 50 is arranged to detect a short circuit condition across port capacitor CP after start up, i.e. during operating mode.
- comparator 110 is arranged to detect a short circuit condition across port capacitor CP during start up, i.e. during charge up mode.
- a predetermined function of voltage VINN_OA 2 is compared with voltage VG of ramp voltage circuitry 40 .
- voltage VINN_OA 2 is supposed to be equal to voltage VG and a difference between voltages VINN_OA 2 and VG is indicative of a short circuit condition across port capacitor CP.
- the phrase equal to means within an offset value of differential amplifier 20 , which is typically in the range of ⁇ 5 mV for standard accuracy op-amp, and may drop to a few ⁇ V for high-accuracy op-amps.
- the predetermined function of voltage VINN_OA 2 is voltage VINN_OA 2 plus a short circuit voltage value output by voltage source 120 , denoted VS.
- short circuit voltage VS is about 20 mV.
- short circuit voltage VS is selected such that VS times the internal gain of differential amplifier 20 is greater than the maximum output voltage range of differential amplifier 20 .
- differential amplifier 20 is able to compensate for the difference by adjusting the gate voltage of NFET S 1 accordingly. If the difference is too great, differential amplifier 20 will no longer be able to compensate and NFET S 1 will need to be switched off.
- comparator 100 is arranged to output a high signal LATCH_CLK to the clock of D flip flop 90 only when port capacitor CP is fully charged.
- signal LATCH_CLK is thus low and the inverted output of D flip flop 90 will be high, i.e. V+. Therefore, while port capacitor CP is charging, NFET S 4 is closed and the output of comparator 110 is coupled to the set input of D flip flop 90 .
- VINN_OA 2 doesn't rise as fast VG, i.e. VG is greater than VINN_OA2+VS, the output of comparator 110 is high thereby setting D flip flop 90 to output voltage V+ to the gate of NFET S 3 .
- comparator 50 compares a function of VPN_OUT to VREF 1 . Since port capacitor CP is not yet fully charged, the function of VPN_OUT will be greater than VREF 1 and comparator 50 closes NFET S 2 thereby drawing voltage VG to the common potential, thus causing differential amplifier 20 to switch off NFET S 1 .
- FIG. 3 illustrates a high level flow chart of an inrush current limiting method.
- a ramped voltage is generated.
- a first function of a voltage across a port capacitor is compared with the generated ramp voltage of stage 1000 .
- an electronically controlled switch coupled to the port capacitor is controlled such that the voltage across the port capacitor is a linear function of the generated ramped voltage of stage 1000 .
- the electronically controlled switch is implemented as an NFET, the gate voltage of the NFET controlled responsive to the outcome of the comparison of stage 1010 such that the voltage at the drain thereof is a linear function of the generated ramped voltage of stage 1000 .
- the port capacitor is coupled between a fixed supply voltage and the drain of the NFET, therefore the port capacitor voltage is also linearly ramped.
- a second function of the voltage at a terminal of the electronically controlled switch of stage 1020 is compared with a predetermined reference voltage.
- the comparison is performed responsive to either one of: the voltage at the terminal of the electronically controlled switch being less than a predetermined charge value; and the difference between the first function of the terminal voltage and the generated ramp voltage of stage 1000 being greater than a predetermined short circuit value.
- the terminal voltage of the electronically controlled switch is compared with the predetermined charge value and the outcome of the comparison is input into a first input of a latch, optionally a clock input of the latch.
- the first function of the terminal voltage of the electronically controlled switch is compared with the generated ramp voltage and the outcome of the comparison is input into a second input of the latch, optionally a set input of the latch.
- the comparison of the second function of the terminal voltage of the electronically controlled switch with the predetermined reference voltage is responsive to an output of the latch.
- the output of the latch is arranged to alternately open and close an electronically controlled switch. When the electronically controlled switch is closed the terminal voltage second function is coupled to a comparator and when the electronically controlled switch is open the terminal voltage second function is decoupled from the comparator.
- the inputting of the comparison outcome into the second latch input is performed responsive to the outcome of the comparison of the terminal voltage and the predetermined charge value indicating that the terminal voltage is greater than the predetermined charge value, i.e. indicating that the port capacitor is not yet fully charged.
- stage 1040 responsive to the outcome of the comparison of stage 1030 indicating that the second function of the terminal voltage is greater than the predetermined reference voltage, the generated ramp voltage of stage 1000 is pulled towards a shutoff voltage.
- the electronically controlled switch of stage 1020 is implemented as an NFET
- the source of the NFET is coupled to the shutoff voltage.
- the shutoff voltage is implemented as the common voltage.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
I CP =C CP *dV CP /dt EQ. 1
where CCP is the capacitance of port capacitor CP and VCP is the voltage across port capacitor CP, i.e. VPD−VPN_OUT. For a linearly ramped voltage VCP, the derivative thereof is a fixed value. As a result, the magnitude of inrush current ICP is a fixed value, the value being controlled by
VINN_OA2=V CP*(R R1 /R R2) EQ. 2
where VCP is the voltage across port capacitor CP, i.e. VPD−VPN_OUT, RR1 is the resistance value of each of resistors R1 and RR2 is the resistance value of each of resistors R2.
V CP =VG*(R R2 /R R1) EQ. 3
Thus, an inrush current to port capacitor CP is controlled to be equal to a predetermined function of current IG of
where CCP is the capacitance value of port capacitor CP and CCG is the capacitance value of capacitor CG of
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/805,165 US10615593B2 (en) | 2016-11-29 | 2017-11-07 | Inrush current limit circuitry and method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662427189P | 2016-11-29 | 2016-11-29 | |
US15/805,165 US10615593B2 (en) | 2016-11-29 | 2017-11-07 | Inrush current limit circuitry and method |
Publications (2)
Publication Number | Publication Date |
---|---|
US20180152017A1 US20180152017A1 (en) | 2018-05-31 |
US10615593B2 true US10615593B2 (en) | 2020-04-07 |
Family
ID=62190529
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/805,165 Active 2038-08-17 US10615593B2 (en) | 2016-11-29 | 2017-11-07 | Inrush current limit circuitry and method |
Country Status (1)
Country | Link |
---|---|
US (1) | US10615593B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11165243B2 (en) * | 2019-04-24 | 2021-11-02 | Acer Incorporated | Power supply apparatus |
US11418022B2 (en) | 2020-07-29 | 2022-08-16 | Sl Power Electronics Corporation | Active inrush current limiter |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10712426B2 (en) * | 2018-12-11 | 2020-07-14 | Texas Instruments Incorporated | Fault tolerant digital input receiver circuit |
US11239656B2 (en) * | 2019-07-19 | 2022-02-01 | Texas Instruments Incorporated | Methods and apparatus for current sensing and current limiting |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6335654B1 (en) | 2000-03-17 | 2002-01-01 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Inrush current control circuit |
US20050286200A1 (en) * | 2004-06-16 | 2005-12-29 | Yazaki Corporation | Control apparatus of semiconductor switch |
US7019583B2 (en) | 2001-01-29 | 2006-03-28 | Axiohm Transaction Solutions, Inc. | Current inrush limiting circuit |
US9063558B2 (en) * | 2010-02-17 | 2015-06-23 | Ricoh Company, Ltd. | Current limiting circuit configured to limit output current of driver circuit |
-
2017
- 2017-11-07 US US15/805,165 patent/US10615593B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6335654B1 (en) | 2000-03-17 | 2002-01-01 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Inrush current control circuit |
US7019583B2 (en) | 2001-01-29 | 2006-03-28 | Axiohm Transaction Solutions, Inc. | Current inrush limiting circuit |
US20050286200A1 (en) * | 2004-06-16 | 2005-12-29 | Yazaki Corporation | Control apparatus of semiconductor switch |
US9063558B2 (en) * | 2010-02-17 | 2015-06-23 | Ricoh Company, Ltd. | Current limiting circuit configured to limit output current of driver circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11165243B2 (en) * | 2019-04-24 | 2021-11-02 | Acer Incorporated | Power supply apparatus |
US11418022B2 (en) | 2020-07-29 | 2022-08-16 | Sl Power Electronics Corporation | Active inrush current limiter |
Also Published As
Publication number | Publication date |
---|---|
US20180152017A1 (en) | 2018-05-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10615593B2 (en) | Inrush current limit circuitry and method | |
US7276888B2 (en) | Precharge circuit for DC/DC boost converter startup | |
US11996765B2 (en) | Current limit control circuit and switched-mode power supply chip incorporating same | |
US9893517B2 (en) | Electrostatic discharge protection circuitry | |
US20150130434A1 (en) | Fast current limiting circuit in multi loop ldos | |
US9590502B2 (en) | Regulated switching converter | |
US8300376B2 (en) | Temperature protection circuit | |
KR101771719B1 (en) | Battery state monitoring circuit and battery device | |
US20070176582A1 (en) | Constant voltage circuit | |
US20140320197A1 (en) | Gate driver circuit | |
US20190050011A1 (en) | Regulator circuit | |
WO2015146041A1 (en) | Drive device | |
US20190131870A1 (en) | Precharge circuit using non-regulating output of an amplifier | |
US7466171B2 (en) | Voltage detection circuit and circuit for generating a trigger flag signal | |
US10243550B2 (en) | High voltage comparator | |
US7741870B2 (en) | Multi-function input terminal | |
JP2881729B2 (en) | Burn-in detection circuit for semiconductor memory | |
US20230343779A1 (en) | Esd protection circuit | |
CN101673943A (en) | Electrostatic discharge protection circuit and method thereof | |
US9473114B1 (en) | Power-on-reset detector | |
US7005924B2 (en) | Current limiting circuit with rapid response feedback loop | |
US7248092B2 (en) | Clamp circuit device | |
US10008656B1 (en) | Piezo actuator driver with slew rate protection | |
US9960755B2 (en) | Low voltage switching gate driver under a high voltage rail | |
US7808062B2 (en) | Signal isolator linear receiver |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: MICROSEMI P.O.E. LTD., ISRAEL Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LANGER, TAMIR;REEL/FRAME:044119/0468 Effective date: 20161129 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT RECEIVED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |