TWI779578B - Data boundary detection circuit and control chip and electronic device using the same - Google Patents
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Abstract
一種數據邊界偵測電路,其具有:一暫存單元,用以以移位的方式儲存多筆輸入字符字節數據,且其係依一輸出邊界位址選取兩筆連續的所述輸入字符字節數據以提供一筆輸出數據;以及一邊界位址產生單元,用以依一可更新的邊界位址及一可更新的位址偏移值之和產生該輸出邊界位址,其中,該可更新的邊界位址係由一筆同步用數據之一邊界字符在所述多筆輸入字符字節數據中出現之一邊界位址所更新,該可更新的位址偏移值係由該邊界位址之一目前值與一先前值之一差值所更新。A data boundary detection circuit, which has: a temporary storage unit for storing multiple input character byte data in a shifted manner, and it selects two consecutive input character words according to an output boundary address Section data to provide a piece of output data; and a boundary address generation unit, used to generate the output boundary address according to the sum of an updatable boundary address and an updatable address offset value, wherein the updatable The boundary address is updated by a boundary address in which a boundary character of a piece of synchronization data appears in the multiple input character byte data, and the updateable address offset value is updated by the boundary address Updated by the difference between a current value and a previous value.
Description
本發明係有關高速數據接收,尤指一種用以確保高速數據不致錯位接收之邊界偵測電路。The present invention relates to high-speed data reception, especially a boundary detection circuit for ensuring that high-speed data is received without misalignment.
在數據傳輸的速率要求越來越高的情況下,有越來越多的電子裝置選擇C-PHY介面代替D-PHY介面作為高速通信介面,資料寬度也由協定中規定的7字符(Symbol)擴展到14字符(Symbol),其中,D-PHY介面具有多個差動通道,其中一通道傳送一時鐘信號,其餘通道傳送數據; 相對地,C-PHY介面具有至少一個三線通道以傳輸數據,而其時鐘信號則係在接收端對由C-PHY介面信號轉成的數據信號進行時鐘恢復運算而得。In the case of higher and higher data transmission rate requirements, more and more electronic devices choose the C-PHY interface instead of the D-PHY interface as the high-speed communication interface, and the data width is also specified in the agreement. 7 characters (Symbol) Extended to 14 characters (Symbol), wherein, the D-PHY interface has multiple differential channels, one of which transmits a clock signal, and the remaining channels transmit data; relatively, the C-PHY interface has at least one three-wire channel to transmit data, The clock signal is obtained by performing a clock recovery operation on the data signal converted from the C-PHY interface signal at the receiving end.
然而,在C-PHY通信的過程中,由於時鐘信號是由數據信號恢復出來的,當數據在高速序列傳輸的過程中出錯或丟失,恢復出來的時鐘信號也會跟著出錯,致使數據邊界發生錯位及造成接續的DSI-2協定解析邏輯單元出現解包錯誤。因此,在C-PHY傳輸中,就需要動態的跟蹤數據邊界是否正確。However, in the process of C-PHY communication, since the clock signal is recovered from the data signal, when the data is wrong or lost during high-speed serial transmission, the recovered clock signal will also be wrong, resulting in misalignment of the data boundary And cause an unpacking error to occur in the subsequent DSI-2 protocol parsing logic unit. Therefore, in C-PHY transmission, it is necessary to dynamically track whether the data boundary is correct.
為解決上述的問題,一般的做法是在C-PHY協定中增加同步資訊,以在數據傳輸過程中根據同步資訊判定同步是否丟失,如果資料邊界同步丟失,則需要儘快恢復資料邊界的同步以確保下一個數據包的正確擷取。亦即,如何快速判定邊界同步丟失及盡快恢復數據邊界,以最小化數據損失就成了C-PHY通信設計中的關鍵重點之一。In order to solve the above problems, the general approach is to add synchronization information in the C-PHY protocol to determine whether the synchronization is lost during data transmission. If the synchronization of the data boundary is lost, it is necessary to restore the synchronization of the data boundary as soon as possible to ensure The correct capture of the next packet. That is, how to quickly determine the boundary synchronization loss and restore the data boundary as soon as possible to minimize data loss has become one of the key points in the C-PHY communication design.
然而,在採用14字符(Symbol)的並行數據傳輸設計中,如圖1所示,同步資訊卻可能存在高7字符(Symbol)中或低7字符(Symbol)中,致使三個C-PHY通道間的同步確定過程變得異常複雜。However, in the parallel data transmission design using 14 symbols (Symbol), as shown in Figure 1, the synchronization information may exist in the upper 7 symbols (Symbol) or the lower 7 symbols (Symbol), resulting in three C-PHY channels The process of determining the synchronization between them becomes extremely complicated.
因此,本領域亟需一種新穎的數據邊界偵測電路。Therefore, there is an urgent need in the art for a novel data boundary detection circuit.
本發明之一目的在於提供一種數據邊界偵測電路,其可藉由定義一邊界地址範圍,及利用一簡潔的循序邏輯電路對一同步用數據的邊界字符出現在該邊界地址範圍內的前、後位置進行一邊界地址計算,而能快速恢復正確的數據擷取邊界以最小化數據損失。An object of the present invention is to provide a data boundary detection circuit, which can define a boundary address range and utilize a simple sequential logic circuit to detect a synchronization data boundary character before and after the boundary character within the boundary address range A boundary address calculation is performed at the last position, and the correct data capture boundary can be quickly restored to minimize data loss.
本發明之另一目的在於提供一種控制晶片,其可藉由上述之數據邊界偵測電路快速恢復正確的數據擷取邊界以最小化數據損失。Another object of the present invention is to provide a control chip, which can quickly restore the correct data capture boundary through the above-mentioned data boundary detection circuit to minimize data loss.
本發明之又一目的在於提供一種電子裝置,其可藉由上述之控制晶片快速恢復正確的數據擷取邊界以最小化數據損失。Another object of the present invention is to provide an electronic device, which can quickly restore the correct data capture boundary through the above-mentioned control chip to minimize data loss.
為達到前述之目的,一種數據邊界偵測電路乃被提出,其具有:In order to achieve the aforementioned purpose, a data boundary detection circuit is proposed, which has:
一暫存單元,用以以移位的方式儲存多筆輸入字符字節數據,且其係依一輸出邊界位址選取兩筆連續的所述輸入字符字節數據以提供一筆輸出數據;以及A temporary storage unit is used to store multiple input character byte data in a shifted manner, and it selects two consecutive input character byte data according to an output boundary address to provide an output data; and
一邊界位址產生單元,用以依一可更新的邊界位址及一可更新的位址偏移值之和產生該輸出邊界位址,其中,該可更新的邊界位址係由一筆同步用數據之一邊界字符在所述多筆輸入字符字節數據中出現之一邊界位址所更新,該可更新的位址偏移值係由該邊界位址之一目前值與一先前值之一差值所更新。A boundary address generating unit is used to generate the output boundary address according to the sum of an updateable boundary address and an updateable address offset value, wherein the updateable boundary address is generated by a synchronous A boundary character of the data is updated by a boundary address that appears in the multiple input character byte data, and the updateable address offset value is one of a current value and a previous value of the boundary address The difference is updated.
在一實施例中,該暫存單元具有:In one embodiment, the temporary storage unit has:
一移位暫存器,用以儲存所述多筆輸入字符字節數據;以及a shift register for storing the plurality of input character byte data; and
一控制電路,用以依該輸出邊界位址自該移位暫存器中讀取兩筆連續的所述輸入字符字節數據以提供所述輸出數據。A control circuit is used for reading two consecutive pieces of input character byte data from the shift register according to the output boundary address to provide the output data.
在一實施例中,該邊界位址產生單元具有:In one embodiment, the boundary address generating unit has:
一邊界偵測單元,用以依該移位暫存器之儲存內容偵測出該同步用數據之該邊界字符在一邊界範圍中之位置,並只在偵測出該邊界字符時才更新該可更新的邊界位址的內容。A boundary detection unit, used for detecting the position of the boundary character of the synchronization data in a boundary range according to the storage content of the shift register, and updating the boundary character only when the boundary character is detected The content of the updatable boundary address.
在一實施例中,該邊界位址產生單元進一步具有: 一邊界位址儲存單元以儲存該可更新的邊界位址。 In one embodiment, the boundary address generating unit further has: A boundary address storage unit stores the updateable boundary address.
在一實施例中,該邊界位址產生單元進一步具有:In one embodiment, the boundary address generating unit further has:
一位址偏移值儲存單元以儲存該可更新的位址偏移值。An address offset value storage unit stores the updateable address offset value.
在一實施例中,數據邊界偵測電路,其中該邊界位址產生單元進一步具有:In one embodiment, the data boundary detection circuit, wherein the boundary address generating unit further has:
一第一多工器,用以自該邊界位址之所述目前值和所述先前值中擇一以產生該可更新的邊界位址;a first multiplexer for selecting one of the current value and the previous value of the boundary address to generate the updateable boundary address;
一第二多工器,用以自該差值之一目前值和一先前值中擇一以產生該可更新的位址偏移值;以及a second multiplexer for selecting one of a current value and a previous value of the difference to generate the updateable address offset value; and
一加法器,用以對該可更新的邊界位址及該可更新的位址偏移值進行一加法運算以產生該輸出邊界位址。An adder is used for performing an addition operation on the updateable boundary address and the updateable address offset value to generate the output boundary address.
為達到前述之目的,本發明進一步提出一種控制晶片,其具有一信號轉換單元及一數據邊界偵測電路,所述信號轉換單元係用以依多個C-PHY通道之傳輸信號產生輸入字符字節數據並將其傳送至該數據邊界偵測電路,且該數據邊界偵測電路具有:To achieve the above-mentioned purpose, the present invention further proposes a control chip, which has a signal conversion unit and a data boundary detection circuit, and the signal conversion unit is used to generate input character words according to the transmission signals of multiple C-PHY channels section data and transmit it to the data boundary detection circuit, and the data boundary detection circuit has:
一暫存單元,用以以移位的方式儲存多筆所述輸入字符字節數據,且其係依一輸出邊界位址選取兩筆連續的所述輸入字符字節數據以提供一筆輸出數據;以及A temporary storage unit is used to store multiple pieces of input character byte data in a shifted manner, and it selects two consecutive pieces of input character byte data according to an output boundary address to provide one piece of output data; as well as
一邊界位址產生單元,用以依一可更新的邊界位址及一可更新的位址偏移值之和產生該輸出邊界位址,其中,該可更新的邊界位址係由一筆同步用數據之一邊界字符在所述多筆輸入字符字節數據中出現之一邊界位址所更新,該可更新的位址偏移值係由該邊界位址之一目前值與一先前值之一差值所更新。A boundary address generating unit is used to generate the output boundary address according to the sum of an updateable boundary address and an updateable address offset value, wherein the updateable boundary address is generated by a synchronous A boundary character of the data is updated by a boundary address that appears in the multiple input character byte data, and the updateable address offset value is one of a current value and a previous value of the boundary address The difference is updated.
在一實施例中,該暫存單元具有:In one embodiment, the temporary storage unit has:
一移位暫存器,用以儲存所述多筆輸入字符字節數據;以及a shift register for storing the plurality of input character byte data; and
一控制電路,用以依該輸出邊界位址自該移位暫存器中讀取兩筆連續的所述輸入字符字節數據以提供所述輸出數據。A control circuit is used for reading two consecutive pieces of input character byte data from the shift register according to the output boundary address to provide the output data.
在一實施例中,該邊界位址產生單元具有:In one embodiment, the boundary address generating unit has:
一邊界偵測單元,用以依該移位暫存器之儲存內容偵測出該同步用數據之該邊界字符在一邊界範圍中之位置,並只在偵測出該邊界字符時才更新該可更新的邊界位址的內容。在一實施例中,該數據邊界偵測電路進一步具有:A boundary detection unit, used for detecting the position of the boundary character of the synchronization data in a boundary range according to the storage content of the shift register, and updating the boundary character only when the boundary character is detected The content of the updatable boundary address. In one embodiment, the data boundary detection circuit further has:
一輸出閘控單元,具有多個輸入端以耦接所述多個狀態信號,一輸出端以提供該輸出暫停信號,以及一反及閘以在所述多個狀態信號均為高電位時使該輸出暫停信號呈現低電位以致能所述多個先進先出暫存單元之數據輸出,及在所述多個狀態信號中有任一信號為低電位時使該輸出暫停信號呈現高電位以禁能所述多個先進先出暫存單元之所述數據輸出。An output gate control unit has a plurality of input terminals to couple the plurality of state signals, an output end to provide the output pause signal, and an inverting gate to enable the The output suspend signal presents a low potential to enable the data output of the plurality of FIFO temporary storage units, and when any signal in the plurality of status signals is low, the output suspend signal presents a high potential to disable The data output of the plurality of first-in-first-out temporary storage units can be performed.
在一實施例中,該邊界位址產生單元進一步具有: 一邊界位址儲存單元以儲存該可更新的邊界位址。 In one embodiment, the boundary address generating unit further has: A boundary address storage unit stores the updateable boundary address.
在一實施例中,該邊界位址產生單元進一步具有: 一位址偏移值儲存單元以儲存該可更新的位址偏移值。 In one embodiment, the boundary address generating unit further has: An address offset value storage unit stores the updateable address offset value.
在一實施例中,該邊界位址產生單元進一步具有:In one embodiment, the boundary address generating unit further has:
一第一多工器,用以自該邊界位址之所述目前值和所述先前值中擇一以產生該可更新的邊界位址;a first multiplexer for selecting one of the current value and the previous value of the boundary address to generate the updateable boundary address;
一第二多工器,用以自該差值之一目前值和一先前值中擇一以產生該可更新的位址偏移值;以及a second multiplexer for selecting one of a current value and a previous value of the difference to generate the updateable address offset value; and
一加法器,用以對該可更新的邊界位址及該可更新的位址偏移值進行一加法運算以產生該輸出邊界位址。An adder is used for performing an addition operation on the updateable boundary address and the updateable address offset value to generate the output boundary address.
為達到前述之目的,本發明進一步提出一種電子裝置,其具有一功能單元及如前述之控制晶片,且該功能單元包含一音頻功能單元及/或一視頻功能單元。In order to achieve the aforementioned object, the present invention further proposes an electronic device, which has a functional unit and the aforementioned control chip, and the functional unit includes an audio functional unit and/or a video functional unit.
在可能的實施例中,該電子裝置可為一顯示器、一攜帶型電腦或一智慧型手持裝置。In possible embodiments, the electronic device can be a display, a portable computer or a smart handheld device.
請參照圖2,其繪示包含本發明之數據邊界偵測電路之一實施例之電路圖。如圖2所示,一數據邊界偵測電路100包含一暫存單元110、一邊界偵測單元120、一邊界位址儲存單元130、一位址比較單元140、一位址偏移值儲存單元150、一第一多工器160、一第二多工器170及一加法器180。Please refer to FIG. 2 , which shows a circuit diagram including an embodiment of the data boundary detection circuit of the present invention. As shown in Figure 2, a data
暫存單元110具有一移位暫存器110a及一控制電路110b,其中,該移位暫存器110a具有三個14字符空間的儲存單元,用以以一次移動14字符的方式儲存各筆14字符的輸入數據SYMB
IN,例如,假設第一、二、三、四筆輸入的14字符SYMB
IN分別為S14
1、S14
2、S14
3、S14
4,則移位暫存器110a的儲存內容會以(14個空白字符, 14個空白字符, 14個空白字符)、(S14
1, 14個空白字符, 14個空白字符)、(S14
2, S14
1, 14個空白字符)、(S14
3, S14
2, S14
1) 、(S14
4, S14
3, S14
2)的方式變動;控制電路110b係用以依一輸出邊界位址BAOUT自移位暫存器110a之第1至42個字符空間中之第BAOUT+1至BAOUT+14個字符空間讀取14個字符以提供一筆14字符的輸出數據SYMB
OUT,其中,BAOUT為介於1至20之間的整數。
The
邊界偵測單元120係用以依該移位暫存器110a之儲存內容偵測出一7字符同步用數據之一邊界字符在1至20中之位置,並只在偵測出該邊界字符時產生一第一邊界位址BA1,且其方式為依該位置加1以決定一第一邊界位址BA1。例如,假設該7字符同步用數據為(3, 4, 4, 4, 4, 4, 3),該邊界字符為最左的字符3,而該邊界字符位在該移位暫存器110a之由左算起的第6個字符空間內,則該第一邊界位址BA1 = 6+1 = 7。The
邊界位址儲存單元130係用以儲存該第一邊界位址BA1以提供一第二邊界位址BA2,其中該第二邊界位址BA2代表該第一邊界位址BA1之一先前值,亦即,當邊界偵測單元120產生該第一邊界位址BA1時,邊界位址儲存單元130輸出的該第二邊界位址BA2係該第一邊界位址BA1的先前值。The boundary
位址比較單元140係用以產生一第一選擇信號SEL1,對該第一邊界位址BA1和該第二邊界位址BA2進行一差值運算以產生一第一位址差值DA1,及對該第一位址差值DA1和一第二位址差值DA2進行一比較運算以產生一第二選擇信號SEL2,其中,該第一選擇信號SEL1在初始時呈現一第一狀態,之後即呈現一第二狀態;該第二選擇信號SEL2在初始時呈現所述第一狀態,之後,則會在該第一位址差值DA1和該第二位址差值DA2相同時呈現所述第一狀態,相異時呈現所述第二狀態。The
位址偏移值儲存單元150係用以儲存該第一位址差值DA1以提供一第二位址差值DA2,其中該第二位址差值DA2代表該第一位址差值DA1之一先前值,亦即,當位址比較單元140產生該第一位址差值DA1時,位址偏移值儲存單元150輸出的該位址差值DA2係該第一位址差值DA1的先前值。The address offset
第一多工器160係用以依該第一選擇信號SEL1之控制選擇該第一邊界位址BA1或該第二邊界位址BA2以充作一邊界位址BA,其中,當該第一選擇信號SEL1呈現所述第一狀態時,第一多工器160選擇該第一邊界位址BA1;當該第一選擇信號SEL1呈現所述第二狀態時,第一多工器160選擇該第二邊界位址BA2。The
第二多工器170係用以依該第二選擇信號SEL2之控制選擇該第一位址差值DA1或該第二位址差值DA2以充作一位址差值DA,其中,當該第二選擇信號SEL2呈現所述第一狀態時,第二多工器170選擇該第二位址差值DA2;當該第二選擇信號SEL2呈現所述第二狀態時,第二多工器170選擇該第一位址差值DA1。The
加法器180係用以依該邊界位址BA與該位址差值DA之和產生該輸出邊界位址BAOUT。The
依上述的技術方案,本發明乃可有效解決C-PHY通信過程中字符(symbol)出錯造成的資料邊界丟失的問題。亦即,本發明藉由在一暫存單元中提供一量化的位址空間,即可以量化的方式反應一邊界字符的位置變動;以及藉由保留上一次的邊界字符的位址資訊,並將目前的邊界字符的位址資訊與上一次的邊界字符的位址資訊進行比較,本發明即可動態微調輸出數據邊界位址的位置,從而能快速回復到正確擷取輸入數據的狀態。在此要特別指出的是,在多C-PHY通道的數據傳輸過程中,若出現數據丟失的現象,整個並行數據便會產生偏移,進而導致後續的DSI-2解包失敗,而要解決這個問題,不能只依靠從頭尋找同步資訊,還須保留上一次的邊界資訊方能有效解決數據丟失所造成的錯位問題。According to the above technical solution, the present invention can effectively solve the problem of data boundary loss caused by symbol errors during C-PHY communication. That is to say, the present invention can reflect the position change of a boundary character in a quantitative manner by providing a quantized address space in a temporary storage unit; and by retaining the address information of the last boundary character, and By comparing the address information of the current boundary character with the address information of the last boundary character, the present invention can dynamically fine-tune the position of the boundary address of the output data, so as to quickly return to the state of correctly capturing the input data. It should be pointed out here that in the process of data transmission of multiple C-PHY channels, if data loss occurs, the entire parallel data will be offset, which will lead to subsequent DSI-2 unpacking failures. For this problem, we can not only rely on searching for synchronization information from the beginning, but also need to retain the last boundary information to effectively solve the misalignment problem caused by data loss.
依上述的說明,本發明進一步提出一控制晶片。請參照圖3,其繪示本發明之控制晶片之一實施例的方塊圖。如圖3所示,一控制晶片200具有三個信號轉換單元210及一數據邊界偵測電路220,其中,一信號轉換單元210係用以依三個C-PHY通道之傳輸信號(CPHY0、CPHY1、CPHY2)產生所述的14字符SYMB
IN以傳送至數據邊界偵測電路220,且數據邊界偵測電路220係由數據邊界偵測電路100實現。
According to the above description, the present invention further provides a control chip. Please refer to FIG. 3 , which shows a block diagram of an embodiment of the control chip of the present invention. As shown in FIG. 3, a
依上述的說明,本發明進一步提出一電子裝置。請參照圖4,其繪示本發明之電子裝置之一實施例的方塊圖。如圖4所示,一電子裝置300具有一控制晶片310及一功能單元320,其中,控制晶片310係由控制晶片200實現,且功能單元320可包含一音頻功能單元或一視頻功能單元。另外,電子裝置300可為一顯示器、一攜帶型電腦或一智慧型手持裝置。According to the above description, the present invention further provides an electronic device. Please refer to FIG. 4 , which shows a block diagram of an embodiment of the electronic device of the present invention. As shown in FIG. 4 , an
依上述的說明可知,本發明可提供以下的優點:According to the above description, the present invention can provide the following advantages:
1.本發明的數據邊界偵測電路可藉由定義一邊界地址範圍,及利用一簡潔的循序邏輯電路對一同步用數據的邊界字符出現在該邊界地址範圍內的前、後位置進行一邊界地址計算,而能快速恢復正確的數據擷取邊界以最小化數據損失。1. The data boundary detection circuit of the present invention can define a boundary address range, and utilize a simple sequential logic circuit to perform a boundary on the front and rear positions where the boundary character of a synchronization data appears in the boundary address range Address calculation, which can quickly restore the correct data capture boundary to minimize data loss.
2.本發明的控制晶片可藉由上述之數據邊界偵測電路快速恢復正確的數據擷取邊界以最小化數據損失。2. The control chip of the present invention can quickly restore the correct data capture boundary through the above-mentioned data boundary detection circuit to minimize data loss.
3.本發明的電子裝置可藉由上述之控制晶片快速恢復正確的數據擷取邊界以最小化數據損失。3. The electronic device of the present invention can quickly restore the correct data capture boundary through the above-mentioned control chip to minimize data loss.
本發明所揭示者,乃較佳實施例之一種,舉凡局部之變更或修飾而源於本發明之技術思想而為熟習該項技藝知人所易於推知者,俱不脫本發明之專利權範疇。What is disclosed in the present invention is one of the preferred embodiments. For example, all partial changes or modifications derived from the technical idea of the present invention and easily deduced by those skilled in the art do not depart from the scope of the patent right of the present invention.
綜上所陳,本案無論目的、手段與功效,皆顯示其迥異於習知技術,且其首先發明合於實用,確實符合發明之專利要件,懇請 貴審查委員明察,並早日賜予專利俾嘉惠社會,是為至禱。To sum up, regardless of the purpose, means and efficacy of this case, it shows that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. I implore your review committee to understand it clearly and grant a patent as soon as possible. Society is for the Most Prayer.
100:數據邊界偵測電路
110:暫存單元
110a:移位暫存器
110b:控制電路
120:邊界偵測單元
130:邊界位址儲存單元
140:位址比較單元
150:位址偏移值儲存單元
160:第一多工器
170:第二多工器
180:加法器
200:控制晶片
210:信號轉換單元
220:數據邊界偵測電路
300:電子裝置
310:控制晶片
320:功能單元100: Data boundary detection circuit
110:
為進一步揭示本發明之具體技術內容,首先請參閱圖式,其中: 圖1繪示在習知採用14字符的並行數據傳輸設計中,同步資訊可能存在高7字符中或低7字符中的示意圖。 圖2繪示包含本發明之數據邊界偵測電路之一實施例之電路圖。 圖3繪示本發明之控制晶片之一實施例的方塊圖。 圖4繪示本發明之電子裝置之一實施例的方塊圖。 In order to further disclose the specific technical content of the present invention, first please refer to the drawings, wherein: FIG. 1 is a schematic diagram showing that synchronization information may be stored in the upper 7 characters or the lower 7 characters in the conventional parallel data transmission design using 14 characters. FIG. 2 shows a circuit diagram of an embodiment of a data boundary detection circuit including the present invention. FIG. 3 shows a block diagram of an embodiment of the control chip of the present invention. FIG. 4 shows a block diagram of an embodiment of the electronic device of the present invention.
100:數據邊界偵測電路 100: Data boundary detection circuit
110:暫存單元 110: Temporary storage unit
110a:移位暫存器 110a: shift register
110b:控制電路 110b: control circuit
120:邊界偵測單元 120: Boundary detection unit
130:邊界位址儲存單元 130: boundary address storage unit
140:位址比較單元 140: address comparison unit
150:位址偏移值儲存單元 150: Address offset value storage unit
160:第一多工器 160: The first multiplexer
170:第二多工器 170: Second multiplexer
180:加法器 180: Adder
Claims (14)
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TW200616400A (en) * | 2004-03-16 | 2006-05-16 | Michael L Fowler | Bit clock with embedded word clock boundary |
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