TWI675273B - Voltage boosting circuit, output buffer circuit and display panel - Google Patents
Voltage boosting circuit, output buffer circuit and display panel Download PDFInfo
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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Abstract
提供一種升壓電路，至少包括位準移位電路與輸出緩衝電路。位準移位電路接收輸入電壓脈衝以提供平移後的第一電壓脈衝、第二電壓脈衝與第三電壓脈衝至輸出緩衝電路。輸出緩衝電路包括緩衝電路與偏壓電路。緩衝電路包括串聯於系統高電壓與輸出端點之間的K個P型電晶體與串聯於輸出端點與系統低電壓之間的K個N型電晶體，K是大於或等於5的整數。偏壓電路根據第二電壓脈衝提供多個動態偏壓以控制緩衝電路中的部分電晶體，並且包括耦接第1個第一P型電晶體的控制端與第1個第一N型電晶體的控制端的第一電容。一種顯示面板亦被提供。A boost circuit is provided, which includes at least a level shift circuit and an output buffer circuit. The level shift circuit receives an input voltage pulse to provide a first voltage pulse, a second voltage pulse, and a third voltage pulse after translation to the output buffer circuit. The output buffer circuit includes a buffer circuit and a bias circuit. The buffer circuit includes K P-type transistors connected in series between the high voltage of the system and the output terminal, and K N-type transistors connected in series between the output terminal and the low voltage of the system, where K is an integer greater than or equal to 5. The bias circuit provides a plurality of dynamic biases according to the second voltage pulse to control a part of the transistors in the buffer circuit, and includes a control terminal coupled to the first first P-type transistor and the first first N-type transistor. The first capacitor of the control terminal of the crystal. A display panel is also provided.
Description
本發明是有關於一種電子電路，且特別是有關於一種升壓電路、輸出緩衝電路與顯示面板。The invention relates to an electronic circuit, and in particular to a boost circuit, an output buffer circuit and a display panel.
現有電子裝置的電路常常會需要使用不同的工作電壓範圍，因此需要升壓電路將低位準的電壓信號轉換成具有高位準的電壓信號以驅動其他電路。舉例來說，具有省電、開關速度快的發光二極體(Light Emitting Diode, LED)開始應用到平面顯示器上，發光二極體的驅動電路就會需要使用升壓電路提供高位準電壓信號。Circuits of existing electronic devices often need to use different operating voltage ranges, so a boost circuit is required to convert a low-level voltage signal into a high-level voltage signal to drive other circuits. For example, a light-emitting diode (Light Emitting Diode, LED) with power saving and fast switching speed is beginning to be applied to a flat display, and the driving circuit of the light-emitting diode will need a boost circuit to provide a high-level voltage signal.
因為輸出電壓信號會在高位準跟低位準之間切換，現有的升壓電路可能會有訊號轉態太慢或是消耗功率太大的問題，或者是晶片面積過大或成本過高等其他問題，因此如何提供一種能夠在高低位準間快速切換、面積微小化並且節約功耗與成本的升壓電路成為本領域技術人員重要的課題之一。Because the output voltage signal will switch between high and low levels, the existing booster circuit may have problems such as slow signal transition or excessive power consumption, or other problems such as excessive chip area or high cost. How to provide a boost circuit capable of quickly switching between high and low levels, miniaturizing area, and saving power consumption and cost has become one of the important topics for those skilled in the art.
本發明提供一種升壓電路、輸出緩衝電路與顯示面板，升壓電路或輸出緩衝電路可以應用於顯示面板的驅動電路，並具有電路面積微小化、全幅輸出、位準切換快速以及運作穩定的優點。The invention provides a booster circuit, an output buffer circuit and a display panel. The booster circuit or the output buffer circuit can be applied to a drive circuit of a display panel, and has the advantages of minimizing circuit area, full-scale output, fast level switching, and stable operation. .
本發明的實施例提供一種升壓電路，用以接收輸入電壓脈衝以在輸出端點提供輸出電壓脈衝。升壓電路包括位準移位電路與輸出緩衝電路。位準移位電路接收輸入電壓脈衝以提供平移後的第一電壓脈衝、第二電壓脈衝與第三電壓脈衝。輸出緩衝電路，包括緩衝電路與偏壓電路。緩衝電路包括串聯於系統高電壓與輸出端點之間的K個P型電晶體與串聯於輸出端點與系統低電壓之間的K個N型電晶體，K是大於或等於5的整數。第K個第一P型電晶體受控於第一電壓脈衝且第K個第一N型電晶體受控於第三電壓脈衝，其中第i個第一P型電晶體與第i個第一N型電晶體表示K個第一P型電晶體與K個第一N型電晶體中的電晶體相對於輸出端點的順序，i為1至K的整數且i愈小表示電晶體愈靠近輸出端點。偏壓電路電性連接於緩衝電路與位準移位電路之間。偏壓電路根據第二電壓脈衝提供多個動態偏壓至緩衝電路，K個第一P型電晶體與K個第一N型電晶體中的部分電晶體受控於這些動態偏壓，且偏壓電路包括耦接第1個第一P型電晶體的控制端與第1個第一N型電晶體的控制端的第一電容。An embodiment of the present invention provides a boost circuit for receiving an input voltage pulse to provide an output voltage pulse at an output terminal. The boost circuit includes a level shift circuit and an output buffer circuit. The level shift circuit receives an input voltage pulse to provide a first voltage pulse, a second voltage pulse, and a third voltage pulse after translation. The output buffer circuit includes a buffer circuit and a bias circuit. The buffer circuit includes K P-type transistors connected in series between the high voltage of the system and the output terminal, and K N-type transistors connected in series between the output terminal and the low voltage of the system, where K is an integer greater than or equal to 5. The K-th first P-type transistor is controlled by a first voltage pulse and the K-th first N-type transistor is controlled by a third voltage pulse, wherein the i-th first P-type transistor and the i-th first The N-type transistor indicates the order of the transistors in the K first P-type transistors and the K first N-type transistors with respect to the output terminals. I is an integer from 1 to K, and the smaller i is, the closer the transistor is. Output endpoint. The bias circuit is electrically connected between the buffer circuit and the level shift circuit. The bias circuit provides a plurality of dynamic bias voltages to the buffer circuit according to the second voltage pulse. Some of the K first P-type transistors and the K first N-type transistors are controlled by these dynamic bias voltages, and The bias circuit includes a first capacitor coupled to the control terminal of the first first P-type transistor and the control terminal of the first first N-type transistor.
在本發明的一實施例中，上述的升壓電路中的偏壓電路還包括電性連接位準移位電路的第一開關與電性連接第一開關與緩衝電路的第二開關。第一開關根據第二電壓脈衝選擇提供第一內部偏壓或第二內部偏壓至第二開關。第二開關受控於第一節點上的電壓以提供第一開關的輸出至第二節點或第三節點，其中，第一節點耦接第1個第一P型電晶體與第1個第一N型電晶體的控制端，第二節點耦接第2個第一N型電晶體的控制端，第三節點耦接第2個第一P型電晶體的控制端。In an embodiment of the present invention, the bias circuit in the booster circuit further includes a first switch electrically connected to the level shift circuit and a second switch electrically connected to the first switch and the buffer circuit. The first switch selects to provide the first internal bias voltage or the second internal bias voltage to the second switch according to the second voltage pulse. The second switch is controlled by the voltage on the first node to provide the output of the first switch to the second node or the third node, wherein the first node is coupled to the first first P-type transistor and the first first The control node of the N-type transistor, the second node is coupled to the control terminal of the second first N-type transistor, and the third node is coupled to the control terminal of the second first P-type transistor.
在本發明的一實施例中，在上述的升壓電路中，當第一開關提供第二內部偏壓至第二開關時，第二開關相應地提供第二內部偏壓作為這些動態偏壓的其中之一至第三節點，以及當第一開關提供第一內部偏壓至第二開關時，第二開關相應地提供第一內部偏壓作為這些動態偏壓的其中之一至第二節點。In an embodiment of the present invention, in the above-mentioned boosting circuit, when the first switch provides a second internal bias voltage to the second switch, the second switch correspondingly provides a second internal bias voltage as the dynamic bias voltage. One of them to the third node, and when the first switch provides the first internal bias to the second switch, the second switch accordingly provides the first internal bias as one of these dynamic biases to the second node.
在本發明的一實施例中，在上述的升壓電路中，偏壓電路還包括（K-2）個第二N型電晶體、（K-2）個第二P型電晶體、第三P型電晶體與第三N型電晶體。（K-2）個第二N型電晶體串聯於第（K-1）個P型電晶體的控制端與第一節點之間，其中第j個第二N型電晶體的兩端分別耦接第j個第一P型電晶體的控制端與第（j+1）個第一P型電晶體的控制端，且第j個第二N型電晶體的控制端耦接第j個第一P型電晶體的第一端與第（j+1）個第一P型電晶體的第二端。（K-2）個第二P型電晶體串聯於第一節點與第（K-1）個N型電晶體的控制端之間，其中第j個第二P型電晶體的兩端分別耦接第j個第一N型電晶體的控制端與第（j+1）個第一N型電晶體的控制端，且第j個第二P型電晶體的控制端耦接第j個第一N型電晶體的第二端與第（j+1）個第一N型電晶體的第一端，其中第j個第二P型電晶體與第j個第二N型電晶體表示（K-2）個第二P型電晶體與（K-2）個第二N型電晶體中的電晶體相對於第一節點的順序，j為1至（K-2）的整數且j愈小表示電晶體愈靠近第一節點。第三P型電晶體的控制端耦接第三節點，其兩端分別耦接第一內部偏壓與第3個第一P型電晶體的控制端。第三N型電晶體的控制端耦接第二節點，其兩端分別耦接第二內部偏壓與第3個第一N型電晶體的控制端。In an embodiment of the present invention, in the above-mentioned booster circuit, the bias circuit further includes (K-2) second N-type transistors, (K-2) second P-type transistors, Three P-type transistors and a third N-type transistor. The (K-2) second N-type transistor is connected in series between the control terminal of the (K-1) P-type transistor and the first node, and the two ends of the j-th second N-type transistor are respectively coupled The control terminal of the j-th first P-type transistor is connected to the control terminal of the (j + 1) th first P-type transistor, and the control terminal of the j-th second N-type transistor is coupled to the j-th The first end of a P-type transistor and the second end of the (j + 1) th first P-type transistor. (K-2) second P-type transistors are connected in series between the first node and the control terminal of the (K-1) th N-type transistor, where both ends of the j-th second P-type transistor are respectively coupled The control terminal of the j-th first N-type transistor is connected to the control terminal of the (j + 1) th first N-type transistor, and the control terminal of the j-th second P-type transistor is coupled to the j-th The second end of an N-type transistor and the first end of the (j + 1) th first N-type transistor, where the j-th second P-type transistor and the j-th second N-type transistor are represented ( K-2) The order of the transistors in the second P-type transistor and the (K-2) second N-type transistor relative to the first node, j is an integer from 1 to (K-2) and j is greater Small means that the transistor is closer to the first node. The control terminal of the third P-type transistor is coupled to the third node, and its two ends are respectively coupled to the first internal bias voltage and the control terminal of the third first P-type transistor. The control terminal of the third N-type transistor is coupled to the second node, and its two ends are respectively coupled to the second internal bias voltage and the control terminal of the third first N-type transistor.
在本發明的一實施例中，在上述的升壓電路中，第一開關包括第四P型電晶體與一第四N型電晶體。第四P型電晶體的第一端耦接第一內部偏壓，第二端耦接第四N型電晶體的第一端，第四N型電晶體的第二端耦接第二內部偏壓，並且第四P型電晶體與第四N型電晶體的控制端共同接收第二電壓脈衝。第二開關包括第五P型電晶體與第五N型電晶體。第五P型電晶體的一端耦接第三節點，另一端耦接第五N型電晶體的一端、第四P型電晶體的第二端與第四N型電晶體的第一端，以及第五N型電晶體的另一端耦接第二節點，並且第五P型電晶體與第五N型電晶體的控制端共同耦接第一節點。In an embodiment of the present invention, in the above-mentioned booster circuit, the first switch includes a fourth P-type transistor and a fourth N-type transistor. The first terminal of the fourth P-type transistor is coupled to the first internal bias, the second terminal is coupled to the first terminal of the fourth N-type transistor, and the second terminal of the fourth N-type transistor is coupled to the second internal bias. And the control terminals of the fourth P-type transistor and the fourth N-type transistor jointly receive the second voltage pulse. The second switch includes a fifth P-type transistor and a fifth N-type transistor. One end of the fifth P-type transistor is coupled to the third node, and the other end is coupled to one end of the fifth N-type transistor, the second end of the fourth P-type transistor and the first end of the fourth N-type transistor, and The other end of the fifth N-type transistor is coupled to the second node, and the fifth P-type transistor and the control terminal of the fifth N-type transistor are commonly coupled to the first node.
在本發明的一實施例中，在上述的升壓電路中，當（K-2）個第二P型電晶體被導通時，第二節點的位準被下拉以截止第三N型電晶體，第一節點的位準被下拉以截止第五N型電晶體並導通第五P型電晶體，其中第四P型電晶體被截止且第四N型電晶體被導通使得第二內部偏壓被提供至第三節點。In an embodiment of the present invention, in the above-mentioned booster circuit, when (K-2) second P-type transistors are turned on, the level of the second node is pulled down to cut off the third N-type transistor. The level of the first node is pulled down to turn off the fifth N-type transistor and turn on the fifth P-type transistor, wherein the fourth P-type transistor is turned off and the fourth N-type transistor is turned on so that the second internal bias voltage Is provided to the third node.
在本發明的一實施例中，在上述的升壓電路中，當（K-2）個第二N型電晶體被導通時，第三節點的位準被上拉以截止第三P型電晶體，第一節點的位準被上拉以導通第五N型電晶體並截止第五P型電晶體，其中第四P型電晶體被導通且第四N型電晶體被截止使得第一內部偏壓被提供至第二節點。In an embodiment of the present invention, in the above-mentioned booster circuit, when (K-2) second N-type transistors are turned on, the level of the third node is pulled up to cut off the third P-type transistor. Crystal, the level of the first node is pulled up to turn on the fifth N-type transistor and turn off the fifth P-type transistor, where the fourth P-type transistor is turned on and the fourth N-type transistor is turned off so that the first internal A bias is provided to the second node.
在本發明的一實施例中，在上述的升壓電路中，輸入電壓脈衝的高位準是VDD，系統高電壓的位準是K*VDD，K個第一P型電晶體與K個第一N型電晶體中的部分電晶體受控於多個內部偏壓，這些內部偏壓包括第一內部偏壓與第二內部偏壓，第一內部偏壓為（K+1）*VDD/2，第二內部偏壓為（K-1）*VDD/2。其中當K=5時，第一內部偏壓的位準是3*VDD，第二內部偏壓的位準是2*VDD，其中第4個第一P型電晶體的控制端接收位準是4*VDD的內部偏壓，並且第4個第一N型電晶體的控制端接收位準是VDD的內部偏壓。In an embodiment of the present invention, in the above-mentioned booster circuit, the high level of the input voltage pulse is VDD, the high voltage level of the system is K * VDD, K first P-type transistors and K first Some transistors in N-type transistors are controlled by multiple internal biases. These internal biases include a first internal bias and a second internal bias. The first internal bias is (K + 1) * VDD / 2 , The second internal bias voltage is (K-1) * VDD / 2. When K = 5, the level of the first internal bias is 3 * VDD, the level of the second internal bias is 2 * VDD, and the receiving level of the control end of the fourth first P-type transistor is 4 * VDD internal bias, and the control terminal receiving level of the fourth first N-type transistor is the internal bias of VDD.
在本發明的一實施例中，在上述的升壓電路還包括耦接系統高電壓的偏壓產生電路。偏壓產生電路包括多個分壓電晶體與多個第二電容。多個分壓電晶體以串聯的形式耦接於系統高電壓與系統低電壓之間，且相鄰的這些分壓電晶體之間具有一分壓節點以提供這些內部偏壓的其中之一。多個第二電容耦接這些分壓節點且與對應的分壓電晶體並聯。In an embodiment of the present invention, the booster circuit further includes a bias voltage generating circuit coupled to a high voltage of the system. The bias generating circuit includes a plurality of piezoelectric sub-crystals and a plurality of second capacitors. A plurality of partial piezoelectric crystals are coupled in series between the high voltage of the system and the low voltage of the system, and a voltage dividing node is provided between the adjacent partial piezoelectric crystals to provide one of these internal bias voltages. A plurality of second capacitors are coupled to the voltage dividing nodes and are connected in parallel with the corresponding voltage dividing crystals.
在本發明的一實施例中，在上述的升壓電路中，輸入電壓脈衝的高位準是VDD，系統高電壓的位準是K*VDD，第一電壓脈衝的高位準是K*VDD，第二電壓脈衝的高位準是（K+1）*VDD/2，以及第三電壓脈衝的高位準是VDD，其中第一電壓脈衝、第二電壓脈衝以及第三電壓脈衝與輸入電壓脈衝的相位實質上相反。In an embodiment of the present invention, in the above-mentioned booster circuit, the high level of the input voltage pulse is VDD, the high voltage level of the system is K * VDD, and the high level of the first voltage pulse is K * VDD. The high level of the two voltage pulses is (K + 1) * VDD / 2, and the high level of the third voltage pulse is VDD. The phases of the first voltage pulse, the second voltage pulse, and the third voltage pulse and the input voltage pulse are substantially On the contrary.
在本發明的一實施例中，在上述的升壓電路中，第一電壓脈衝、第二電壓脈衝以及第三電壓脈衝與輸入電壓脈衝的脈衝高度實質上相同。In an embodiment of the present invention, in the above-mentioned booster circuit, the pulse heights of the first voltage pulse, the second voltage pulse, and the third voltage pulse and the input voltage pulse are substantially the same.
本發明的實施例提供一種輸出緩衝電路，包括緩衝電路與偏壓電路。緩衝電路包括串聯於系統高電壓與輸出端點之間的K個P型電晶體與串聯於輸出端點與系統低電壓之間的K個N型電晶體，K是大於或等於5的整數。第K個第一P型電晶體受控於第一電壓脈衝且第K個第一N型電晶體受控於第三電壓脈衝，其中第i個第一P型電晶體與第i個第一N型電晶體表示K個第一P型電晶體與K個第一N型電晶體中的電晶體相對於輸出端點的順序，i為1至K的整數且i愈小表示電晶體愈靠近輸出端點。偏壓電路接收第二電壓脈衝且電性連接於緩衝電路，其中，偏壓電路根據第二電壓脈衝提供多個動態偏壓至緩衝電路。偏壓電路包括耦接第1個第一P型電晶體的控制端與第1個第一N型電晶體的控制端的第一電容。K個第一P型電晶體與K個第一N型電晶體中的部分電晶體受控於這些動態偏壓，且第二電壓脈衝的位準大於第三電壓脈衝且小於第一電壓脈衝。An embodiment of the present invention provides an output buffer circuit including a buffer circuit and a bias circuit. The buffer circuit includes K P-type transistors connected in series between the high voltage of the system and the output terminal, and K N-type transistors connected in series between the output terminal and the low voltage of the system, where K is an integer greater than or equal to 5. The K-th first P-type transistor is controlled by a first voltage pulse and the K-th first N-type transistor is controlled by a third voltage pulse, wherein the i-th first P-type transistor and the i-th first The N-type transistor indicates the order of the transistors in the K first P-type transistors and the K first N-type transistors with respect to the output terminals. I is an integer from 1 to K, and the smaller i is, the closer the transistor is. Output endpoint. The bias circuit receives a second voltage pulse and is electrically connected to the buffer circuit, wherein the bias circuit provides a plurality of dynamic bias voltages to the buffer circuit according to the second voltage pulse. The bias circuit includes a first capacitor coupled to the control terminal of the first first P-type transistor and the control terminal of the first first N-type transistor. Some of the K first P-type transistors and the K first N-type transistors are controlled by these dynamic biases, and the level of the second voltage pulse is greater than the third voltage pulse and smaller than the first voltage pulse.
本發明的實施例提供一種顯示面板，包括上述的升壓電路。閘極驅動器接收由升壓電路提供的輸出電壓脈衝且提供多個閘極信號。多個畫素耦接多條掃描線以接收對應的閘極信號。An embodiment of the present invention provides a display panel including the above-mentioned booster circuit. The gate driver receives the output voltage pulse provided by the boost circuit and provides a plurality of gate signals. Multiple pixels are coupled to multiple scan lines to receive corresponding gate signals.
基於上述，本發明提供一種升壓電路、輸出緩衝電路與顯示面板。升壓電路可以應用於顯示面板並且包括輸出緩衝電路。輸出緩衝電路包括緩衝電路與偏壓電路，且從位準移位電路接收有關於輸入電壓脈衝的第一電壓脈衝、第二電壓脈衝與第三電壓脈衝。緩衝電路包括串聯於系統高電壓與輸出端點之間的K個第一P型電晶體以及串聯於輸出端點與系統低電壓之間的K個第一N型電晶體。第K個第一P型電晶體受控於第一電壓脈衝且第K個第一N型電晶體受控於第三電壓脈衝。偏壓電路根據第二電壓脈衝提供多個動態偏壓至緩衝電路中其他部分電晶體的控制端。藉由偏壓電路提供的動態分壓來精準控制緩衝電路中的電晶體的控制端的位準，能夠使緩衝電路中的電晶體運作穩定，並且實現一階段式的位準切換。偏壓電路包括耦接第1個第一P型電晶體的控制端與第1個第一N型電晶體的控制端的第一電容，能夠提升輸出電壓脈衝的信號切換速度。Based on the above, the present invention provides a booster circuit, an output buffer circuit, and a display panel. The boost circuit can be applied to a display panel and includes an output buffer circuit. The output buffer circuit includes a buffer circuit and a bias circuit, and receives a first voltage pulse, a second voltage pulse, and a third voltage pulse regarding the input voltage pulse from the level shift circuit. The buffer circuit includes K first P-type transistors connected in series between the high voltage of the system and the output terminal, and K first N-type transistors connected in series between the output terminal and the low voltage of the system. The K-th first P-type transistor is controlled by a first voltage pulse and the K-th first N-type transistor is controlled by a third voltage pulse. The bias circuit provides a plurality of dynamic bias voltages to the control terminals of other transistors in the buffer circuit according to the second voltage pulse. By accurately controlling the level of the control terminal of the transistor in the buffer circuit through the dynamic voltage division provided by the bias circuit, the transistor in the buffer circuit can operate stably and realize a one-stage level switching. The bias circuit includes a first capacitor coupled to the control terminal of the first first P-type transistor and the control terminal of the first first N-type transistor, which can improve the signal switching speed of the output voltage pulse.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.
圖1是依照本發明的一實施例的一種顯示面板的示意圖。請參照圖1，在本實施例中，顯示面板10包括升壓電路100、閘極驅動器200、多條掃描線SL以及多個畫素PX。升壓電路100接收輸入電壓脈衝VIN以提供輸出電壓脈衝VOUT給閘極驅動器200。輸出電壓脈衝VOUT例如是輸入電壓脈衝VIN的升壓後的電壓脈衝，輸入電壓脈衝VIN具有較低的位準，例如VDD，輸出電壓脈衝VOUT則具有較高的位準，例如5VDD。閘極驅動器200接收輸出電壓脈衝VOUT並提供多個閘極信號GS。這些畫素PX成陣列排列且分別耦接掃描線SL與資料線（圖中未顯示）。這些畫素PX會通過掃描線SL接收閘極信號GS以及通過資料線接收畫素電壓。FIG. 1 is a schematic diagram of a display panel according to an embodiment of the invention. Referring to FIG. 1, in this embodiment, the display panel 10 includes a boost circuit 100, a gate driver 200, a plurality of scan lines SL, and a plurality of pixels PX. The boost circuit 100 receives an input voltage pulse VIN to provide an output voltage pulse VOUT to the gate driver 200. The output voltage pulse VOUT is, for example, a boosted voltage pulse of the input voltage pulse VIN. The input voltage pulse VIN has a lower level, such as VDD, and the output voltage pulse VOUT has a higher level, such as 5VDD. The gate driver 200 receives the output voltage pulse VOUT and provides a plurality of gate signals GS. These pixels PX are arranged in an array and are respectively coupled to the scan lines SL and the data lines (not shown in the figure). These pixels PX receive the gate signal GS through the scan line SL and the pixel voltage through the data line.
在本實施例中，顯示面板10可以是micro-LED顯示面板或是液晶顯示面板，本發明並不限制。另外，升壓電路100也可以應用在其他電子裝置中，本發明不限制升壓電路100的用處。In this embodiment, the display panel 10 may be a micro-LED display panel or a liquid crystal display panel, and the present invention is not limited thereto. In addition, the booster circuit 100 can also be applied to other electronic devices, and the present invention does not limit the usefulness of the booster circuit 100.
圖2是依照本發明的一實施例的一種升壓電路的電路示意圖。請參照圖2，升壓電路100用以接收輸入電壓脈衝VIN以在輸出端點OUT提供輸出電壓脈衝VOUT。升壓電路100至少包括位準移位電路110與輸出緩衝電路150，其中輸出緩衝電路150包括緩衝電路120以及偏壓電路130。FIG. 2 is a circuit diagram of a booster circuit according to an embodiment of the present invention. Referring to FIG. 2, the boost circuit 100 is used to receive an input voltage pulse VIN to provide an output voltage pulse VOUT at an output terminal OUT. The boost circuit 100 includes at least a level shift circuit 110 and an output buffer circuit 150. The output buffer circuit 150 includes a buffer circuit 120 and a bias circuit 130.
位準移位電路110接收輸入電壓脈衝VIN以輸出平移後的第一電壓脈衝VO1、第二電壓脈衝VO2與第三電壓脈衝VO3至輸出緩衝電路150。位準移位電路110提供第一電壓脈衝VO1與第三電壓脈衝VO3給緩衝電路120。位準移位電路110提供第二電壓脈衝VO2給偏壓電路130。The level shift circuit 110 receives the input voltage pulse VIN to output the first voltage pulse VO1, the second voltage pulse VO2, and the third voltage pulse VO3 after translation to the output buffer circuit 150. The level shift circuit 110 provides a first voltage pulse VO1 and a third voltage pulse VO3 to the buffer circuit 120. The level shift circuit 110 provides a second voltage pulse VO2 to the bias circuit 130.
緩衝電路120包括K個第一P型電晶體與K個第一N型電晶體，K是大於或等於5的整數。在圖2的實施例中K被設定為5，緩衝電路120包括5個第一P型電晶體TP1～TP5與5個第一N型電晶體TN1～TN5。第一P型電晶體TP1～TP5串聯於系統高電壓與輸出端點OUT之間，系統高電壓的位準是K倍VDD（以K*VDD或KVDD表示），在圖2中是5VDD。第一N型電晶體TN1～TN5串聯於輸出端點OUT與系統低電壓VSS之間，系統低電壓VSS例如是接地端，或稱零位準參考端。The buffer circuit 120 includes K first P-type transistors and K first N-type transistors, where K is an integer greater than or equal to 5. In the embodiment of FIG. 2, K is set to 5, and the buffer circuit 120 includes five first P-type transistors TP1 to TP5 and five first N-type transistors TN1 to TN5. The first P-type transistors TP1 to TP5 are connected in series between the high voltage of the system and the output terminal OUT. The level of the high voltage of the system is K times VDD (represented by K * VDD or KVDD), which is 5VDD in FIG. 2. The first N-type transistors TN1 to TN5 are connected in series between the output terminal OUT and the system low voltage VSS. The system low voltage VSS is, for example, a ground terminal or a zero reference terminal.
偏壓電路130電性連接於緩衝電路120與位準移位電路110之間。偏壓電路130根據第二電壓脈衝VO2提供多個動態偏壓至緩衝電路120，第一P型電晶體TP1～TP5與第一N型電晶體TN1～TN5中的部分電晶體會受控於這些動態偏壓。The bias circuit 130 is electrically connected between the buffer circuit 120 and the level shift circuit 110. The bias circuit 130 provides a plurality of dynamic bias voltages to the buffer circuit 120 according to the second voltage pulse VO2. Some of the first P-type transistors TP1 to TP5 and the first N-type transistors TN1 to TN5 are controlled by These dynamic biases.
詳細來說，前3個第一P型電晶體TP1～TP3與前3個第一N型電晶體TN1～TN3的控制端（閘極）接收來自偏壓電路130的動態偏壓，第4個第一P型電晶體TP4與第4個第一N型電晶體TN4則分別接收固定的偏壓4VDD與VDD，第5個第一P型電晶體TP5則受控於第一電壓脈衝VO1，第5個第一N型電晶體TN5受控於第三電壓脈衝VO3。本說明書中所述的第i個第一P型電晶體與第i個第一N型電晶體是指這些第一P型電晶體TP1～TP5與這些第一N型電晶體TN1～TN5中的電晶體相對於輸出端點OUT的順序，i為1至K（K=5）的整數且i愈小表示電晶體愈靠近輸出端點。In detail, the control terminals (gates) of the first three first P-type transistors TP1 to TP3 and the first three first N-type transistors TN1 to TN3 receive dynamic bias from the bias circuit 130, and the fourth The first first P-type transistor TP4 and the fourth first N-type transistor TN4 receive fixed bias voltages 4VDD and VDD, respectively. The fifth first P-type transistor TP5 is controlled by the first voltage pulse VO1. The fifth first N-type transistor TN5 is controlled by a third voltage pulse VO3. The i-th first P-type transistor and the i-th first N-type transistor in this description refer to the first P-type transistor TP1 to TP5 and the first N-type transistor TN1 to TN5. The order of the transistor relative to the output terminal OUT, i is an integer from 1 to K (K = 5) and the smaller i is, the closer the transistor is to the output terminal.
根據第一電壓脈衝VO1、第三電壓脈衝VO3與來自偏壓電路130的這些動態偏壓，第一P型電晶體TP1～TP5被截止且第一N型電晶體TN1～TN5被導通或者第一P型電晶體TP1～TP5被導通且第一N型電晶體TN1～TN5被截止以輸出具有不同位準的輸出電壓脈衝VOUT。According to the first voltage pulse VO1, the third voltage pulse VO3 and these dynamic biases from the bias circuit 130, the first P-type transistors TP1 to TP5 are turned off and the first N-type transistors TN1 to TN5 are turned on or the first A P-type transistors TP1 to TP5 are turned on and the first N-type transistors TN1 to TN5 are turned off to output output voltage pulses VOUT having different levels.
偏壓電路130包括第一電容CF。第一電容CF的一端耦接第1個第一P型電晶體TP1的控制端與第1個第一N型電晶體TN1的控制端，且另一端耦接第2個第一N型電晶體TN2的控制端。在本實施例中，第一電容CF的電容值例如是110fF（皮法拉）。設置第一電容CF可以加速輸出電壓脈衝VOUT的信號上升（rising）速度與下降（falling）速度。The bias circuit 130 includes a first capacitor CF. One end of the first capacitor CF is coupled to the control end of the first first P-type transistor TP1 and the control end of the first first N-type transistor TN1, and the other end is coupled to the second first N-type transistor. Control terminal of TN2. In this embodiment, the capacitance value of the first capacitor CF is, for example, 110 fF (picofarad). Setting the first capacitor CF can accelerate the rising speed and falling speed of the signal of the output voltage pulse VOUT.
圖3是依照本發明的一實施例的一種升壓電路的信號波形圖。請參照圖3，在本實施例中，輸入電壓脈衝VIN的高位準是VDD，低位準是系統低電壓VSS，例如0V（伏特），經過位準移位電路110平移後的第一電壓脈衝VO1的高位準是K倍VDD，低位準是（K-1）倍VDD。第二電壓脈衝VO2的高位準是（K+1）/2*VDD，低位準是（K-1）/2*VDD，第三電壓脈衝VO3是輸入電壓脈衝VIN的反相信號，其電壓位準則維持不變，高位準同樣是VDD，低位準同樣是0V。具體而言，第一電壓脈衝VO1、第二電壓脈衝VO2以及第三電壓脈衝VO3都跟輸入電壓脈衝VIN的相位實質上相反，但脈衝振幅實質上相同。FIG. 3 is a signal waveform diagram of a booster circuit according to an embodiment of the present invention. Referring to FIG. 3, in this embodiment, the high level of the input voltage pulse VIN is VDD, and the low level is the system low voltage VSS, such as 0V (volt). The first voltage pulse VO1 is translated by the level shift circuit 110. The high level is K times VDD, and the low level is (K-1) times VDD. The high level of the second voltage pulse VO2 is (K + 1) / 2 * VDD, the low level is (K-1) / 2 * VDD, and the third voltage pulse VO3 is the inverted signal of the input voltage pulse VIN, and its voltage level The guidelines remain the same, the high level is also VDD, and the low level is also 0V. Specifically, the phases of the first voltage pulse VO1, the second voltage pulse VO2, and the third voltage pulse VO3 are substantially opposite to the input voltage pulse VIN, but the pulse amplitudes are substantially the same.
在圖2的實施例中，K=5，系統低電壓VSS是0V，輸入電壓脈衝VIN的位準是0V～VDD，第一電壓脈衝VO1的位準是5VDD～4VDD，第二電壓脈衝VO2的位準是3VDD～2VDD，第二電壓脈衝VO1的位準是VDD～0V，升壓電路100所提供的輸出電壓脈衝VOUT的位準是0V～5VDD。In the embodiment of FIG. 2, K = 5, the system low voltage VSS is 0V, the level of the input voltage pulse VIN is 0V to VDD, the level of the first voltage pulse VO1 is 5VDD to 4VDD, and the level of the second voltage pulse VO2 is The level is 3VDD to 2VDD, the level of the second voltage pulse VO1 is VDD to 0V, and the level of the output voltage pulse VOUT provided by the booster circuit 100 is 0V to 5VDD.
簡言之，第一電壓脈衝VO1、第二電壓脈衝VO2與第三電壓脈衝VO3的位準變化是隨著輸入電壓脈衝VIN連動，升壓電路100的偏壓電路130可以根據第二電壓脈衝VO2的位準變化相應地提供動態偏壓給緩衝電路120，以搭配第一電壓脈衝VO1與第三電壓脈衝VO3來控制緩衝電路120中電晶體的開關，進而在輸出端點OUT提供具有全幅輸出的輸出電壓脈衝VOUT。In short, the level changes of the first voltage pulse VO1, the second voltage pulse VO2, and the third voltage pulse VO3 are linked with the input voltage pulse VIN. The bias circuit 130 of the boost circuit 100 may The level change of VO2 accordingly provides a dynamic bias voltage to the buffer circuit 120 to match the first voltage pulse VO1 and the third voltage pulse VO3 to control the switching of the transistor in the buffer circuit 120, thereby providing a full-scale output at the output terminal OUT. The output voltage pulse VOUT.
下面更進一步說明本實施例的升壓電路100的電路架構。The circuit architecture of the booster circuit 100 of this embodiment is further described below.
在本實施例中，升壓電路100還包括偏壓產生電路140。偏壓產生電路140耦接於系統高電壓5VDD與系統低電壓VSS之間。偏壓產生電路140包括多個分壓電晶體142以及多個第二電容144。這些分壓電晶體142以串聯的形式耦接於系統高電壓5VDD與系統低電壓VSS之間，且相鄰的分壓電晶體142之間具有分壓節點N4～N7以提供多個內部偏壓。這些第二電容144分別耦接這些分壓節點N4～N7並且與對應的分壓電晶體142並聯。分壓節點N4~N7所提供的內部分壓包括第一內部偏壓VIB1與第二內部偏壓VIB2。詳細來說，分壓節點N4上的內部偏壓位準是4VDD；分壓節點N5上的內部偏壓位準是3VDD，作為第一內部偏壓VIB1；分壓節點N6上的內部偏壓位準是2VDD，作為第二內部偏壓VIB2；分壓節點N7上的內部偏壓位準是VDD。In the present embodiment, the boost circuit 100 further includes a bias generating circuit 140. The bias generating circuit 140 is coupled between the system high voltage 5VDD and the system low voltage VSS. The bias generating circuit 140 includes a plurality of piezoelectric crystals 142 and a plurality of second capacitors 144. These piezoelectric crystals 142 are coupled in series between the system high voltage 5VDD and the system low voltage VSS, and there are voltage-dividing nodes N4 to N7 between adjacent voltage-dividing crystals 142 to provide multiple internal bias voltages. . The second capacitors 144 are respectively coupled to the voltage-dividing nodes N4-N7 and connected in parallel with the corresponding voltage-dividing crystals 142. The internal partial voltages provided by the voltage dividing nodes N4 to N7 include a first internal bias voltage VIB1 and a second internal bias voltage VIB2. In detail, the internal bias level on the voltage divider node N4 is 4VDD; the internal bias level on the voltage divider node N5 is 3VDD as the first internal bias voltage VIB1; the internal bias voltage level on the voltage divider node N6 It is 2VDD, which is the second internal bias voltage VIB2. The internal bias level on the voltage divider node N7 is VDD.
此外，第一N型電晶體TN4的控制端耦接分壓節點N7以從偏壓產生電路140接收電壓位準VDD。第一P型電晶體TP4的控制端耦接分壓節點N4以從偏壓產生電路140接收電壓位準4VDD。In addition, the control terminal of the first N-type transistor TN4 is coupled to the voltage-dividing node N7 to receive the voltage level VDD from the bias generating circuit 140. The control terminal of the first P-type transistor TP4 is coupled to the voltage-dividing node N4 to receive the voltage level 4VDD from the bias generating circuit 140.
通過偏壓產生電路140提供內部偏壓可以使升壓電路100不需要外接其他偏壓電源，可以免去電路上外接偏壓所需要的導電墊片（pad），大幅節省電路面積以及提升電路效能。另外，耦接分壓節點N4～N7的第二電容144具有穩壓的功效，可以消除因為電壓的劇烈變化造成的尖波（spike），藉此提升升壓電路100的準確度與可靠度。The internal bias provided by the bias generating circuit 140 can make the boost circuit 100 not need to be connected with other bias power, and can eliminate the conductive pad required for external bias on the circuit, which can greatly save circuit area and improve circuit efficiency. . In addition, the second capacitor 144 coupled to the voltage-dividing nodes N4 to N7 has a voltage stabilizing function, which can eliminate spikes caused by a drastic change in voltage, thereby improving the accuracy and reliability of the boost circuit 100.
但須說明的是，在其他的實施例中，升壓電路100也可以搭配其他結構的偏壓產生電路，或是不包括偏壓產生電路而外接偏壓。It should be noted that, in other embodiments, the boosting circuit 100 may also be used with a bias generating circuit of other structure, or an external bias may be included without the bias generating circuit.
偏壓電路130還包括第一開關132、第二開關134、（K-2）個第二P型電晶體（圖2中的3個第二P型電晶體T1～T3）、（K-2）個第二N型電晶體（圖2中的3個第二N型電晶體T4～T6）、第三N型電晶體T7與第三P型電晶體T8。The bias circuit 130 further includes a first switch 132, a second switch 134, (K-2) second P-type transistors (three second P-type transistors T1 to T3 in FIG. 2), (K- 2) a second N-type transistor (3 second N-type transistors T4 to T6 in FIG. 2), a third N-type transistor T7, and a third P-type transistor T8.
第一開關132電性連接位準移位電路110以接收第二電壓脈衝VO2。第一開關132包括第四N型電晶體T9與第四P型電晶體T10。第四P型電晶體T10的第一端（例如源極）耦接第一內部偏壓VIB1，第二端（例如汲極）耦接第四N型電晶體T9的第一端（例如汲極），第四N型電晶體的第二端（例如源極）耦接第二內部偏壓VIB2，並且第四P型電晶體T10與第四N型電晶體T9的控制端共同接收第二電壓脈衝VO2。The first switch 132 is electrically connected to the level shift circuit 110 to receive a second voltage pulse VO2. The first switch 132 includes a fourth N-type transistor T9 and a fourth P-type transistor T10. The first terminal (such as the source) of the fourth P-type transistor T10 is coupled to the first internal bias voltage VIB1, and the second terminal (such as the drain) is coupled to the first terminal (such as the drain) of the fourth N-type transistor T9. ), The second terminal (for example, the source) of the fourth N-type transistor is coupled to the second internal bias voltage VIB2, and the control terminal of the fourth P-type transistor T10 and the fourth N-type transistor T9 receive the second voltage together Pulse VO2.
第二開關134電性連接第一開關132與緩衝電路120。第二開關134包括第五N型電晶體T11與第五P型電晶體T12。第五P型電晶體T12的一端耦接第三節點N3，另一端耦接第五N型電晶體T11的一端、第四P型電晶體T10的第二端與第四N型電晶體T9的第一端，以及第五N型電晶體T11的另一端耦接第二節點N2，並且第五P型電晶體T12與第五N型電晶體T11的控制端共同耦接第一節點N1。The second switch 134 is electrically connected to the first switch 132 and the buffer circuit 120. The second switch 134 includes a fifth N-type transistor T11 and a fifth P-type transistor T12. One end of the fifth P-type transistor T12 is coupled to the third node N3, and the other end is coupled to one end of the fifth N-type transistor T11, the second end of the fourth P-type transistor T10, and the fourth N-type transistor T9. The first terminal and the other end of the fifth N-type transistor T11 are coupled to the second node N2, and the fifth P-type transistor T12 and the control terminal of the fifth N-type transistor T11 are commonly coupled to the first node N1.
第一開關132會根據第二電壓脈衝VO2選擇提供第一內部偏壓VIB1或第二內部偏壓VIB2至第二開關134。第二開關134根據第一節點N1上的電壓選擇提供第一開關132的輸出至第二節點N2或第三節點N3。第一節點N1耦接第1個第一P型電晶體TP1與第1個第一N型電晶體TN1的控制端，第二節點N2耦接第2個第一N型電晶體TN2的控制端，第三節點N3耦接第2個第一P型電晶體TP2的控制端。The first switch 132 selects to provide the first internal bias VIB1 or the second internal bias VIB2 to the second switch 134 according to the second voltage pulse VO2. The second switch 134 provides the output of the first switch 132 to the second node N2 or the third node N3 according to the voltage on the first node N1. The first node N1 is coupled to the control terminal of the first first P-type transistor TP1 and the first first N-type transistor TN1, and the second node N2 is coupled to the control terminal of the second first N-type transistor TN2. The third node N3 is coupled to the control terminal of the second first P-type transistor TP2.
更具體而言，當第一開關132提供第二內部偏壓VIB2至第二開關134時，第二開關134相應地提供第二內部偏壓VIB2作為些動態偏壓的其中之一至第三節點N3。當第一開關132提供第一內部偏壓VIB1至第二開關134時，第二開關134相應地提供第一內部偏壓VIB2作為些動態偏壓的其中之一至第二節點N2。稍後會更詳細說明說明關於第一開關132與第二開關134的實施細節。More specifically, when the first switch 132 provides the second internal bias VIB2 to the second switch 134, the second switch 134 correspondingly provides the second internal bias VIB2 as one of the dynamic biases to the third node N3. . When the first switch 132 provides the first internal bias VIB1 to the second switch 134, the second switch 134 accordingly provides the first internal bias VIB2 as one of the dynamic biases to the second node N2. The implementation details of the first switch 132 and the second switch 134 will be described in more detail later.
圖2的3個第二P型電晶體T1～T3串聯於第一節點N1與第一N型電晶體TN4的控制端之間，並且與前4個第一N型電晶體TN1～TN4交叉耦接。3個第二N型電晶體T4～T6串聯於第4個第一P型電晶體TP4的控制端與第一節點N1之間，並且與前4個第一P型電晶體TP1～TP4交叉耦接。The two second P-type transistors T1 to T3 of FIG. 2 are connected in series between the first node N1 and the control terminal of the first N-type transistor TN4, and are cross-coupled with the first four first N-type transistors TN1 to TN4. Pick up. Three second N-type transistors T4 to T6 are connected in series between the control terminal of the fourth first P-type transistor TP4 and the first node N1, and are cross-coupled with the first four first P-type transistors TP1 to TP4. Pick up.
第二P型電晶體T1的兩端分別耦接第一N型電晶體TN1的控制端（在此同時耦接到第一節點N1）與第一N型電晶體TN2的控制端，其控制端耦接第一N型電晶體TN1的第二端（例如是源極）與第一N型電晶體TN2的第一端（例如是汲極）。第二P型電晶體T2的兩端分別耦接第一N型電晶體TN2的控制端與第一N型電晶體TN3的控制端，其控制端耦接第一N型電晶體TN2的第二端與第一N型電晶體TN3的第一端。第二P型電晶體T3的兩端分別耦接第一N型電晶體TN3的控制端與第一N型電晶體TN4的控制端，其控制端耦接第一N型電晶體TN3的第二端與第一N型電晶體TN4的第一端。The two ends of the second P-type transistor T1 are respectively coupled to the control terminal of the first N-type transistor TN1 (also coupled to the first node N1 at the same time) and the control terminal of the first N-type transistor TN2. The second terminal (for example, the source) of the first N-type transistor TN1 is coupled to the first terminal (for example, the drain) of the first N-type transistor TN2. The two ends of the second P-type transistor T2 are respectively coupled to the control terminal of the first N-type transistor TN2 and the control terminal of the first N-type transistor TN3, and the control terminals thereof are coupled to the second of the first N-type transistor TN2. And the first terminal of the first N-type transistor TN3. The two ends of the second P-type transistor T3 are respectively coupled to the control terminal of the first N-type transistor TN3 and the control terminal of the first N-type transistor TN4, and the control terminals thereof are coupled to the second of the first N-type transistor TN3. And the first terminal of the first N-type transistor TN4.
第二N型電晶體T4的兩端分別耦接第一P型電晶體TP1的控制端（在此同時耦接到第一節點N1）與第一P型電晶體TP2的控制端，其控制端耦接第一P型電晶體TP1的第一端（例如是源極）與第一P型電晶體TP2的第二端（例如是汲極）。第二N型電晶體T5的兩端分別耦接第一P型電晶體TP2的控制端與第一P型電晶體TP3的控制端，其控制端耦接第一P型電晶體TP2的第一端與第一P型電晶體TP3的第二端。第二N型電晶體T6的兩端分別耦接第一P型電晶體TP3的控制端與第一P型電晶體TP4的控制端，其控制端耦接第一P型電晶體TP3的第一端與第一P型電晶體TP4的第二端。The two ends of the second N-type transistor T4 are respectively coupled to the control terminal of the first P-type transistor TP1 (also coupled to the first node N1 at the same time) and the control terminal of the first P-type transistor TP2. The first terminal (for example, the source) of the first P-type transistor TP1 and the second terminal (for example, the drain) of the first P-type transistor TP2 are coupled. The two ends of the second N-type transistor T5 are respectively coupled to the control terminal of the first P-type transistor TP2 and the control terminal of the first P-type transistor TP3, and the control terminals thereof are coupled to the first of the first P-type transistor TP2. And the second terminal of the first P-type transistor TP3. The two ends of the second N-type transistor T6 are respectively coupled to the control terminal of the first P-type transistor TP3 and the control terminal of the first P-type transistor TP4, and the control terminals thereof are coupled to the first of the first P-type transistor TP3. And the second terminal of the first P-type transistor TP4.
換句話說，（K-2）個第二P型電晶體是串聯於第一節點N1與第（K-1）個N型電晶體的控制端之間，並且與前（K-1）個第一N型電晶體交叉耦接。（K-2）個第二N型電晶體串聯於第（K-1）個P型電晶體的控制端與第一節點N1之間，並且與前（K-1）個第一P型電晶體交叉耦接。In other words, the (K-2) second P-type transistor is connected in series between the first node N1 and the control terminal of the (K-1) th N-type transistor, and is in series with the previous (K-1) The first N-type transistor is cross-coupled. The (K-2) second N-type transistor is connected in series between the control terminal of the (K-1) th P-type transistor and the first node N1, and is connected to the first (K-1) first P-type transistor Crystal cross-coupled.
第j個第二P型電晶體的兩端分別耦接第j個第一N型電晶體的控制端與第（j+1）個第一N型電晶體的控制端，且第j個第二P型電晶體的控制端耦接第j個第一N型電晶體的第二端與第（j+1）個第一N型電晶體的第一端；第j個第二N型電晶體的兩端分別耦接第j個第一P型電晶體的控制端與第（j+1）個第一P型電晶體的控制端，且第j個第二N型電晶體的控制端耦接第j個第一P型電晶體的第一端與第（j+1）個第一P型電晶體的第二端。第j個第二P型電晶體與第j個第二N型電晶體表示（K-2）個第二P型電晶體T1～T3與（K-2）個第二N型電晶體中的電晶體T4～T6相對於第一節點N1的順序，j為1至（K-2）的整數且j愈小表示電晶體愈靠近第一節點N1。The two ends of the j-th second P-type transistor are respectively coupled to the control end of the j-th first N-type transistor and the control end of the (j + 1) th first N-type transistor, and the j-th The control terminal of the two P-type transistors is coupled to the second terminal of the j-th first N-type transistor and the first terminal of the (j + 1) -th first N-type transistor; the j-th second N-type transistor The two ends of the crystal are respectively coupled to the control end of the j-th first P-type transistor and the control end of the (j + 1) th first P-type transistor, and the control end of the j-th second N-type transistor The first end of the j-th first P-type transistor is coupled to the second end of the (j + 1) -th first P-type transistor. The j-th second P-type transistor and the j-th second N-type transistor represent the values of (K-2) second P-type transistors T1 to T3 and (K-2) second N-type transistor. The order of the transistors T4 to T6 relative to the first node N1, j is an integer from 1 to (K-2), and the smaller j is, the closer the transistor is to the first node N1.
第三N型電晶體T7的控制端耦接第二節點N2，其兩端分別耦接第二內部偏壓VIB2與第一N型電晶體TN3的控制端。第三P型電晶體T8的控制端耦接第三節點N3，其兩端分別耦接第一內部偏壓VIB1與第一P型電晶體TP3的控制端。The control terminal of the third N-type transistor T7 is coupled to the second node N2, and its two ends are respectively coupled to the control terminal of the second internal bias voltage VIB2 and the first N-type transistor TN3. The control terminal of the third P-type transistor T8 is coupled to the third node N3, and its two ends are respectively coupled to the control terminal of the first internal bias voltage VIB1 and the first P-type transistor TP3.
簡言之，偏壓電路130的第一開關132與第二開關134會分別根據第二電壓脈衝VO2以及第一節點N1上的電壓來調整第二節點N2或第三節點N3的電壓位準。第二節點N2與第三節點N3分別耦接第一N型電晶體TN2或第一P型電晶體TP2的控制端並且第二節點N2與第三節點N3上的電壓位準還會控制第三N型電晶體T7或第三P型電晶體T8以影響第一N型電晶體TN3或第一P型電晶體TP3的控制端的電壓位準。因此偏壓電路130可以至少提供動態偏壓至前3個第一P型電晶體TP1～TP3與前3個第一N型電晶體TN1～TN3。In short, the first switch 132 and the second switch 134 of the bias circuit 130 adjust the voltage level of the second node N2 or the third node N3 according to the second voltage pulse VO2 and the voltage on the first node N1, respectively. . The second node N2 and the third node N3 are respectively coupled to the control terminals of the first N-type transistor TN2 or the first P-type transistor TP2, and the voltage levels on the second node N2 and the third node N3 will also control the third node. The N-type transistor T7 or the third P-type transistor T8 affects the voltage level of the control terminal of the first N-type transistor TN3 or the first P-type transistor TP3. Therefore, the bias circuit 130 can provide at least dynamic bias to the first three first P-type transistors TP1 to TP3 and the first three first N-type transistors TN1 to TN3.
請搭配參照圖3，當輸入電壓脈衝VIN處於高位準VDD時，第一電壓脈衝VO1處於低位準4VDD（K=5），第二電壓脈衝VO2處於低位準2VDD，第三電壓脈衝VO3處於低位準0V（在此VSS=0V）。此時，第二電壓脈衝VO2低於第一內部偏壓VIB1但實質上等於第二內部偏壓VIB2，因此第一開關132的第四P型電晶體T10被導通且第四N型電晶體T9被截止，第一內部偏壓VIB1被提供至第二開關134。Please refer to Figure 3. When the input voltage pulse VIN is at a high level VDD, the first voltage pulse VO1 is at a low level 4VDD (K = 5), the second voltage pulse VO2 is at a low level 2VDD, and the third voltage pulse VO3 is at a low level. 0V (here VSS = 0V). At this time, the second voltage pulse VO2 is lower than the first internal bias voltage VIB1 but is substantially equal to the second internal bias voltage VIB2. Therefore, the fourth P-type transistor T10 of the first switch 132 is turned on and the fourth N-type transistor T9 is turned on. Being turned off, the first internal bias VIB1 is supplied to the second switch 134.
另一方面，第一P型電晶體TP5被導通，第一P型電晶體TP4～TP1也依序被導通，第二N型電晶體T4～T6也相對應被導通。第一節點N1與第三節點N3的位準會一起被分壓節點N4的位準上拉至4VDD。第三P型電晶體T8被截止。On the other hand, the first P-type transistor TP5 is turned on, the first P-type transistors TP4 to TP1 are sequentially turned on, and the second N-type transistor T4 to T6 are also turned on correspondingly. The levels of the first node N1 and the third node N3 will be pulled up to 4VDD by the level of the divided node N4. The third P-type transistor T8 is turned off.
因為第一節點N1的位準被上拉，第五P型電晶體T12被截止而第五N型電晶體T11被導通。由第一開關132所提供的第一內部偏壓VIB1被提供至第二節點N2，以使第二節點N2的位準維持在3VDD。第三N型電晶體T7受控於第二節點N2的位準而被導通，讓第一N型電晶體TN3的控制端接收第二內部偏壓VIB2。Because the level of the first node N1 is pulled up, the fifth P-type transistor T12 is turned off and the fifth N-type transistor T11 is turned on. The first internal bias voltage VIB1 provided by the first switch 132 is provided to the second node N2 to maintain the level of the second node N2 at 3VDD. The third N-type transistor T7 is controlled by the level of the second node N2 and is turned on, so that the control terminal of the first N-type transistor TN3 receives the second internal bias voltage VIB2.
第一N型電晶體TN1的控制端耦接第一節點N1。第一N型電晶體TN2與第一N型電晶體TN3的控制端分別接收第一內部偏壓VIB1與第二內部偏壓VIB2。第一N型電晶體TN4的控制端固定接收來自分壓節點N7的內部偏壓VDD。第一N型電晶體TN5的控制端接收處於低位準的第三電壓脈衝VO3。因此第一N型電晶體TP1～TP5依序被截止，對應地，第二P型電晶體T1～T3也被截止。處在截止狀態的第一N型電晶體TN1～TN5與第二P型電晶體T1～T3可以提供逐步降壓功能，將輸出端點OUT上的5VDD與系統低電壓VSS之間區分成多個電壓範圍，以避免單顆電晶體承受過大的跨壓而異常或損毀，例如每顆電晶體所承認的跨壓不超過VDD。因為升壓電路100中每個電晶體不需要遭遇過大的跨壓，因此可以利用低壓製程的電晶體來實現，不需要高壓製成的電晶體元件，進而能夠降低成本以及功耗。使用低壓製程的元件也能夠幫助縮減電路面積。The control terminal of the first N-type transistor TN1 is coupled to the first node N1. The control terminals of the first N-type transistor TN2 and the first N-type transistor TN3 receive the first internal bias voltage VIB1 and the second internal bias voltage VIB2, respectively. The control terminal of the first N-type transistor TN4 fixedly receives the internal bias voltage VDD from the voltage dividing node N7. The control terminal of the first N-type transistor TN5 receives a third voltage pulse VO3 at a low level. Therefore, the first N-type transistors TP1 to TP5 are sequentially turned off, and correspondingly, the second P-type transistors T1 to T3 are also turned off. The first N-type transistors TN1 to TN5 and the second P-type transistors T1 to T3 in the off state can provide a step-down function to distinguish between 5VDD on the output terminal OUT and the system low voltage VSS. Voltage range to avoid abnormal or damage to a single transistor under excessive voltage, for example, the voltage recognized by each transistor does not exceed VDD. Because each transistor in the boost circuit 100 does not need to experience excessive cross-voltage, it can be realized by using a low-voltage process transistor, and no transistor element made of high-voltage is needed, which can reduce cost and power consumption. Using low-voltage components can also help reduce circuit area.
特別補充的是，在本實施例中，因為輸出端點OUT上的電壓在上升時，第一節點N1上的電壓上升速度會快於第二節點N2上的電壓上升速度，因此耦接於第一節點N1跟第二節點N2之間的第一電容CF可以緩衝第一節點N1與第二節點N2之間的電壓變化速度，以提升輸出電壓脈衝VOUT的位準上升速度。In particular, in this embodiment, because the voltage at the output terminal OUT is rising, the voltage rising speed at the first node N1 will be faster than the voltage rising speed at the second node N2, so it is coupled to the first node N2. The first capacitor CF between the node N1 and the second node N2 can buffer the speed of the voltage change between the first node N1 and the second node N2 to increase the level of the output voltage pulse VOUT.
最終，輸出端點OUT會輸出處於高位準5VDD的輸出電壓脈衝VOUT。Finally, the output terminal OUT will output an output voltage pulse VOUT at a high level of 5VDD.
類似地，當輸入電壓脈衝VIN處於低位準VSS時，第一電壓脈衝VO1處於高位準5VDD，第二電壓脈衝VO2處於高位準3VDD，第三電壓脈衝VO3處於高位準VDD。Similarly, when the input voltage pulse VIN is at a low level VSS, the first voltage pulse VO1 is at a high level 5VDD, the second voltage pulse VO2 is at a high level 3VDD, and the third voltage pulse VO3 is at a high level VDD.
此時，第二電壓脈衝VO2實質上等於第一內部偏壓VIB1且高於第二內部偏壓VIB2，因此第一開關132的第四P型電晶體T10被截止且第四N型電晶體T9被導通，第二內部偏壓VIB2被提供至第二開關134。At this time, the second voltage pulse VO2 is substantially equal to the first internal bias voltage VIB1 and is higher than the second internal bias voltage VIB2. Therefore, the fourth P-type transistor T10 of the first switch 132 is turned off and the fourth N-type transistor T9 is turned off. When turned on, the second internal bias VIB2 is provided to the second switch 134.
第一N型電晶體TN5被第三電壓脈衝VO3導通，第一N型電晶體TN1～TN4也依序被導通，第二P型電晶體T1～T3也相對應被導通，第一節點N1與第二節點N2的位準會一起被分壓節點N7的位準下拉至VDD。The first N-type transistor TN5 is turned on by the third voltage pulse VO3, the first N-type transistors TN1 to TN4 are also turned on in order, and the second P-type transistor T1 to T3 are also turned on correspondingly. The first node N1 and The level of the second node N2 will be pulled down to VDD by the level of the divided node N7.
因為第二節點N2的位準被下拉，第三N型電晶體T7被截止。因為第一節點N1的位準被下拉至VDD，第五P型電晶體T12被導通而第五N型電晶體T11被截止。由第一開關132所提供的第二內部偏壓VIB2被提供至第三節點N3，以使第三節點N3的位準維持在2VDD。第三P型電晶體T8被導通，第一P型電晶體TP3的控制端接收第一內部偏壓VIB1。Because the level of the second node N2 is pulled down, the third N-type transistor T7 is turned off. Because the level of the first node N1 is pulled down to VDD, the fifth P-type transistor T12 is turned on and the fifth N-type transistor T11 is turned off. The second internal bias voltage VIB2 provided by the first switch 132 is provided to the third node N3 to maintain the level of the third node N3 at 2VDD. The third P-type transistor T8 is turned on, and the control terminal of the first P-type transistor TP3 receives the first internal bias voltage VIB1.
第一P型電晶體TP1的控制端耦接第一節點N1。第一P型電晶體TP2與第一P型電晶體TP3的控制端分別接收第二內部偏壓VIB2與第一內部偏壓VIB1。第一P型電晶體TP4的控制端固定接收來自分壓節點N4的電壓位準4VDD。第一P型電晶體TP5的控制端接收處於高位準的第一電壓脈衝VO1。因此第一P型電晶體TP1～TP5依序被截止，第二N型電晶體T4～T6對應地也被截止。處在截止狀態的第一P型電晶體TP1～TP5與第二N型電晶體T4～T6也會提供逐步降壓功能，將輸出端點OUT上的位準VSS與系統高電壓5VDD之間區分成多個電壓範圍以避免單顆電晶體承受過大的跨壓而異常或損毀。The control terminal of the first P-type transistor TP1 is coupled to the first node N1. The control terminals of the first P-type transistor TP2 and the first P-type transistor TP3 receive the second internal bias voltage VIB2 and the first internal bias voltage VIB1, respectively. The control terminal of the first P-type transistor TP4 fixedly receives the voltage level 4VDD from the voltage dividing node N4. The control terminal of the first P-type transistor TP5 receives the first voltage pulse VO1 at a high level. Therefore, the first P-type transistors TP1 to TP5 are sequentially turned off, and the second N-type transistors T4 to T6 are also turned off correspondingly. The first P-type transistors TP1 to TP5 and the second N-type transistors T4 to T6 in the cut-off state will also provide a step-down function, which will set the level between the output terminal OUT level VSS and the system high voltage 5VDD. Divided into multiple voltage ranges to avoid abnormal or damage to a single transistor under excessive cross-voltage.
同樣地，第一電容CF可以縮短輸出電壓脈衝VOUT的位準上升速度。最終，輸出端點OUT可以輸出處於低位準VSS的輸出電壓脈衝VOUT。Similarly, the first capacitor CF can shorten the level rising speed of the output voltage pulse VOUT. Finally, the output terminal OUT can output an output voltage pulse VOUT at a low level VSS.
圖4是依照本發明的一實施例的一種具有第一電容的升壓電路跟缺乏第一電容的升壓電路所產生的輸出電壓脈衝波形圖。曲線410則代表與升壓電路100結構基本上相同但缺乏第一電容CF的升壓電路所提供的輸出電壓脈衝的波形，曲線420代表升壓電路100的輸出電壓脈衝VOUT的波形。曲線420的上升時間與下降時間比曲線410來的短，可見使用第一電容CF可以有效的縮短位準的上升時間與下降時間。從圖4的結果還可以清楚看到，升壓電路100能夠放大輸入電壓脈衝VIN，所輸出電壓脈衝VOUT位準能準確地在VSS與5VDD之間切換，實現一階段切換位準的全擺幅輸出。4 is a waveform diagram of output voltage pulses generated by a booster circuit having a first capacitor and a booster circuit lacking a first capacitor according to an embodiment of the present invention. Curve 410 represents the waveform of the output voltage pulse provided by the booster circuit that is basically the same as the structure of the booster circuit 100 but lacks the first capacitor CF. Curve 420 represents the waveform of the output voltage pulse VOUT of the booster circuit 100. The rise time and fall time of the curve 420 are shorter than those of the curve 410. It can be seen that the use of the first capacitor CF can effectively shorten the rise time and fall time of the level. It can also be clearly seen from the result of FIG. 4 that the booster circuit 100 can amplify the input voltage pulse VIN, and the output voltage pulse VOUT level can be accurately switched between VSS and 5VDD to achieve a full swing of the switching level in one stage Output.
綜上所述，本發明提供一種升壓電路、輸出緩衝電路與顯示面板。升壓電路可以應用於顯示面板並且包括輸出緩衝電路。輸出緩衝電路包括緩衝電路與偏壓電路，且從位準移位電路接收有關於輸入電壓脈衝的第一電壓脈衝、第二電壓脈衝與第三電壓脈衝。偏壓電路可以根據第二電壓脈衝來因應輸入電壓脈衝的位準高低而提供不同的偏壓以穩定緩衝電路的操作。本發明的升壓電路中的電晶體會被有效保護而不需要因為輸入電壓脈衝的位準切換而遭遇過大的電壓，而且可以提供位準精確的全幅放大電壓脈衝。本發明的偏壓電路在第1個第一P型電晶體以及第1個第一N型電晶體的控制端與第2個第一N型電晶體的控制端之間設置第一電容以緩衝兩端點的電壓改變，因而可以縮短輸出電壓脈衝的上升時間跟下降時間。因此本發明的升壓電路具有運作穩定、輸出電壓位準精確且切換速度快、全擺幅輸出、以及適用於低壓製程的優點。In summary, the present invention provides a boost circuit, an output buffer circuit, and a display panel. The boost circuit can be applied to a display panel and includes an output buffer circuit. The output buffer circuit includes a buffer circuit and a bias circuit, and receives a first voltage pulse, a second voltage pulse, and a third voltage pulse regarding the input voltage pulse from the level shift circuit. The bias circuit can provide different bias voltages according to the level of the input voltage pulse to stabilize the operation of the buffer circuit according to the level of the input voltage pulse. The transistor in the booster circuit of the present invention will be effectively protected from the need to encounter excessive voltage due to the level switching of the input voltage pulse, and can provide a full-amplified amplified voltage pulse with accurate level. In the bias circuit of the present invention, a first capacitor is provided between the control terminal of the first first P-type transistor and the first first N-type transistor and the control terminal of the second first N-type transistor to The voltage change at both ends of the buffer is buffered, so the rise time and fall time of the output voltage pulse can be shortened. Therefore, the booster circuit of the invention has the advantages of stable operation, accurate output voltage level, fast switching speed, full swing output, and suitability for low-voltage processes.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
10‧‧‧顯示面板
100‧‧‧升壓電路
110‧‧‧位準移位電路
120‧‧‧緩衝電路
130‧‧‧偏壓電路
132‧‧‧第一開關
134‧‧‧第二開關
140‧‧‧偏壓產生電路
142‧‧‧分壓電晶體
144‧‧‧第二電容
150‧‧‧輸出緩衝電路
200‧‧‧閘極驅動器
410、420‧‧‧電壓曲線
CF‧‧‧第一電容
GS‧‧‧閘極信號
K‧‧‧整數
N1‧‧‧第一節點
N2‧‧‧第二節點
N3‧‧‧第三節點
N4 ~N7‧‧‧分壓節點
SL‧‧‧掃描線
TP1～TP5‧‧‧第一P型電晶體
TN1～TN5‧‧‧第一N型電晶體
T1～T3‧‧‧第二P型電晶體
T4～T6‧‧‧第二N型電晶體
T7‧‧‧第三N型電晶體
T8‧‧‧第三P型電晶體
T9‧‧‧第四N型電晶體
T10‧‧‧第四P型電晶體
T11‧‧‧第五N型電晶體
T12‧‧‧第五P型電晶體
OUT‧‧‧輸出端點
PX‧‧‧畫素
VDD‧‧‧電壓位準
VIB1‧‧‧第一內部偏壓
VIB2‧‧‧第二內部偏壓
VIN‧‧‧輸入電壓脈衝
VSS‧‧‧系統低電壓
VO1‧‧‧第一電壓脈衝
VO2‧‧‧第二電壓脈衝
VO3‧‧‧第三電壓脈衝
VOUT‧‧‧輸出電壓脈衝
10‧‧‧Display Panel
100‧‧‧Boost circuit
110‧‧‧level shift circuit
120‧‧‧ buffer circuit
130‧‧‧ bias circuit
132‧‧‧The first switch
134‧‧‧Second switch
140‧‧‧ bias generating circuit
142‧‧‧point piezoelectric crystal
144‧‧‧Second capacitor
150‧‧‧ output buffer circuit
200‧‧‧Gate driver
410, 420‧‧‧Voltage curve
CF‧‧‧first capacitor
GS‧‧‧Gate signal
K‧‧‧ integer
N1‧‧‧First Node
N2‧‧‧Second Node
N3‧‧‧ third node
N4 ~ N7‧‧‧ divided voltage nodes
SL‧‧‧scan line
TP1 ～ TP5‧‧‧The first P-type transistor
TN1 ～ TN5‧‧‧The first N-type transistor
T1 ～ T3‧‧‧Second P-type transistor
T4 ～ T6‧‧‧Second N-type transistor
T7‧‧‧Third N-type transistor
T8‧‧‧Third P-type transistor
T9‧‧‧Fourth N-type transistor
T10‧‧‧Fourth P-type transistor
T11‧‧‧Fifth N-type transistor
T12‧‧‧Fifth P-type transistor
OUT‧‧‧ output endpoint
PX‧‧‧Pixels
VDD‧‧‧Voltage Level
VIB1‧‧‧First internal bias
VIB2‧‧‧Second Internal Bias
VIN‧‧‧Input voltage pulse
VSS‧‧‧System Low Voltage
VO1‧‧‧First voltage pulse
VO2‧‧‧second voltage pulse
VO3‧‧‧The third voltage pulse
VOUT‧‧‧Output voltage pulse
圖1是依照本發明的一實施例的一種顯示面板的示意圖。
圖2是依照本發明的一實施例的一種升壓電路的電路示意圖。
圖3是依照本發明的一實施例的一種升壓電路的信號波形圖。
圖4是依照本發明的一實施例的一種具有第一電容的升壓電路跟缺乏第一電容的升壓電路所產生的輸出電壓脈衝波形圖。
FIG. 1 is a schematic diagram of a display panel according to an embodiment of the invention.
FIG. 2 is a circuit diagram of a booster circuit according to an embodiment of the present invention.
FIG. 3 is a signal waveform diagram of a booster circuit according to an embodiment of the present invention.
4 is a waveform diagram of output voltage pulses generated by a booster circuit having a first capacitor and a booster circuit lacking a first capacitor according to an embodiment of the present invention.
Claims (13)
一位準移位電路，接收該輸入電壓脈衝以提供平移後的一第一電壓脈衝、一第二電壓脈衝與一第三電壓脈衝；以及
一輸出緩衝電路，包括：
一緩衝電路，包括：
K個第一P型電晶體，串聯於一系統高電壓與該輸出端點之間，K是大於或等於5的整數；以及
K個第一N型電晶體，串聯於該輸出端點與一系統低電壓之間，
其中，第K個第一P型電晶體受控於該第一電壓脈衝且第K個第一N型電晶體受控於該第三電壓脈衝，其中第i個第一P型電晶體與第i個第一N型電晶體表示該K個第一P型電晶體與該K個第一N型電晶體中的電晶體相對於該輸出端點的順序，i為1至K的整數且i愈小表示該電晶體愈靠近該輸出端點；以及
一偏壓電路，電性連接於該緩衝電路與該位準移位電路之間，其中，該偏壓電路根據該第二電壓脈衝提供多個動態偏壓至該緩衝電路，該K個第一P型電晶體與該K個第一N型電晶體中的部分電晶體受控於該些動態偏壓，且該偏壓電路包括：
一第一電容，耦接第1個第一P型電晶體的控制端與第1個第一N型電晶體的控制端。 A boost circuit is used to receive an input voltage pulse to provide an output voltage pulse at an output terminal. The boost circuit includes:
A level shift circuit receives the input voltage pulse to provide a first voltage pulse, a second voltage pulse and a third voltage pulse after translation; and an output buffer circuit, including:
A buffer circuit, including:
K first P-type transistors connected in series between a system high voltage and the output terminal, K is an integer greater than or equal to 5; and
K first N-type transistors connected in series between the output terminal and a system low voltage,
Wherein, the K-th first P-type transistor is controlled by the first voltage pulse and the K-th first N-type transistor is controlled by the third voltage pulse, wherein the i-th first P-type transistor and the i first N-type transistors represent the order of the K first P-type transistors and the K first N-type transistors relative to the output endpoint, i is an integer from 1 to K and i The smaller means the transistor is closer to the output terminal; and a bias circuit is electrically connected between the buffer circuit and the level shift circuit, wherein the bias circuit is based on the second voltage pulse A plurality of dynamic bias voltages are provided to the buffer circuit, some of the K first P-type transistors and the K first N-type transistors are controlled by the dynamic bias voltages, and the bias circuit include:
A first capacitor is coupled to the control terminal of the first first P-type transistor and the control terminal of the first first N-type transistor.
一第一開關，電性連接該位準移位電路；
一第二開關，電性連接該第一開關與該緩衝電路，
其中，該第一開關根據該第二電壓脈衝選擇提供一第一內部偏壓或一第二內部偏壓至該第二開關，以及該第二開關受控於一第一節點上的電壓以提供該第一開關的輸出至一第二節點或一第三節點，其中，該第一節點耦接第1個第一P型電晶體與第1個第一N型電晶體的控制端，該第二節點耦接第2個第一N型電晶體的控制端，該第三節點耦接第2個第一P型電晶體的控制端。 The booster circuit as described in item 1 of the patent application scope, wherein the bias circuit further includes:
A first switch electrically connected to the level shift circuit;
A second switch electrically connecting the first switch and the buffer circuit,
Wherein, the first switch selectively provides a first internal bias voltage or a second internal bias voltage to the second switch according to the second voltage pulse, and the second switch is controlled by a voltage on a first node to provide The output of the first switch is to a second node or a third node, wherein the first node is coupled to the control terminals of the first first P-type transistor and the first first N-type transistor. The two nodes are coupled to the control terminal of the second first N-type transistor, and the third node is coupled to the control terminal of the second first P-type transistor.
當該第一開關提供該第二內部偏壓至該第二開關時，該第二開關相應地提供該第二內部偏壓作為該些動態偏壓的其中之一至該第三節點，以及
當該第一開關提供該第一內部偏壓至該第二開關時，該第二開關相應地提供該第一內部偏壓作為該些動態偏壓的其中之一至該第二節點。 The booster circuit as described in item 2 of the patent application scope, in which
When the first switch provides the second internal bias to the second switch, the second switch accordingly provides the second internal bias as one of the dynamic biases to the third node, and when the When the first switch provides the first internal bias to the second switch, the second switch correspondingly provides the first internal bias as one of the dynamic biases to the second node.
（K-2）個第二N型電晶體，串聯於第（K-1）個P型電晶體的控制端與該第一節點之間，其中第j個第二N型電晶體的兩端分別耦接第j個第一P型電晶體的控制端與第（j+1）個第一P型電晶體的控制端，且該第j個第二N型電晶體的控制端耦接第j個第一P型電晶體的第一端與第（j+1）個第一P型電晶體的第二端；
（K-2）個第二P型電晶體，串聯於該第一節點與第（K-1）個N型電晶體的控制端之間，其中第j個第二P型電晶體的兩端分別耦接第j個第一N型電晶體的控制端與第（j+1）個第一N型電晶體的控制端，且該第j個第二P型電晶體的控制端耦接第j個第一N型電晶體的第二端與第（j+1）個第一N型電晶體的第一端，
其中第j個第二P型電晶體與第j個第二N型電晶體表示該（K-2）個第二P型電晶體與該（K-2）個第二N型電晶體中的電晶體相對於該第一節點的順序，j為1至（K-2）的整數且j愈小表示該電晶體愈靠近該第一節點；
一第三P型電晶體，其控制端耦接該第三節點，其兩端分別耦接該第一內部偏壓與第3個第一P型電晶體的控制端；以及
一第三N型電晶體，其控制端耦接該第二節點，其兩端分別耦接該第二內部偏壓與第3個第一N型電晶體的控制端。 The booster circuit as described in item 2 of the patent application scope, wherein the bias circuit further includes:
(K-2) second N-type transistor, connected in series between the control terminal of the (K-1) th P-type transistor and the first node, where both ends of the j-th second N-type transistor The control terminal of the j-th first P-type transistor and the control terminal of the (j + 1) -th first P-type transistor are respectively coupled, and the control end of the j-th second N-type transistor is coupled to the the first end of the j first P-type transistors and the second end of the (j + 1) th first P-type transistor;
(K-2) second P-type transistors connected in series between the first node and the control terminal of the (K-1) th N-type transistor, where both ends of the j-th second P-type transistor The control terminal of the jth first N-type transistor and the control terminal of the (j + 1) th first N-type transistor are respectively coupled, and the control end of the jth second P-type transistor is coupled to the the second end of the j first N-type transistors and the first end of the (j + 1) th first N-type transistor,
Where the j-th second P-type transistor and the j-th second N-type transistor represent the (K-2) second P-type transistor and the (K-2) second N-type transistor The order of the transistor relative to the first node, j is an integer from 1 to (K-2) and the smaller j indicates the closer the transistor is to the first node;
A third P-type transistor, the control end of which is coupled to the third node, and both ends thereof are respectively coupled to the first internal bias and the control end of the third first P-type transistor; and a third N-type transistor The control terminal of the transistor is coupled to the second node, and the two ends thereof are respectively coupled to the control terminal of the second internal bias voltage and the third first N-type transistor.
該第一開關包括：
一第四P型電晶體與一第四N型電晶體，該第四P型電晶體的第一端耦接該第一內部偏壓，第二端耦接該第四N型電晶體的第一端，該第四N型電晶體的第二端耦接該第二內部偏壓，並且該第四P型電晶體與該第四N型電晶體的控制端共同接收該第二電壓脈衝；以及
該第二開關包括：
一第五P型電晶體與一第五N型電晶體，該第五P型電晶體的一端耦接該第三節點，另一端耦接該第五N型電晶體的一端、該第四P型電晶體的第二端與該第四N型電晶體的第一端，以及該第五N型電晶體的另一端耦接該第二節點，並且該第五P型電晶體與該第五N型電晶體的控制端共同耦接該第一節點。 The booster circuit as described in item 4 of the patent application scope, in which
The first switch includes:
A fourth P-type transistor and a fourth N-type transistor, the first end of the fourth P-type transistor is coupled to the first internal bias voltage, and the second end is coupled to the first end of the fourth N-type transistor At one end, the second end of the fourth N-type transistor is coupled to the second internal bias, and the fourth P-type transistor and the control end of the fourth N-type transistor jointly receive the second voltage pulse; And the second switch includes:
A fifth P-type transistor and a fifth N-type transistor, one end of the fifth P-type transistor is coupled to the third node, and the other end is coupled to one end of the fifth N-type transistor and the fourth P The second end of the transistor and the first end of the fourth N-type transistor, and the other end of the fifth N-type transistor are coupled to the second node, and the fifth P-type transistor and the fifth The control terminal of the N-type transistor is commonly coupled to the first node.
當該（K-2）個第二P型電晶體被導通時，該第二節點的位準被下拉以截止該第三N型電晶體，該第一節點的位準被下拉以截止該第五N型電晶體並導通該第五P型電晶體，其中該第四P型電晶體被截止且該第四N型電晶體被導通使得該第二內部偏壓被提供至該第三節點。 The booster circuit as described in item 5 of the patent application scope, wherein when the (K-2) second P-type transistors are turned on, the level of the second node is pulled down to turn off the third N-type transistor Crystal, the level of the first node is pulled down to turn off the fifth N-type transistor and turn on the fifth P-type transistor, wherein the fourth P-type transistor is turned off and the fourth N-type transistor is turned on The second internal bias voltage is provided to the third node.
當該（K-2）個第二N型電晶體被導通時，該第三節點的位準被上拉以截止該第三P型電晶體，該第一節點的位準被上拉以導通該第五N型電晶體並截止該第五P型電晶體，其中該第四P型電晶體被導通且該第四N型電晶體被截止使得該第一內部偏壓被提供至該第二節點。 The booster circuit as described in item 5 of the patent application scope, wherein when the (K-2) second N-type transistors are turned on, the level of the third node is pulled up to turn off the third P-type transistor Transistor, the level of the first node is pulled up to turn on the fifth N-type transistor and turn off the fifth P-type transistor, wherein the fourth P-type transistor is turned on and the fourth N-type transistor Is turned off so that the first internal bias voltage is provided to the second node.
一偏壓產生電路，耦接該系統高電壓，包括：
多個分壓電晶體，以串聯的形式耦接於該系統高電壓與該系統低電壓之間，且相鄰的該些分壓電晶體之間具有一分壓節點以提供該些內部偏壓的其中之一；以及
多個第二電容，耦接該些分壓節點且與對應的分壓電晶體並聯。 The booster circuit as described in item 8 of the patent application scope also includes a bias voltage generating circuit, coupled to the high voltage of the system, including:
A plurality of partial piezoelectric crystals are coupled in series between the high voltage of the system and the low voltage of the system, and a voltage dividing node is provided between adjacent partial piezoelectric crystals to provide the internal bias voltages One of them; and a plurality of second capacitors, coupled to the voltage dividing nodes and connected in parallel with the corresponding piezoelectric piezoelectric crystal.
一緩衝電路，包括：
K個第一P型電晶體，串聯於一系統高電壓與一輸出端點之間，K是大於或等於5的整數；以及
K個第一N型電晶體，串聯於該輸出端點與一系統低電壓之間，
其中，第K個第一P型電晶體受控於一第一電壓脈衝且第K個第一N型電晶體受控於一第三電壓脈衝，其中第i個第一P型電晶體與第i個第一N型電晶體表示該K個第一P型電晶體與該K個第一N型電晶體中的電晶體相對於該輸出端點的順序，i為1至K的整數且i愈小表示該電晶體愈靠近該輸出端點；以及
一偏壓電路，接收一第二電壓脈衝且電性連接於該緩衝電路，其中，該偏壓電路根據該第二電壓脈衝提供多個動態偏壓至該緩衝電路，該偏壓電路包括：
一第一電容，耦接第1個第一P型電晶體的控制端與第1個第一N型電晶體的控制端，
其中該K個第一P型電晶體與該K個第一N型電晶體中的部分電晶體受控於該些動態偏壓，且該第二電壓脈衝的位準大於該第三電壓脈衝且小於該第一電壓脈衝。 An output buffer circuit includes a buffer circuit, including:
K first P-type transistors connected in series between a system high voltage and an output terminal, K is an integer greater than or equal to 5; and
K first N-type transistors connected in series between the output terminal and a system low voltage,
Wherein, the K-th first P-type transistor is controlled by a first voltage pulse and the K-th first N-type transistor is controlled by a third voltage pulse, wherein the i-th first P-type transistor and the i first N-type transistors represent the order of the K first P-type transistors and the K first N-type transistors relative to the output endpoint, i is an integer from 1 to K and i The smaller the value, the closer the transistor is to the output terminal; and a bias circuit, which receives a second voltage pulse and is electrically connected to the buffer circuit, wherein the bias circuit provides multiple voltages according to the second voltage pulse Dynamic bias voltage to the buffer circuit, the bias circuit includes:
A first capacitor coupled to the control terminal of the first first P-type transistor and the control terminal of the first first N-type transistor,
Among the K first P-type transistors and some of the K first N-type transistors are controlled by the dynamic bias voltages, and the level of the second voltage pulse is greater than the third voltage pulse and Less than this first voltage pulse.
如申請專利範圍第1項所述的升壓電路；
一閘極驅動器，電性連接該升壓電路以接收該輸出電壓脈衝且提供多個閘極信號；
多條掃描線；以及
多個畫素，耦接該些掃描線以接收對應的閘極信號。 A display panel, including:
The booster circuit as described in item 1 of the patent application scope;
A gate driver, electrically connected to the booster circuit to receive the output voltage pulse and provide multiple gate signals;
Multiple scan lines; and multiple pixels, coupled to the scan lines to receive corresponding gate signals.
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| Publication number | Priority date | Publication date | Assignee | Title |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6130556A (en) * | 1998-06-16 | 2000-10-10 | Lsi Logic Corporation | Integrated circuit I/O buffer with 5V well and passive gate voltage |
| CN1777030A (en) * | 2004-11-16 | 2006-05-24 | 矽成积体电路股份有限公司 | Input Buffer circuit for reducing power consumption |
| TW200828233A (en) * | 2006-12-29 | 2008-07-01 | Cheertek Inc | Gate driver structure of TFT-LCD display |
| CN101295536A (en) * | 2007-04-24 | 2008-10-29 | 南亚科技股份有限公司 | Booster circuit and memory structure using the same |
| TWI305361B (en) * | 2004-05-05 | 2009-01-11 | Sandisk Corp | Boosting to control programming of non-volatile memory |
| TWI422141B (en) * | 2010-05-07 | 2014-01-01 | Macronix Int Co Ltd | Oscillator with frequency determined by relative magnitudes of current sources |
| CN103915069A (en) * | 2013-01-04 | 2014-07-09 | 矽创电子股份有限公司 | Driving circuit of display panel and driving module thereof, and display device and method for manufacturing the same |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0974348A (en) * | 1995-09-06 | 1997-03-18 | Seiko Epson Corp | Semiconductor device |
| JP3958271B2 (en) * | 2003-09-19 | 2007-08-15 | シャープ株式会社 | Level shifter and display device using the same |
| US7218165B1 (en) * | 2005-12-27 | 2007-05-15 | Ememory Technology Inc. | Boost circuit |
| CN100536303C (en) * | 2006-12-25 | 2009-09-02 | 普诚科技股份有限公司 | Voltage boost circuit and voltage level shifter |
| JP2008309834A (en) * | 2007-06-12 | 2008-12-25 | Seiko Epson Corp | Semiconductor integrated circuit, power source system interface and electronic equipment |
| TW201044787A (en) * | 2009-06-02 | 2010-12-16 | Innochip Technology Inc | Low-to-high level shift circuit and control method thereof |
| JP2010283954A (en) * | 2009-06-03 | 2010-12-16 | Panasonic Corp | Step-up circuit and step-up circuit device |
| KR20110024936A (en) * | 2009-09-03 | 2011-03-09 | 삼성전자주식회사 | Boosting circuit for wide range suplly voltage, electronic device having the same and voltage boosting mehtod |
| CN101976551B (en) * | 2010-10-19 | 2014-06-04 | 友达光电股份有限公司 | Display driving circuit, liquid crystal display and display driving method |
-
2019
- 2019-03-28 TW TW108111010A patent/TWI675273B/en active
- 2019-10-16 CN CN201910982916.4A patent/CN110580877B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6130556A (en) * | 1998-06-16 | 2000-10-10 | Lsi Logic Corporation | Integrated circuit I/O buffer with 5V well and passive gate voltage |
| TWI305361B (en) * | 2004-05-05 | 2009-01-11 | Sandisk Corp | Boosting to control programming of non-volatile memory |
| CN1777030A (en) * | 2004-11-16 | 2006-05-24 | 矽成积体电路股份有限公司 | Input Buffer circuit for reducing power consumption |
| TW200828233A (en) * | 2006-12-29 | 2008-07-01 | Cheertek Inc | Gate driver structure of TFT-LCD display |
| CN101295536A (en) * | 2007-04-24 | 2008-10-29 | 南亚科技股份有限公司 | Booster circuit and memory structure using the same |
| TWI422141B (en) * | 2010-05-07 | 2014-01-01 | Macronix Int Co Ltd | Oscillator with frequency determined by relative magnitudes of current sources |
| CN103915069A (en) * | 2013-01-04 | 2014-07-09 | 矽创电子股份有限公司 | Driving circuit of display panel and driving module thereof, and display device and method for manufacturing the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114115411A (en) * | 2021-05-12 | 2022-03-01 | 友达光电股份有限公司 | Voltage modulation circuit and operation method thereof |
| TWI770999B (en) * | 2021-05-12 | 2022-07-11 | 友達光電股份有限公司 | Voltage adjust circuit and operation method thereof |
| US11558043B2 (en) | 2021-05-12 | 2023-01-17 | Au Optronics Corporation | Voltage adjust circuit and operation method thereof |
| CN114115411B (en) * | 2021-05-12 | 2023-02-28 | 友达光电股份有限公司 | Voltage modulation circuit and operation method thereof |
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| CN110580877A (en) | 2019-12-17 |
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