TWI571961B - 層疊封裝微電子組件之批次處理製程 - Google Patents

層疊封裝微電子組件之批次處理製程 Download PDF

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Publication number
TWI571961B
TWI571961B TW104109641A TW104109641A TWI571961B TW I571961 B TWI571961 B TW I571961B TW 104109641 A TW104109641 A TW 104109641A TW 104109641 A TW104109641 A TW 104109641A TW I571961 B TWI571961 B TW I571961B
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Taiwan
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conductive
microelectronic
component
support
layer
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TW104109641A
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TW201539661A (zh
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貝勒卡塞姆 哈巴
依利亞斯 ***
良 王
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英凡薩斯公司
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Description

層疊封裝微電子組件之批次處理製程
本發明係關於一種微電子元件之封裝，特別是一種半導體晶片之封裝。
微電子元件通常包含半導體材料所製成之薄板，例如矽或砷化鎵，此薄板通常被稱為晶粒或半導體晶片。半導體晶片通常提供作為個別的預封裝單元。在一些單元的設計中，半導體晶片係安裝於基板或晶片載體上，並接著一起安裝於電路板上，例如印刷電路板。
主動電路係設置於半導體晶片之第一表面(例如前表面)上。為了利於電性連接主動電路，在晶片相同的表面上提供焊接墊。焊接墊通常係以一規則陣列圍繞晶粒之邊緣設置，或針對許多記憶體裝置，設置於晶粒中心上。焊接墊通常係由一導電金屬製成，例如銅或鋁，其厚度大約為0.5微米(μm)。連接墊可包含單層或多層金屬。連接墊之大小將隨裝置類型而改變，但在裝置之一側上所量測到的連接墊之大小通常介於幾十微米到幾百微米之間。
微電子元件(例如半導體晶片)通常需要許多輸入以及輸出，以連接至其他的電子元件。半導體晶片或其他類似裝置的輸入以及輸出接觸部通常係以網格圖案設置，其大致覆蓋晶片之表面(通常被稱為“區域陣列(area array)”)，或者以延長列設置，其可平行於以及相鄰於晶片之前表面之各邊緣進行延伸或設於前表面之中心處。半導體晶片係通常包在封裝內，以利於此半導體晶片在製造期間以及在安裝晶片於外部基板上(例如電路板或其他的電路面板)的期間的處理。例如，許多半導體晶片係設在封裝內以適用於表面安裝技術。一般型態的封裝已大量地被提出於各種應用中。此類封裝包含介電元件，其通常被稱為具有多個端部的“晶片載體”，這些端部係在介電質上形成作為電鍍的或蝕刻的金屬結構。這些端部通常藉由元件，例如沿著其晶片載體延伸的細跡線，以及藉由在晶片之接觸部以及端部或跡線之間延伸的細導線或電線，以連接其晶片之接觸部。在一表面安裝作業中，封裝體係設置於一電路板上，使得封裝上的各端部係對準電路板上相對應的接觸墊。在端部以及接觸墊之間係提供焊料或其他接合材料。封裝可藉由加熱組件而永久地接合於位置上，以便熔化或“回流”焊料或者激活接合材料。
許多封裝體包含呈焊料球體形態之焊料塊，其直徑通常介於大約0.1mm以及大約0.8mm(5以及30mils)之間，並附著於封裝體之端部上。若一封裝具有突出於其底面的一焊料球體陣列，此封裝通常被稱為一球柵陣列或“BGA”封裝。其他封裝，例如被稱為平面柵格陣列或“LGA”封裝，係藉由焊料所形成的薄層或焊盤，而固定於基板上。此型態的封裝可以是相當薄的。通常被稱為“晶片級封裝”的特定封裝，其佔據電路板之 一區域，此區域的大小係相同於或僅稍微大於整合於封裝內的裝置之面積。此種封裝的優勢係在於，減少組件之整體大小以及允許基板上各裝置之間使用短互連，並進而限制裝置之間的訊號傳輸時間，因此有利於組件高速運作。
封裝的半導體晶片時常以“堆疊”排列，例如一封裝係提供於一電路板上，以及另一封裝係安裝於第一封裝之頂部上。這些排列可允許一定數量的不同晶片被安裝於電路板上的一單一腳位內，並可藉由在封裝之間提供一短互連，而能以高速運作。通常，此互連的距離係僅稍微大於其晶片之厚度。在一晶片封裝之堆疊內實現互連，必須在各封裝(除了最上層的封裝)之兩側上提供用於機械以及電性連接的結構。此動作執行，例如藉由在安裝晶片的基板之兩側上提供接觸墊或焊盤，墊片係藉由導電孔或其相似物而連通基板。公開號為2010/0232129的美國專利係提供堆疊的晶片排列以及互連結構之示例，此公開內容通過引用併入本文。
在晶片任何的實體排列中，必需考量晶片的大小。隨著可攜式電子裝置的快速發展，晶片強烈地需要更緊密的物理排列。僅透過舉例的方式，通常被稱為“智慧型手機”的可攜式裝置以及平板電腦的行動裝置，係整合強大的資料處理器、記憶體以及輔助設備(例如全球定位系統接收器、電子攝影機以及區域網路連接高解析度裝置及相關聯的影像處理晶片)的功能。此類裝置可提供多種功能，例如完整的網路連接、包含全解析度視訊、導航、電子銀行的娛樂以及更多內建於口袋大小的裝置的功能。複雜的可攜式裝置需要將大量的晶片封裝至一小空間內。此外，一些晶片係具有許多輸入以及輸出連接部，通常被稱為“I/O”。這些I/O必須互連其 他的晶片的I/O。互連應為短的以及應具有低阻抗，以最小化訊號傳輸延遲。元件間形成互連不應大量增加組件的尺寸。在其他應用中出現類似的需求，例如在資料伺服器內，例如互連使用於網路搜尋引擎。例如，在複雜的晶片之間提供大量短的、低阻抗的互連的結構可增加搜尋引擎的頻寬以及減少其功率消耗。
儘管已取得諸多進步，更進一步的改善可提升具有堆疊端部的微電子封裝的結構以及提升製造此類封裝的處理。
根據本發明之另一態樣的微電子組件可包含第一支撐元件以及第二支撐元件，第一支撐元件以及第二支撐元件皆具有面向組件之一向外方向的一第一表面以及面向組件之一向內方向的一第二表面，此向內方向係指朝向第一支撐元件或第二支撐元件之另一個之第二表面的方向。微電子組件可具有：位於第一支撐元件之第一表面上的第一端部以及位於第二支撐元件之第一表面上的第二端部中的至少一個。在第一支撐元件之第二表面上，可提供第一導電元件。感光材料製成之一圖案層可覆蓋第一支撐元件之第二表面，並具有對準第一導電元件的開孔。在一示例中，開孔可具有一截面尺寸，此截面尺寸係為固定或隨第一支撐元件之第二表面之一高度增加。接合材料製成之導電塊可電性耦接第一導電元件，並通過圖案層相對應之開孔而突出於第一導電元件上方。導電塊可具有一截面尺寸，導電塊之截面尺寸係由導電塊相對應的開孔之一截面尺寸的投射而定義。微電子元件可安裝於第一支撐元件或第二支撐元件之第二表面上。第 二導電元件可設置在第二支撐元件之第二表面上，此第二導電元件可電性耦接導電塊以及透過導電塊電性耦接第一導電元件。密封體可覆蓋第二支撐元件之第二表面、圖案層之一表面，並可接觸至少一些導電塊，這些導電塊係延伸通過密封體之至少一部分。在一具體示例中，延伸通過密封體之至少一部分的導電塊可具有球狀部分。
根據本發明之另一態樣，提供一種堆疊多晶片微電子組件可包含微電子組件以及覆蓋第一支撐元件之第一表面的一微電子封裝，微電子封裝係具有與微電子組件之第一端部相連接的複數個端部。
根據本發明之一具體態樣，提供一種堆疊多晶片微電子組件可包含微電子組件，並具有第二端部，但不具有第一端部。第二端部可通過其間之複數個導電塊而電性耦接第一導電元件。
根據本發明之另一態樣，提供一種製造微電子組件之方法可包含接合第一子組件以及第二子組件，以形成一組件。組件可包含一第一支撐元件以及一第二支撐元件，此第一支撐元件係具有面向一第一方向的一第一外表面，第二支撐元件係具有面向與第一方向相反的一第二方向的一第一外表面。第一支撐元件可具有位於其一第二內表面上之第一導電元件，第二支撐元件可具有位於其一第二內表面上之第二導電元件，至少一微電子元件可安裝覆蓋第一支撐元件以及第二支撐元件之其中一個的第二表面。組件更可包含感光材料製成之一圖案層，其係覆蓋第一支撐元件或第二支撐元件之第二表面，並具有開孔，開孔係具有截面尺寸，此截面尺寸係為固定或隨著距離圖案層所在之支撐元件之表面之高度而增加。組件更可包含接合材料製成之導電塊，導電塊係從第一導電元件通過開孔進行 延伸，並電性耦接第二導電元件，此導電塊係具有由開孔之截面尺寸所定義之一截面尺寸。
在形成組件之後，可在第一子組件以及第二子組件之間的一空間中流入一密封材料，以形成與導電塊之至少一部份之複數個表面相接觸的一密封體。
根據此方法，此組件可包含位於第一支撐元件之第一表面上的第一端部以及位於第二支撐元件之第一表面上的第二端部，第一端部係透過第一元件、第二元件及其間的導電塊而電性耦接第二端部。
此外，根據此方法，組件可包含下列元件中其中一種：第一端部，係位於第一支撐元件之第一表面上，並透過其間之複數個導電塊電性耦接第二導電元件；第二端部，係位於第二支撐元件之第一表面上，並透過其間之複數個導電塊電性耦接第一導電元件。
根據本發明之一具體態樣，方法更可包含沉積由感光材料所製成的一第一層以及沉積一臨時層以形成圖案層，沉積臨時層之步驟包含由感光材料製成之第二層、光刻圖案化臨時層以形成孔洞、使用經圖案化之臨時層圖案化第一層，以根據臨時層內之孔洞形成開孔，接著使用導電塊填充開孔，再接著移除臨時層，使得導電塊突出於支撐元件之第二表面上方一高度，此一高度係大於第一層之高度。
10‧‧‧微電子組件
14‧‧‧組件
16‧‧‧導電接合元件
20‧‧‧微電子組件
101‧‧‧第一表面
102‧‧‧第一支撐元件
103‧‧‧第二表面
104‧‧‧第二支撐元件
105‧‧‧背面
106‧‧‧第二表面
108‧‧‧電路板
110‧‧‧板級組件(Board level assembly)
112‧‧‧表面
120‧‧‧微電子元件
124‧‧‧接觸部
124'‧‧‧接觸部
127‧‧‧表面
129‧‧‧表面
130‧‧‧圖案層
131‧‧‧表面
132‧‧‧第一導電元件
133‧‧‧開孔
134‧‧‧截面尺寸
135‧‧‧開孔
136‧‧‧導電塊
138‧‧‧球狀部分
141‧‧‧第一端部
142‧‧‧第二端部
144‧‧‧接觸部
146‧‧‧接合元件
150‧‧‧密封體
152‧‧‧導電元件
154‧‧‧配線
162‧‧‧厚度
164‧‧‧臨時層
165‧‧‧表面
166‧‧‧厚度
168‧‧‧側向尺寸
170‧‧‧第一子組件
172‧‧‧第二子組件
174‧‧‧微電子組件
176‧‧‧第二密封體
178‧‧‧第一橫向方向
179‧‧‧第二橫向方向
180‧‧‧第一表面的方向
180'‧‧‧方向
220‧‧‧第二微電子元件
224‧‧‧接觸部
224'‧‧‧接觸部
500‧‧‧系統
501‧‧‧殼體
502‧‧‧電路板
504‧‧‧導體
506‧‧‧結構
508‧‧‧電子元件
510‧‧‧電子元件(螢幕)
511‧‧‧透鏡
a‧‧‧最小間距
b‧‧‧最小間距
c‧‧‧最小間距
H‧‧‧高度
本發明之上述及其他特徵及優勢將藉由參照附圖詳細說明其例示性實施例而變得更顯而易知，其中：
第1圖為本案較佳實施例之微電子組件之剖面圖。
第1A圖為第1圖之微電子組件之一態樣之一局部剖面圖。
第2圖為本案較佳實施例之微電子組件之一剖面圖，此微電子組件係耦接另一裝置，例如電路板。
第3圖為本案較佳實施例之一堆疊多晶片組件之一剖面圖，此堆疊多晶片組件包含彼此電性耦接的複數個堆疊微電子組件，例如第1圖之微電子組件。
第4圖為本案較佳實施例之微電子組件之一剖面圖，本實施例係為第1圖之變化型。
第5圖至第12圖為本案較佳實施例之微電子組件之製造階段之剖面圖，其中：第6圖為第5圖之階段的下一階段；第7圖為第6圖之階段的下一階段；第8圖為第7圖之階段的下一階段；第9圖為第8圖之階段的下一階段；第10圖為第9圖之階段的下一階段；第11圖為第10圖之階段的下一階段；以及第12圖為本案較佳實施例之製造微電子組件之一方法中的一階段，本實施例為第6圖至第11圖之實施例之一變化型。
第13圖為本案較佳實施例之製造一微電子組件之一方法中的一階段，此方法為第5圖至第12圖之方法之一變化型。
第14圖為本案較佳實施例之一微電子封裝或組裝更進一步地整合於以 及使用於一系統中之一剖面圖。
因此，本發明之實施例可提供改善的組件，其包含微電子元件，並具有第一端部以及第二端部，例如頂端部以及底端部，其中垂直互連線係電性耦接頂端部以及底端部，並提供期望的間隔高度，同時，在平行於組件中的微電子元件之一表面的水平方向上，也允許以期望的間距緊密地包裝此垂直互連線。請參閱第1圖所示之微電子組件10或微電子封裝，在一示例中，在平行於第一支撐元件之第二表面的至少一方向上，在複數個支撐元件之複數個第二表面之間的一間隔高度H係大於接合材料製成之複數個導電塊136之間的一最小間距“a”的一半。在其他示例中，間隔高度可相同於或大於此最小間距a，或可相同於或大於此最小間距a的1.5倍。
如第1圖所示，微電子封裝10包含一第一支撐元件102以及一第二支撐元件104。支撐元件可例如為封裝基板，例如晶片載體或介電元件或由介電材料、半導體材料以及導電材料中至少兩種所組合的結構，可例如提供端部、跡線、接觸點以及透孔等導電結構。例如，一或二支撐元件可以為或包含一片狀或一板狀的介電元件，此介電元件包含無機或有機介電材料，並可主要包含無機材料或主要包含高分子材料，或可以為包含無機材料以及高分子材料的一複合結構。因此，例如但不限制為，一或二支撐元件可包含一介電元件，此介電元件包含高分子材料，例如聚酰亞胺、聚酰胺、環氧樹脂、熱塑性材料、熱固性材料等。或者，一或二支撐元件可包含一介電元件，此介電元件包含一無機介電材料，例如氧化矽、氮化 矽、碳化矽、氮氧化矽、氧化鋁，一或二支撐元件可包含一半導體材料，例如矽、鍺或碳等或至少一此類無機材料的一組合。在另一示例中，一或二支撐元件可包含一介電元件，此介電元件係為至少一高分子材料以及至少一無機材料的一組合，例如上述的材料。在多個具體示例中，一或二支撐元件可具有一玻璃強化環氧樹脂結構，例如通常被稱為“FR 4”或“BT樹脂”的板結構。例如，在另一示例中，一或二支撐元件實質上可由高分子材料組成，例如聚酰亞胺。一或二支撐元件可包含至少一柔性材料層，在一些情況下，此至少一柔性材料層可曝露於此類支撐元件的第一表面、第二表面或兩者上。在一些情況下，柔性材料可包含聚酰亞胺或聚酰胺，其通常具有小於2.0吉帕斯卡(“GPa”)的楊氏模量，或者，在一些情況下，彈性材料可包含具有一楊氏模量的一彈性體，此楊氏模量係明顯較低，例如低於1.0GPa。
如第1圖所示，各支撐元件係具有相反的第一表面以及第二表面。如微電子組件10或微電子封裝內的組裝所示，支撐元件之第一表面101與105皆面向外側且彼此背對，第二表面103與106皆面向內側且彼此面對。微電子元件120可以為一未封裝的或封裝的半導體晶片，其係安裝於一或二支撐元件102或104之第二表面上。在一具體實施例中，微電子元件可以為一半導體晶片，在其表面上具有耦接晶片之墊片的額外的導電結構。雖未顯示於圖中，在一實施例中，第二微電子元件可安裝於背對支撐元件104的微電子元件120之表面129上方的一空間內。第二微電子元件可設置於第一支撐元件102之表面129以及表面103之間。第二微電子元件可安裝於第一支撐元件102之表面103上，並電性耦接第一導電元件132。此外，第二微 電子元件可電性耦接位於第二支撐元件104之表面106上的導電元件。在第二微電子元件之至少一邊緣表面或一表面上，可提供一第二密封體(未顯示於圖中)，或此第二密封體可覆蓋第二微電子元件之至少一邊緣表面或一表面。
在一具體實施例中，特別是，當第一支撐元件102之第二表面103上具有第一導電元件132時，第一支撐元件102可被稱為“中介層”，此第一導電元件132係以不同的圖案設置，例如相較於在中介層102之第一表面上的一組第一端部141，設於不同的位置或以不同的間距設置。如第1圖所示，在一示例中，第一導電元件132之一最小間距“a”可顯著地小於第一端部141之一最小間距“b”。第一端部141可具有相同於或不同於在微電子組件10之背面105上的第二端部142之最小間距“c”的一最小間距“b”。可使用第一端部141以及第二端部142有具有相同間距的背面，例如，如第3圖所示，高階組件包含彼此堆疊且電性耦接的複數個微電子組件10。
如本公開內容中所使用之一元件，例如中介層、微電子元件、電路板、基板等，導電元件係“位於”一裝置之一表面上的描述係意指，當元件不與任何其他元件組裝時，導電元件可與一理論點相接觸，此理論點係在垂直於元件之表面的一方向上，從裝置外側朝向裝置之表面移動。因此，在一基板之一表面上，端部或其他導電元件可突出於此表面；可與此表面齊平；或可相對凹於基板之表面上形成一孔洞或一凹陷。在一示例中，元件之“表面”可以為介電結構之一表面；然而，在多個具體實施例中，表面可以為其他材料之一表面，例如金屬或其他導電材料或半導 體材料。
在第1圖中，平行於第一支撐元件之第一表面101的方向被稱為第一以及第二橫向方向178與179或“水平”或”側向”方向，而垂直於第一表面的方向180被稱為向上的或向下的方向，亦被稱為“垂直”方向。本文所指的方向係為所稱之結構之參考框中的方向。因此，這些方向可以為參考框所導引的正常方向或重力方向。相較於另一形體，一形體設置於“一表面上方”一較大高度的敘述係意指在相同的正交方向上，相較於其他形體，一形體與此表面之間係具有一c距離。相反地，相較於另一形體，一形體設置於“一表面上方”一較小高度的敘述係意指，在相同的正交方向上，相較於其他形體，一形體與此表面之間係具有一較小距離。
請參閱第1圖，微電子元件120之一承載接觸前接觸乘載面可朝下面對第二支撐元件104之第二表面106，位於微電子元件之前表面上的接觸部124可面對並電性耦接在第二支撐元件之表面106上相對應的接觸部，例如申請日為2013/7/15、公開號為13/942,568之美國專利之第1A圖所，其公開內容併入本文。在一具體示例中，引用申請日2012/4/4、公開號13/439,299(在下文中，公開號為299)之美國專利之併入本文的公開內容，接觸部能以一區域陣列分佈於微電子元件之前表面之至少一部分上，此區域陣列係具有至少二列接觸部以及至少二行接觸部。底層填料可設置於微電子元件之前表面以及第二支撐元件之第二表面106之間，底層填料係圍繞個別的連接部，在一些情況下，底層填料可機械地強化連接部。微電子元件120之接觸部124可電性耦接位於第二支撐元件之第一表面105上的導電的第二端部142。在此示例中，接觸部124可藉由一覆晶連接，以電性耦接位 於面向接觸部124的第二表面106上的相對應的接觸部，亦即藉由一接合金屬，例如錫、銦、焊料或共晶材料或由嵌入於一高分子材料內的金屬粒子構成的一導電基質材料。
此外，替代一覆晶連接，位於朝向前表面下的方向上的接觸部(未顯示於圖中)可改為排列於至少一列為接觸部及/或至少一行為接觸部內的位置上，這些接觸部係對準孔洞或“接合窗”(未顯示於圖中)，並在支撐元件104之第一表面以及第二表面105與106之間進行延伸。在此情況下，微電子元件之接觸部124可通過與接觸部相接合的引線而耦接第二端部142，例如，如第1A圖至第1C圖、第5B圖至第5C圖以及第9A圖至第15圖中的至少一圖所示，這些附圖相對應的實施例係引用申請日為2011/11/29、公開號13/306,068的美國專利，其係併入本文。在一具體示例中，引線可以為導線(未顯示於圖中)，例如打線接合部，其係延伸通過孔洞與接觸部相接合以及與位於第一表面105上的相對應的接觸部(未顯示於圖中)相接合。在另一示例中，這些引線可以為包含一第一部分以及一第二部分的導線，此第一部分係作為一跡線以沿著第一表面或第二表面105或106延伸，此第二部分係整合第一部分，並從跡線延伸至孔洞之區域內，以接合接觸部。
在另一示例中，未顯示於圖中，微電子元件之後表面可向後接合於第二支撐元件之第二表面106，微電子之前(接觸承接)表面可不背對支撐元件104之第一表面106，而微電子元件之接觸部124’係背對第二表面106。在此示例中，接觸部124’可藉由導電結構以電性耦接位於第二表面106上的相對應的接觸部，此導電結構電係在接觸部124’之接觸承接表面129上方進行延伸。例如，打線接合部、導線、帶狀接合線等可用以提供導 電互連。
如第1圖所示，微電子封裝10可包含感光材料所製成之一圖案層130，此圖案層130係具有位於第一支撐元件之第二表面103上方一高度處的一表面131。如第1圖所示，圖案層130係具有開孔133，其對準位於第一支撐元件102之第二表面103上的相對應的第一導電元件132。請參閱第1A圖，開孔係具有一截面尺寸134，此截面尺寸134係為固定或為僅隨距離第一支撐元件之第二表面103之高度而增加。
如第1圖所示，接合材料所製成之導電塊136係電性耦接第一導電元件132，並通過圖案層之相對應的開孔133遠離第一導電元件132突出。在一示例中，導電塊可包含一接合金屬，例如錫、銦、焊料或共晶材料。在其他示例中，導電塊可包含由嵌入於一高分子材料內的金屬顆粒所構成之導電基質材料。在一示例中，在微電子組件之一垂直方向180上，導電塊可具有介於20以及500微米(micrometer)(在下文中為“microns”)之間的一垂直高度。在平行於第一支撐元件之表面103所延伸的此平面的第二方向178或179上，各柱狀物之垂直尺寸係大於相鄰的第一導電元件132之“最小的中心間距“a”的一半。
在圖案層130內，導電塊136係具有一截面尺寸134，其係藉由相對應的開孔133之一截面尺寸的投影而定義。因此，導電塊136之截面尺寸係為固定或僅隨圖案層130內的至少一高度而增加。導電塊係突出於圖案層130之表面131上方，並與位於第二支撐元件之表面106上的相對應的第二導電元件152相接合。如第1圖所示，導電塊136可具有球狀部分138，並在圖案層之表面131以及第二導電元件152之間進行延伸。
如第1圖所示，密封體150可與第二支撐元件104之第二表面106形成相接觸，並可與圖案層之表面131以及導電塊136之表面形成相接觸。在一實施例中，密封體150可形成與邊緣表面127以及微電子元件120之主表面129相接觸。此外，密封體150可與覆蓋邊緣表面127的至少一材料層(未顯示於圖中)形成相接觸，及/或可與覆蓋微電子元件129之主表面129的至少一材料層(未顯示於圖中)形成相接觸，使得密封體150係覆蓋但不接觸微電子元件129之邊緣表面127、主表面129或兩邊緣表面以及主表面。在一示例中，至少一材料層可以為或可包含一第二密封體，此第二密封體係覆蓋微電子元件120之至少一主表面129以及至少一邊緣表面127。
密封體150可包含一高分子材料或實質上由一高分子材料構成。製造密封體的材料可例如為灌注化合物、環氧樹脂、液晶聚合物、熱塑性塑膠以及熱固性聚合物。在一具體示例中，密封體可包含高分子基質以及在高分子基質內的顆粒狀裝載材料，例如藉由模塑成型或沉積具有顆粒狀裝載材料的一未固化高分子材料於圖案層130之表面131上而形成。在一示例中，顆粒狀裝載材料可選擇性具有一低熱膨脹係數("CTE")，使得產生的密封體150可具有低於每攝氏度百萬分之十(parts per million per degree Celsius," "ppm/℃")的一CTE。在一示例中，密封體可包含一填充材料，例如玻璃或陶瓷介電填充物或半導體填充物等。
在實施例的任何或所有的變化型中，微電子組件10中可省略複數個第一端部或第二端部。在此情況下，第一導電元件可通過導電塊136電性耦接第二端部，此導電塊136係設置於第一導電元件以及第二端部之間，或第二導電元件可透過導電塊136電性耦接第一端部，此導電塊136係 設置於第二導電元件以及第一端部之間。在上述實施例的任何或所有的變化型中，微電子元件120可安裝於第一支撐元件102之表面103上，而非安裝於第二支撐元件104之表面106上。
第2圖係根據上述包含微電子組件10或封裝的一板級組件110(Board-level assembly)以及在其表面112上具有接觸部144的電路板108，此接觸部144係透過導電塊136對準以及接合微電子組件10之第二端部142。接合元件可包含至少一導電塊146，例如上述與導電塊136相連接的材料，或可包含導電的固體金屬柱狀物，例如具有實質上由銅組成的單片金屬區域的柱狀物，其通常為圓柱形或平截頭圓錐形，而當從橫截面看時，則通常為矩形或梯形。
第3圖為複數個微電子封裝10之一組件14，其中複數個微電子組件10或複數個封裝係彼此堆疊，並透過個別的第一端部141、與其對準的複數個第二端部142以及複數個導電接合元件16使彼此電性耦接，此導電接合元件16係接觸個別成對的第一端部以及第二端部。請參閱第2圖，如上所述，微電子組件10可具有耦接電路板108之接觸部的第二端部142。
請參閱第4圖，根據上述的組件10之一變化型，在微電子組件20或封裝中，提供第二微電子元件220覆蓋第一支撐元件102之第一表面101，微電子組件20中可省略第一端部。第二微電子元件220可透過提供於第一支撐元件102上的配線154以及透過導電塊136，以電性耦接第二導電元件152。第二微電子元件220可透過配線154、導電塊136以及第二導電元件152，以電性耦接第二端部142。在另一變化型中(未顯示於圖中)，微電子組件20中可省略第二端部，而第一端部通常額外地提供至位於第二支撐元件 102之表面101上的配線154內。在此情況下，第二微電子元件220可電性耦接(例如在第1圖中的位置上的)第一端部，且係透過提供至第一支撐元件102以及導電塊136上的配線154將兩者電性耦接。
請參閱第5圖至第12圖，說明根據本發明之一實施例之製造微電子組件之一方法。如第5圖所示，提供第一支撐元件102或中介層，其特徵如上所述。如第6圖所示，提供感光材料所製成之第一層130覆蓋第一支撐元件102之第二表面103。在一示例中，感光材料可以為一負形光阻材料，例如SU8，更具體地說，感光材料可以為一材料，例如SU8 2150，其可具有介於約20微米至650微米之範圍內的厚度162，感光材料藉由適當處理(例如在圖案化之後，進行熱處理或射線處理)而相交聯時將成為一永久層。製成第一層的感光材料，例如SU8，可施加於第二表面103上，或藉由旋轉塗佈法或滾筒塗佈法，以覆蓋支撐元件之第二表面103。在一實施例中，厚度162可以為200微米。在施加第一層130之後，感光材料所製成之一臨時層164係施加至表面131上或覆蓋第一層之表面131。在一示例中，臨時層可以為一乾膜，其在圖案化之後被移除。臨時層164之厚度166可介於50微米以及300微米的範圍內。在一示例中，厚度166可以為100微米。
隨後，如第7圖所示，臨時層164係藉由光刻進行圖案化，以在其內形成孔洞。孔洞可接著用以圖案化第一層130，例如藉由蝕刻或光刻，以在其內形成對準臨時層內的圖案的開孔133，其中第一導電元件132之表面係至少部分地曝露於開孔133內。在一示例中，在方向178與179(第1圖)上，開孔133之側向尺寸168係為固定或僅在方向180’上增加，此方向180’係指從第一導電元件132上方延伸至臨時層之表面165。在同一時間 形成開孔133，或在不同的時間，相同或相似的處理可用於在臨時層164以及第一層130上形成一較大開孔135，開孔135在方向178與179上係具有大於微電子元件120(第1圖)之側向尺寸，使得開孔135至少部分地容納微電子元件120。
在第8圖所示的層級中，導電材料所製成之導電塊136可填滿開孔133，例如金屬膏或金屬薄片或金屬顆粒材料，此材料係受到回焊或其他足夠將材料硬化的熱處理，以混合至少一焊劑、溶劑或其他揮發性物質。在多個具體示例中，材料可為，但不受限為，包含焊料、錫、銦、銀、金或銅的顆粒的一膏狀物。在另一示例中，材料可以為永久性固化的或硬化的一導電材料。在一示例中，開孔133可使用具有越過臨時層164之表面165的一前端的一工具執行網版、模版或點膠法，以將一導電膏填滿開孔133。
第9圖為當在結構中的一選擇性階段中沉積一回焊材料時，係進行加熱以導致在開孔133內由導電材料所製成之導電塊136回焊。此外，導電材料係為一永久性固化的或硬化的導電材料時，必要時可施加一定量的烘乾或加熱，以部分地固化材料。在一示例中，此固化的導電材料可部分地藉由加熱至一溫度而固化，此溫度係低於導電材料所包含的一高分子材料之一玻璃轉換溫度。此外，在上述處理的一變化型中，可例如藉由批次處理，以注入熔融狀態的一接合金屬至開孔133內而填充此開孔133，例如焊料、錫、銦或共熔混合物。
請參閱第10圖，可移除臨時層，使得導電塊136部分突出於第一層130之表面131上方。在一示例中，臨時層係藉由溶解被移除，例如選擇性地沖洗或蝕刻第一層130之材料。在一示例中，第一組件170包含支 撐元件102、其上的第一層130以及導電材料所製成的導電塊136，此導電塊136係突出於第一層之表面131上方，並待用於具有另一元件的另一組件。因此，如第11圖所示，導電材料所製成的導電塊136係對準相對應的第二導電元件152，此第二導電元件152係位於第二組件172之第二支撐元件104之表面106上。在第一層130內的開孔135係對準微電子元件120。接著，第一子組件170以及第二子組件172可聚在一起，使得導電塊136係與第二導電元件152相接觸或彼此相鄰。當導電塊136包含一回焊材料時，導電塊136可接著被回流與具有第1圖所示的第二導電元件152相連接，其中導電塊136之球狀部分係出現於第一層之表面131上方。此外，由固化的或硬化的材料所製成的導電塊136在與第二導電元件152相接觸後可被固化或硬化，以在兩者之間形成永久的連接。
請參閱第12圖，在上述處理的一變化型中，在第一子組件170以及第二子組件172組裝之前，可加熱具有經回焊的導電塊136的第一組件170至一回焊溫度。在此方法中，導電塊突出於第一層的表面131上方的部分可被回焊，以形成球狀部分138。更進一步，可接著實施第一子組件以及第二子組件的組裝，例如藉由將導電塊136對準相對應的第二導電元件152以及將開孔135對準微電子元件120，以形成微電子組件10(第1圖)，導電塊所攜帶的球狀部分138係與第二導電元件152相接觸，並接著回焊至少一球狀部分138，以在導電塊136以及第二導電元件152之間形成連接。
隨後，請一併參閱第1圖，密封體150可使用例如上述的一密封材料而形成。在一示例中，組件10可設置於一模具中，且可在第一子組件以及第二子組件170與172之間的一空間內注入一密封材料，而使得密封 材料接觸導電塊136之表面，此表面可以為導電塊之直線部分或球狀部分138。密封材料可接觸感光材料所製成的第一層之表面131，並可接觸第二支撐元件之第二表面106。密封材料可接觸微電子元件120之表面127與129。當組裝仍在模具內或密封材料藉由隨後的處理進行固化時，密封材料全部或部分的固化可能受到影響。在一示例中，針對本文所描述的任何或所有微電子組件10與20，如第13圖所示，在第一子組件以及第二子組件170與172組裝之前，第二密封體176可部分地或完全地覆蓋微電子元件120之表面127與129，以形成組件20。密封體150可與微電子元件120形成相接觸，及/或與形成於微電子元件120之一表面上的第二密封體176相接觸。
第13圖係根據上述處理之一變化型之製造第4圖所示之微電子組件20之一階段。如第13圖所示，微電子組件174可包含第一支撐元件102以及安裝於表面101上的微電子元件220，此表面101係面向其待建構的組件20之一向外方向。微電子元件220之接觸部224及/或224’可透過第一支撐元件102上的配線154以及透過第一導電元件132，以電性耦接導電材料所製成之導電塊136。接著，能以例如在第11圖或第12圖所述之一方式，將導電塊136對準以及接合在第二組件上的相對應的第二導電元件152。更進一步，形成一密封體150的處理能以上述之一方式執行。
上述的結構提供特殊的三維互連功能，而這些功能可用於任意型號的晶片。僅透過舉例的方式，上述的結構可包含下列的晶片的結合：(i)一處理器以及適用於此處理器的記憶體；(ii)相同類型的複數個記憶體晶片；(iii)不同類型的複數個記憶體晶片，例如DRAM以及SRAM；(iv)適用於處理來自感測器的影像的一影像感測器以及一影像處理器；(v)一特定應用 的積體電路("ASIC")以及記憶體。上述的結構可應用於各種的電子系統的結構中。例如，請參閱第14圖，根據本發明之另一實施例之系統500，其包含上述與其他電子元件508與510相結合的一結構506。在所繪示的示例中，元件508係為一半導體晶片，元件510係為一顯示螢幕，但也可使用其他任意的元件。當然，雖然第14圖僅為兩個外加元件以明確地說明本發明之系統，但不受限於此，系統可包含任意數量的此類元件。上述的結構506可例如為前述的一微電子封裝，或可以為第1圖、第2圖、第3圖或第4圖中所述的一微電子組件。如示意性繪示的虛線，結構506以及元件508與510係安裝於一共用殼體501上，且彼此電性互連，以形成期望的電路。如示例性系統所示，系統包含一電路板502，例如可撓性印刷電路板，電路板包含大量的導體504，在第14圖中僅其中之一導體504，其用以將複數個元件彼此互連。然而，這僅為示例性；可使用任何適用於製造電性連接的結構。殼體501係為一可攜式殼體型態以及一螢幕510，此可攜式殼體型態可例如使用於行動裝置或個人數位助理中，此螢幕510係曝露於殼體之表面上。結構506包含一光敏元件，例如影像晶片、透鏡511或其他也可發送光線至結構上的光學裝置。同樣地，第14圖僅示例性的簡化系統；其他系統，可包含通常被稱為固定結構的系統，可例如使用上述的結構以製造桌上型電腦、路由器以及其相似物。
本發明之優點、特徵以及達到之技術方法將參照例示性實施例及所附圖式進行更詳細地描述而更容易理解，且本發明或可以不同形式來實現，故不應被理解僅限於此處所陳述的實施例，相反地，對所屬技術領域具有通常知識者而言，所提供的實施例將使本揭露更加透徹與全面且 完整地傳達本發明的範疇，且本發明將僅為所附加的申請專利範圍所定義。
以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。
10‧‧‧微電子組件
101‧‧‧第一表面
102‧‧‧第一支撐元件
103‧‧‧第二表面
104‧‧‧第二支撐元件
105‧‧‧背面
106‧‧‧第二表面
120‧‧‧微電子元件
124‧‧‧接觸部
127‧‧‧表面
129‧‧‧表面
130‧‧‧圖案層
131‧‧‧表面
132‧‧‧第一導電元件
133‧‧‧開孔
136‧‧‧導電塊
138‧‧‧球狀部分
141‧‧‧第一端部
142‧‧‧第二端部
150‧‧‧密封體
152‧‧‧導電元件
178‧‧‧第一橫向方向
179‧‧‧第二橫向方向
180‧‧‧第一表面的方向
a‧‧‧最小間距
b‧‧‧最小間距
c‧‧‧最小間距
H‧‧‧高度

Claims (29)

  1. 一種微電子組件，包含：複數個第一支撐元件(First Support Elements)以及複數個第二支撐元件(Second Support Elements)，各該第一支撐元件以及各該第二支撐元件皆具有面向該微電子組件之一向外方向的一第一表面，以及具有面向該微電子組件之一向內方向的一第二表面，該向內方向係指朝向其他該第一支撐元件及該第二支撐元件之該第二表面之方向，而包含：在各該第一支撐元件之該第一表面上係具有複數個第一端部，或在各該第二支撐元件之該第一表面上係具有複數個第二端部；複數個第一導電元件(Electrically Conductive First Elements)，係位於各該第一支撐元件之該第二表面上；感光材料製成之一圖案層(Pattern Layer)，係覆蓋該第一支撐元件之該第二表面，並具有對準該第一導電元件之複數個開孔，各該開孔係具有一截面尺寸，該截面尺寸係為固定或隨著距離該第一支撐元件之該第二表面之一高度而增加；接合材料製成之複數個導電塊(Electrically Conductive Masses)，係電性耦接該複數個第一導電元件，並通過該圖案層相對應之該開孔而突出於該複數個第一導電元件上方，各該導電塊係具有一截面尺寸，該截面尺寸係由各該導電塊相對應的該開孔之一截面尺寸的投射而定義；一微電子元件(Microelectronic Element)，係安裝於該第一支撐元件或該第二支撐元件之該第二表面上； 複數個第二導電元件(Electrically Conductive Second Elements)，係位於該第二支撐元件之該第二表面上，該複數個第二導電元件係電性耦接該複數個導電塊，並透過該複數個導電塊，以電性耦接該複數個第一導電元件；以及一密封體(Encapsulation)，係覆蓋該第二支撐元件之該第二表面、該圖案層之一表面，並接觸至少一些該複數個導電塊，該複數個導電塊延伸通過該密封體之至少一部分。
  2. 如申請專利範圍第1項所述之微電子組件，其中該微電子組件包含該複數個第一端部(First terminals)以及該複數個第二端部(Second terminals)，該複數個第一端部係位於該第一支撐元件之該第一表面上，並通過該複數個第一導電元件、該複數個第二導電元件以及其間之該複數個導電塊電性耦接該複數個第二端部，該複數個第二端部係位於該第二支撐元件之該第一表面上，或該組件包含下列之一者：該複數個第一端部，係位於該第一支撐元件之該第一表面上，並通過其間之該複數個導電塊電性耦接該複數個第二導電元件；或該複數個第二端部，係位於該第二支撐元件之該第一表面上，並通過其間之該複數個導電塊電性耦接該複數個第一導電元件。
  3. 如申請專利範圍第1項所述之微電子組件，其中該複數個導電塊包含複數個球狀部分(Bulbous Portions)，並延伸通過該密封體之至少一部分。
  4. 如申請專利範圍第2項所述之微電子組件，其中該密封體係與該圖案層之該表面以及各該第二支撐元件之該第二表面形成接觸。
  5. 如申請專利範圍第2項所述之微電子組件，其中該微電子元件係具有背對該第二支撐元件之一表面，該密封體係形成一第一密封體，其係與下列至少一者接觸：該微電子元件之該表面，或形成於該微電子元件之表面上的一第二密封體。
  6. 如申請專利範圍第5項所述之微電子組件，其中該微電子組件包含該第二密封體以及該第一密封體，該第二密封體係形成於該微電子元件之該表面上，該第一密封體係與該第二密封體形成接觸。
  7. 一種堆疊多晶片微電子組件，包含如申請專利範圍第2項所述之該微電子組件，以及覆蓋該第一支撐元件之該第一表面的一微電子封裝(Microelectronic Assembly)，該微電子封裝之複數個端部(Terminals)與該微電子組件之該複數個第一端部相連接。
  8. 如申請專利範圍第7項所述之堆疊多晶片微電子組件，其中該複數個第一端部之一最小間距係大於該複數個第一導電元件之一最小間距。
  9. 如申請專利範圍第8項所述之堆疊多晶片微電子組件，其中該複數個第一 端部之該最小間距係相同於該複數個第二端部之一最小間距。
  10. 一種堆疊多晶片微電子組件，包含如申請專利範圍第2項所述之該微電子組件，其中該微電子組件包含該複數個第二端部，但不包含該複數個第一端部，該複數個第二端部係通過其間之該複數個導電塊電性耦接該複數個第一導電元件。
  11. 如申請專利範圍第10項所述之堆疊多晶片微電子組件，更包含一第二微電子元件以及一第二密封體，該第二微電子元件係安裝於各該第一支撐元件之該第一表面上，該第二密封體係與該第一支撐元件之該第一表面及該第二微電子元件之複數個表面(Surfaces)相接觸。
  12. 如申請專利範圍第11項所述之堆疊多晶片微電子組件，其中該第二微電子元件與該複數個第二端部之電性耦接，係透過該複數個第一導電元件及透過電性耦接於其間的該複數個導電塊。
  13. 一種製造微電子組件之方法，包含：接合(Joining)複數個第一子組件(First subassemblies)以及複數個第二子組件(Second subassemblies)以形成一組件(Assembly)，該組件包含一第一支撐元件以及一第二支撐元件，該第一支撐元件係具有面向一第一方向的一第一外表面(Outwardly-facing first surface)，該第二支撐元件係具有面向與該第一方向相反的一第二方向的一第一外表面，該第一支撐元件係具有位於 其一第二內表面(Inwardly-facing second surface)上之複數個第一導電元件，該第二支撐元件係具有位於其一第二內表面上之複數個第二導電元件，至少一微電子元件係安裝覆蓋該第一支撐元件或該第二支撐元件之該第二表面，感光材料製成之一圖案層係覆蓋該第一支撐元件或第二支撐元件之該第二表面，該圖案層係具有複數個開孔，該複數個開孔係具有複數個截面尺寸，該截面尺寸係為固定或隨著距離該圖案層所在之各別支撐元件之表面之高度而增加，該組件更包含接合材料(Bonding Material)製成之複數個導電塊(Masses)，該複數個導電塊係從該複數個第一導電元件各別通過該複數個開孔進行延伸，並各別電性耦接該複數個第二導電元件，該複數個導電塊之複數個截面尺寸，係由該複數個開孔之複數個截面尺寸所定義；以及在該複數個第一子組件以及該複數個第二子組件之間的一空間中流入(Flowing)一密封材料(Encapsulant)，以形成與該複數個導電塊之至少一部分之該複數個表面相接觸之一密封體。
  14. 如申請專利範圍第13項所述之方法，其中：該微電子組件包含複數個第一端部以及複數個第二端部，該複數個第一端部係位於該第一支撐元件之該第一表面上，該複數個第二端部係位於該第二支撐元件之該第一表面上，且該複數個第一端部與該複數個第二端部之電性耦接，係各別透過該複數個第一導電元件、該複數個第二導電元件及其間的該複數個導電塊；或者該微電子組件包含：該複數個第一端部，係位於該第一支撐元件之該第一表面上，並各別透過 其間之該複數個導電塊電性耦接該複數個第二導電元件；或該複數個第二端部，係位於該第二支撐元件之該第一表面上，並各別透過其間之該複數個導電塊電性耦接該複數個第一導電元件。
  15. 如申請專利範圍第13項所述之方法，更包含藉由沉積一第一感光材料層(Photo-imageable material)以及沉積一臨時層(Temporary Layer)以形成該圖案層，沉積該臨時層之步驟包含由感光材料製成該臨時層、光刻圖案化(Photolithographically patterning)該臨時層以形成複數個孔洞(Apertures)、使用經圖案化之該臨時層圖案化該第一層，以根據該臨時層內之該複數個孔洞形成複數個開孔(Openings)，接著用該複數個導電塊填充該複數個開孔，再接著移除該臨時層，使得該複數個導電塊突出之高度，係大於該第一層之一高度，該第一層係位於該支撐元件之該第二表面上方。
  16. 如申請專利範圍第15項所述之方法，更包含在接合該複數個第一子組件以及該複數個第二子組件之前，加熱(Heating)該複數個導電塊至一回流溫度，其中該複數個導電塊之加熱回流部分係為球狀，且突出於該第一層之該表面上方。
  17. 如申請專利範圍第14項所述之方法，其中該微電子元件係具有背對該第二支撐元件之一表面(Face)，流入該密封材料所形成之一第一密封體係與下列至少一者相接觸：該微電子元件之該表面，或形成於該微電子元件之該表面上的一第二密封體。
  18. 如申請專利範圍第17項所述之方法，其中流入該密封材料形成與一第二密封體相接觸的一第一密封體，該第二密封體係形成於該微電子元件之該表面上。
  19. 如申請專利範圍第14項所述之方法，其中該微電子組件包含該複數個第二端部，但不包含該複數個第一端部，該複數個第二端部係透過其間之該複數個導電塊電性耦接該複數個第一導電元件。
  20. 如申請專利範圍第14項所述之方法，其中該第一組件更包含一第二微電子元件及一第二密封體，該第二微電子元件係安裝於該第一支撐元件之該第一表面上，並透過該第一導電元件及透過其間之該複數個導電塊以電性耦接該複數個第二端部，該第二密封體係與該第一支撐元件之該第一表面及該第二微電子元件之複數個表面相接觸。
  21. 一種製造一微電子組件的方法，包含：接合(Joining)複數個第一子組件(First subassemblies)以及複數個第二子組件(Second subassemblies)以形成一組件(Assembly)，該組件包含一第一支撐元件以及一第二支撐元件，該第一支撐元件係具有面向一第一方向的一第一外表面(Outwardly-facing first surface)，該第二支撐元件係具有面向與該第一方向相反的一第二方向的一第一外表面，該第一支撐元件係具有位於其一第二內表面(Inwardly-facing second surface)上之複數個第一導電元件，該第二支撐元件係具有位於其一第二內表面上之複數個第二導電元件，至 少一微電子元件係安裝覆蓋該第一支撐元件或該第二支撐元件之該第二表面，高分子材料製成之一圖案層係覆蓋該第一支撐元件或第二支撐元件之該第二表面，該圖案層係具有複數個開孔，該複數個開孔係具有複數個截面尺寸，該截面尺寸係為固定或隨著距離該圖案層所在之各別支撐元件之表面之高度而增加，該組件更包含接合材料(Bonding Material)製成之複數個導電塊(Masses)，該複數個導電塊係從該複數個第一導電元件各別通過該複數個開孔進行延伸，並各別電性耦接該複數個第二導電元件，該複數個導電塊之複數個截面尺寸係各別由該複數個開孔之複數個截面尺寸所定義；以及在該複數個第一子組件以及該複數個第二子組件之間的一空間中流入(Flowing)一密封材料(Encapsulant)，以形成與該複數個導電塊之至少一部分之該複數個表面相接觸之一密封體。
  22. 如申請專利範圍第21項所述之方法，其中：該微電子組件包含複數個第一端部以及複數個第二端部，該複數個第一端部係位於該第一支撐元件之該第一表面上，該複數個第二端部係位於該第二支撐元件之該第一表面上，且該複數個第一端部與該複數個第二端部之電性耦接，係各別透過該複數個第一導電元件、該複數個第二導電元件及其間的該複數個導電塊；或者該微電子組件包含：該複數個第一端部，係位於該第一支撐元件之該第一表面上，並各別透過其間之該複數個導電塊電性耦接該複數個第二導電元件；或 該複數個第二端部，係位於該第二支撐元件之該第一表面上，並各別透過其間之該複數個導電塊電性耦接該複數個第一導電元件。
  23. 如申請專利範圍第22項所述之方法，其中該高分子材料為一種光阻材料。
  24. 如申請專利範圍第21項所述之方法，更包含藉由沉積一第一高分子材料層(Polymeric material)以及沉積一臨時層(Temporary Layer)以形成該圖案層，沉積該臨時層之步驟包含由感光材料製成該臨時層、光刻圖案化(Photolithographically patterning)該臨時層以形成複數個孔洞(Apertures)、使用經圖案化之該臨時層圖案化該第一層，以根據該臨時層內之該複數個孔洞形成複數個開孔(Openings)，接著用該複數個導電塊填充該複數個開孔，再接著移除該臨時層，使得該複數個導電塊突出之高度，係大於該第一層之一高度，該第一層係位於該支撐元件之該第二表面上方。
  25. 如申請專利範圍第24項所述之方法，更包含在接合該複數個第一子組件以及該複數個第二子組件之前，加熱(Heating)該複數個導電塊至一回流溫度，其中該複數個導電塊之加熱回流部分係為球狀，且突出於該第一層之該表面上方。
  26. 如申請專利範圍第22項所述之方法，其中該微電子元件係具有背對該第二支撐元件之一表面(Face)，流入該密封材料所形成之一第一密封體係與下列至少一者相接觸：該微電子元件之該表面，或形成於該微電子元件之 該表面上的一第二密封體。
  27. 如申請專利範圍第26項所述之方法，其中流入該密封材料形成與一第二密封體相接觸的一第一密封體，該第二密封體係形成於該微電子元件之該表面上。
  28. 如申請專利範圍第22項所述之方法，其中該微電子組件包含該複數個第二端部，但不包含該複數個第一端部，該複數個第二端部係各別透過其間之該複數個導電塊電性耦接該複數個第一導電元件。
  29. 如申請專利範圍第22項所述之方法，其中該第一組件更包含一第二微電子元件及一第二密封體，該第二微電子元件係安裝於該第一支撐元件之該第一表面上，並透過該第一導電元件及透過其間之該複數個導電塊以電性耦接該複數個第二端部，該第二密封體係與該第一支撐元件之該第一表面及該第二微電子元件之複數個表面相接觸。
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US20160260696A1 (en) 2016-09-08
TW201539661A (zh) 2015-10-16
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US9356006B2 (en) 2016-05-31
US9812433B2 (en) 2017-11-07

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