TWI470398B - Driver circuit and current control circuit thereof - Google Patents
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本揭示內容是有關於一種電子電路,且特別是有關於一種驅動電路及其中之電流控制電路。The present disclosure relates to an electronic circuit, and more particularly to a drive circuit and a current control circuit therefor.
電子產品已經成為現代人生活中不可或缺的一部份。在各式各樣的電子裝置中,需要可應用在這些裝置中的半導體組件。半導體組件的特性主要是由製備該組件的製程來決定。由於半導體組件通常較複雜,則其製程亦變化較多。半導體組件中需要多種具有不同特性的電晶體。高壓電晶體即是為了滿足能在高壓操作的環境而設計出的元件。Electronic products have become an integral part of modern life. In a wide variety of electronic devices, semiconductor components that can be used in these devices are needed. The characteristics of a semiconductor component are primarily determined by the process of making the component. Since semiconductor components are often complicated, the process is also subject to change. A variety of transistors with different characteristics are required in semiconductor components. High-voltage piezoelectric crystals are designed to meet the requirements of high-voltage operation.
此外,為符合現代人的需求,電子產品逐漸被設計成輕薄短小的型態,以方便人們攜帶。考慮到電子產品在其大小及元件速度之間的取捨,如何在維持面積小的情形下,設計出能擁有相同、甚至更快之開關速度的功率金氧半電晶體,為本領域技術人員探討的問題之一。In addition, in order to meet the needs of modern people, electronic products are gradually designed into a light and thin type to facilitate people to carry. Considering the trade-off between electronic products and their component speeds, how to design a power MOS semi-transistor with the same or even faster switching speed in the case of small maintenance area is discussed by those skilled in the art. One of the problems.
本發明內容之一技術態樣係關於一種電流控制電路,係用以控制驅動電路,藉使前述驅動電路相應地驅動功率金氧半電晶體。前述電流控制電路包含電流鏡、箝位P型金氧半電晶體以及峰值電流控制支路。進一步而言,峰值 電流控制支路包含電容、電阻以及控制N型金氧半電晶體。前述電流鏡之第一電流支路以及前述第二電流支路之一端電性耦接於共同端點,前述共同端點用以接收第一電位。前述箝位P型金氧半電晶體之前述控制端用以接收參考電壓,而其第一端電性耦接於前述電流鏡之前述第一電流支路。One aspect of the present invention relates to a current control circuit for controlling a drive circuit by which the aforementioned drive circuit drives a power MOS transistor. The current control circuit includes a current mirror, a clamped P-type MOS transistor, and a peak current control branch. Further, the peak The current control branch contains capacitors, resistors, and control N-type MOS transistors. The first current branch of the current mirror and one end of the second current branch are electrically coupled to a common end point, and the common end point is for receiving the first potential. The control terminal of the clamped P-type MOS transistor is configured to receive a reference voltage, and the first end of the clamped P-type MOS transistor is electrically coupled to the first current branch of the current mirror.
此外,前述峰值電流控制支路中電容的第一端用以接收開關信號,並由其第二端輸出耦合信號。前述電阻的前述第一端電性耦接於前述電容之前述第二端,而其第二端用以接收第二電位。前述控制N型金氧半電晶體的控制端電性耦接於前述電容之前述第二端,而其第二端電性耦接於前述箝位P型金氧半電晶體之第二端。In addition, the first end of the capacitor in the aforementioned peak current control branch is for receiving the switching signal, and the second end outputs a coupling signal. The first end of the resistor is electrically coupled to the second end of the capacitor, and the second end is configured to receive a second potential. The control terminal of the N-type MOS transistor is electrically coupled to the second end of the capacitor, and the second end is electrically coupled to the second end of the clamped P-type MOS transistor.
當前述電容之前述第一端接收之前述開關信號為電壓位準狀態時,前述控制N型金氧半電晶體導通,而由前述電流鏡之前述第一電流支路提供峰值電流,前述電流鏡之前述第二電流支路相應地輸出控制電流至前述驅動電路之控制端點,藉使前述驅動電路輸出至前述功率金氧半電晶體的功率閘極之驅動電壓下降,以開啟前述功率金氧半電晶體。When the aforementioned switching signal received by the first end of the capacitor is in a voltage level state, the control N-type MOS transistor is turned on, and the first current branch of the current mirror provides a peak current, the current mirror The second current branch correspondingly outputs a control current to the control terminal of the driving circuit, so that the driving voltage of the power gate outputted by the driving circuit to the power MOS transistor is decreased to turn on the power gold oxide Semi-transistor.
根據本發明一實施例,前述電流鏡之前述第一電流支路在特定時間內提供前述峰值電流。According to an embodiment of the invention, the first current branch of the current mirror provides the peak current for a specific time.
根據本發明再一實施例,前述峰值電流控制支路之前述電阻會對前述耦合信號進行放電。According to still another embodiment of the present invention, the resistor of the peak current control branch discharges the coupling signal.
根據本發明又一實施例,前述第一電位為正電位,而 前述第二電位小於前述第一電位。According to still another embodiment of the present invention, the first potential is a positive potential, and The aforementioned second potential is smaller than the aforementioned first potential.
根據本發明另再一實施例,前述功率金氧半電晶體為高壓金氧半電晶體。According to still another embodiment of the present invention, the power MOS transistor is a high voltage MOS transistor.
本發明內容之另一技術態樣係關於一種驅動電路,其係用以驅動功率金氧半電晶體。前述驅動電路包含電流控制電路、第一驅動支路以及第二驅動支路。進一步而言,前述電流控制電路包含電流鏡、第一箝位P型金氧半電晶體以及峰值電流控制支路。前述第一驅動支路包含電流源、第二箝位P型金氧半電晶體以及第一開關N型金氧半電晶體。前述第二驅動支路包含電流供應P型金氧半電晶體、第三箝位P型金氧半電晶體以及第二開關N型金氧半電晶體。其中,峰值電流控制支路包含電容、電阻以及控制N型金氧半電晶體。Another aspect of the present invention is directed to a drive circuit for driving a power MOS transistor. The aforementioned driving circuit includes a current control circuit, a first driving branch, and a second driving branch. Further, the current control circuit includes a current mirror, a first clamped P-type MOS transistor, and a peak current control branch. The first driving branch includes a current source, a second clamped P-type MOS transistor, and a first switch N-type MOS transistor. The second driving branch includes a current supply P-type MOS transistor, a third clamp P-type MOS transistor, and a second switch N-type MOS transistor. Among them, the peak current control branch includes a capacitor, a resistor, and a control N-type MOS transistor.
此外,前述電流控制電路中電流鏡的第一電流支路以及第二電流支路之一端電性耦接於共同端點,前述共同端點用以接收第一電位。前述第一箝位P型金氧半電晶體的控制端用以接收參考電壓,而其第一端電性耦接於前述電流鏡之前述第一電流支路。前述第一驅動支路中第二箝位P型金氧半電晶體之控制端用以接收前述參考電壓,而其第一端電性耦接於控制端點以及前述電流源。前述第一開關N型金氧半電晶體之控制端用以接收反相開關信號,而其第一端電性耦接於前述第二箝位P型金氧半電晶體之前述第二端。In addition, in the current control circuit, the first current branch of the current mirror and one end of the second current branch are electrically coupled to a common end point, and the common end point is used to receive the first potential. The control end of the first clamp P-type MOS transistor is configured to receive a reference voltage, and the first end thereof is electrically coupled to the first current branch of the current mirror. The control terminal of the second clamp P-type MOS transistor in the first driving branch is configured to receive the reference voltage, and the first end thereof is electrically coupled to the control terminal and the current source. The control end of the first switch N-type MOS transistor is configured to receive the inverted switch signal, and the first end thereof is electrically coupled to the second end of the second clamp P-type MOS transistor.
前述第二驅動支路中電流供應P型金氧半電晶體之控 制端電性耦接於前述控制端點,而其第一端用以接收前述第一電位。前述第三箝位P型金氧半電晶體之控制端用以接收前述參考電壓,其第一端電性耦接於前述電流供應P型金氧半電晶體之第二端,而其第一端輸出驅動電壓至前述功率金氧半電晶體之功率閘極。前述第二驅動支路中第二開關N型金氧半電晶體之控制端用以接收前述開關信號,而其第一端電性耦接於前述第三箝位N型金氧半電晶體之第二端。Control of current supply P-type MOS semi-transistor in the aforementioned second driving branch The terminal is electrically coupled to the aforementioned control terminal, and the first end thereof is configured to receive the first potential. The control terminal of the third clamp P-type MOS transistor is configured to receive the reference voltage, and the first end thereof is electrically coupled to the second end of the current supply P-type MOS transistor, and the first end thereof The terminal outputs a driving voltage to the power gate of the aforementioned power MOS transistor. The control end of the second switch N-type MOS transistor in the second driving branch is configured to receive the switching signal, and the first end thereof is electrically coupled to the third clamping N-type MOS transistor Second end.
此外,前述峰值電流控制支路中峰值電流控制支路之電容的第一端用以接收開關信號,並由其第二端輸出耦合信號。前述電阻之第一端電性耦接於前述電容之前述第二端,前述電阻之第二端用以接收第二電位。前控制N型金氧半電晶體的控制端電性耦接於前述電容之第二端,而其第一端電性耦接於前述箝位P型金氧半電晶體之第二端。In addition, the first end of the capacitance of the peak current control branch in the aforementioned peak current control branch is for receiving the switching signal, and the second terminal outputs the coupling signal. The first end of the resistor is electrically coupled to the second end of the capacitor, and the second end of the resistor is configured to receive a second potential. The control terminal of the front control N-type MOS transistor is electrically coupled to the second end of the capacitor, and the first end thereof is electrically coupled to the second end of the clamped P-type MOS transistor.
承上所敘,當前述電容之前述第一端接收之前述開關信號為電壓位準狀態時,前述控制N型金氧半電晶體導通,前述電流鏡之前述第一電流支路提供峰值電流,前述電流鏡之前述第二電流支路相應地輸出控制電流至前述驅動電路之控制端點,藉使前述驅動電路輸出至前述功率金氧半電晶體的功率閘極之驅動電壓下降,以開啟前述功率金氧半電晶體。As described above, when the aforementioned switching signal received by the first end of the capacitor is in a voltage level state, the control N-type MOS transistor is turned on, and the first current branch of the current mirror provides a peak current. The second current branch of the current mirror correspondingly outputs a control current to a control terminal of the driving circuit, so that a driving voltage of the power gate outputted by the driving circuit to the power MOS transistor is lowered to turn on the foregoing Power MOS semi-transistor.
根據本發明一實施例,前述電流鏡之前述第一電流支路在特定時間內提供前述峰值電流。According to an embodiment of the invention, the first current branch of the current mirror provides the peak current for a specific time.
根據本發明再一實施例,前述峰值電流控制支路之前 述電阻會對前述耦合信號進行放電。According to still another embodiment of the present invention, before the aforementioned peak current control branch The resistor discharges the aforementioned coupling signal.
根據本發明又一實施例,前述第一電位為正電位,而前述第二電位小於前述第一電位。According to still another embodiment of the present invention, the first potential is a positive potential, and the second potential is smaller than the first potential.
根據本發明另再一實施例,前述功率金氧半電晶體為高壓金氧半電晶體。According to still another embodiment of the present invention, the power MOS transistor is a high voltage MOS transistor.
本發明內容之又一技術態樣係關於一種電流控制電路,其係用以控制驅動電路,藉使驅動電路相應地驅動功率金氧半電晶體。前述電流控制電路包含電流鏡、箝位N型金氧半電晶體以及峰值電流控制支路。進一步而言,前述峰值電流控制支路包含電容、電阻以及控制P型金氧半電晶體。前述電流鏡之第一電流支路以及第二電流支路之一端電性耦接於共同端點,前述共同端點用以接收第一電位。前述箝位N型金氧半電晶體之控制端用以接收參考電壓,而其第一端電性耦接於前述電流鏡之第一電流支路。Yet another aspect of the present invention is directed to a current control circuit for controlling a drive circuit whereby a drive circuit drives a power MOS transistor. The current control circuit includes a current mirror, a clamped N-type MOS transistor, and a peak current control branch. Further, the aforementioned peak current control branch includes a capacitor, a resistor, and a P-type MOS transistor. The first current branch of the current mirror and one end of the second current branch are electrically coupled to a common end point, and the common end point is for receiving the first potential. The control terminal of the clamping N-type MOS transistor is configured to receive a reference voltage, and the first end thereof is electrically coupled to the first current branch of the current mirror.
此外,前述峰值電流控制支路中電容的第一端用以接收開關信號,並由其第二端輸出耦合信號。前述電阻之第一端電性耦接於前述電容之前述第二端,而其第二端用以接收第二電位。前述控制P型金氧半電晶體之控制端電性耦接於前述電容之前述第二端,而其第一端電性耦接於前述箝位N型金氧半電晶體之第二端。當前述電容之前述第一端接收之前述開關信號為電壓位準狀態時,前述控制P型金氧半電晶體導通,而由前述電流鏡之前述第一電流支路提供電流,前述電流鏡之前述第二電流支路相應地由控制端點汲取電流,藉使前述驅動電路輸出至前述功率金氧 半電晶體的功率閘極之驅動電壓上升,以開啟前述功率金氧半電晶體。In addition, the first end of the capacitor in the aforementioned peak current control branch is for receiving the switching signal, and the second end outputs a coupling signal. The first end of the resistor is electrically coupled to the second end of the capacitor, and the second end is configured to receive a second potential. The control terminal of the P-type MOS transistor is electrically coupled to the second end of the capacitor, and the first end thereof is electrically coupled to the second end of the clamped N-type MOS transistor. When the aforementioned switching signal received by the first end of the capacitor is in a voltage level state, the P-type MOS transistor is turned on, and the current is supplied by the first current branch of the current mirror, and the current mirror is The second current branch correspondingly draws current from the control terminal, so that the driving circuit outputs the power to the aforementioned power The driving voltage of the power gate of the semi-transistor rises to turn on the aforementioned power MOS transistor.
根據本發明一實施例,前述電流鏡之前述第一電流支路在特定時間內提供前述峰值電流。According to an embodiment of the invention, the first current branch of the current mirror provides the peak current for a specific time.
根據本發明又一實施例,前述電流控制電路更包含電壓供應N型金氧半電晶體,其包含第一端以及第二端,前述第一端電性耦接於前述峰值電流控制支路的控制P型金氧半電晶體之第二端,而前述第二端用以接收高電壓電位。According to still another embodiment of the present invention, the current control circuit further includes a voltage supply N-type MOS transistor, including a first end and a second end, wherein the first end is electrically coupled to the peak current control branch The second end of the P-type MOS transistor is controlled, and the second end is for receiving a high voltage potential.
根據本發明再一實施例,前述峰值電流控制支路之前述電阻會對前述電容之前述第二端進行充電。According to still another embodiment of the present invention, the resistor of the peak current control branch charges the second end of the capacitor.
根據本發明又一實施例,前述第一電位為負電位,而前述第二電位大於前述第一電位。According to still another embodiment of the present invention, the first potential is a negative potential, and the second potential is greater than the first potential.
根據本發明另再一實施例,前述功率金氧半電晶體為高壓金氧半電晶體。According to still another embodiment of the present invention, the power MOS transistor is a high voltage MOS transistor.
本發明內容之再一技術態樣係關於一種驅動電路,其係用以驅動功率金氧半電晶體。前述驅動電路包含電流控制電路、第一驅動支路以及第二驅動支路。進一步而言,前述電流控制電路包含電流鏡、第一箝位N型金氧半電晶體以及峰值電流控制支路。前述第一驅動支路包含電流源、第二箝位N型金氧半電晶體以及第一開關P型金氧半電晶體。前述第二驅動支路包含電流供應N型金氧半電晶體、第三箝位N型金氧半電晶體以及第二開關P型金氧半電晶體。其中,前述峰值電流控制支路包含電容、電阻以及控制P型金氧半電晶體。Still another aspect of the present invention is directed to a driving circuit for driving a power MOS transistor. The aforementioned driving circuit includes a current control circuit, a first driving branch, and a second driving branch. Further, the current control circuit includes a current mirror, a first clamp N-type MOS transistor, and a peak current control branch. The first driving branch includes a current source, a second clamped N-type MOS transistor, and a first switch P-type MOS transistor. The second driving branch includes a current supply N-type MOS transistor, a third clamp N-type MOS transistor, and a second switch P-type MOS transistor. Wherein, the peak current control branch includes a capacitor, a resistor, and a P-type MOS transistor.
此外,前述電流控制電路中電流鏡之第一電流支路以及第二電流支路之一端電性耦接於共同端點,前述共同端點用以接收第一電位。前述第一箝位N型金氧半電晶體之控制端用以接收參考電壓,而其第一端電性耦接於前述電流鏡之前述第一電流支路。前述第一驅動支路中第二箝位N型金氧半電晶體之控制端用以接收前述參考電壓,而其第一端電性耦接於控制端點以及前述電流源。前述第一開關P型金氧半電晶體之控制端用以接收反相開關信號,而其第一端電性耦接於前述第二箝位N型金氧半電晶體之第二端。In addition, in the current control circuit, the first current branch of the current mirror and one end of the second current branch are electrically coupled to a common end point, and the common end point is used to receive the first potential. The control terminal of the first clamp N-type MOS transistor is configured to receive a reference voltage, and the first end thereof is electrically coupled to the first current branch of the current mirror. The control terminal of the second clamp N-type MOS transistor in the first driving branch is configured to receive the reference voltage, and the first end thereof is electrically coupled to the control terminal and the current source. The control terminal of the first switch P-type MOS transistor is configured to receive the inverted switch signal, and the first end thereof is electrically coupled to the second end of the second clamp N-type MOS transistor.
前述第二驅動支路中電流供應N型金氧半電晶體之控制端電性耦接於前述控制端點,而其第一端用以接收前述第一電位。前述第三箝位N型金氧半電晶體之控制端用以接收前述參考電壓,其第一端電性耦接於前述電流供應N型金氧半電晶體之第二端,而其第一端輸出驅動電壓至前述功率金氧半電晶體之功率閘極。前述第二驅動支路中第二開關P型金氧半電晶體之控制端用以接收前述開關信號,而其第一端電性耦接於前述第三箝位N型金氧半電晶體之第二端。The control terminal of the current supply N-type MOS transistor in the second driving branch is electrically coupled to the control terminal, and the first end thereof is configured to receive the first potential. The control end of the third clamp N-type MOS transistor is configured to receive the reference voltage, and the first end thereof is electrically coupled to the second end of the current supply N-type MOS transistor, and the first end thereof The terminal outputs a driving voltage to the power gate of the aforementioned power MOS transistor. a control end of the second switch P-type MOS transistor in the second driving branch is configured to receive the switching signal, and a first end thereof is electrically coupled to the third clamping N-type MOS transistor Second end.
此外,前述電流控制電路中峰值電流控制支路之電容的第一端用以接收開關信號,並由其第二端輸出耦合信號。前述電阻之第一端電性耦接於前述電容之前述第二端,而其第二端用以接收第二電位。前述控制P型金氧半電晶體之控制端電性耦接於前述電容之前述第二端,而其 第一端電性耦接於前述第一箝位N型金氧半電晶體之第二端。In addition, the first end of the capacitance of the peak current control branch in the current control circuit is for receiving the switching signal, and the second terminal outputs the coupling signal. The first end of the resistor is electrically coupled to the second end of the capacitor, and the second end is configured to receive a second potential. The control terminal of the P-type MOS transistor is electrically coupled to the second end of the capacitor, and The first end is electrically coupled to the second end of the first clamp N-type oxynitride.
承上所述,當前述電容之前述第一端接收之前述開關信號為電壓位準狀態時,前述控制P型金氧半電晶體導通,前述電流鏡之前述第一電流支路提供峰值電流,前述電流鏡之前述第二電流支路相應地由控制端點汲取電流,藉使前述第三箝位N型金氧半電晶體之前述第一端輸出至前述功率金氧半電晶體的前述功率閘極之前述驅動電壓上升,以開啟前述功率金氧半電晶體。According to the above, when the first switch received by the first end of the capacitor is in a voltage level state, the P-type MOS transistor is turned on, and the first current branch of the current mirror provides a peak current. The second current branch of the current mirror correspondingly draws current from the control terminal, wherein the first end of the third clamped N-type MOS transistor is output to the power of the power MOS transistor The aforementioned driving voltage of the gate rises to turn on the aforementioned power MOS transistor.
根據本發明一實施例,前述電流鏡之前述第一電流支路在特定時間內提供前述峰值電流。According to an embodiment of the invention, the first current branch of the current mirror provides the peak current for a specific time.
根據本發明又一實施例,前述驅動電路更包含電壓供應N型金氧半電晶體,其包含第一端以及第二端,前述第一端電性耦接於前述電流控制電路的控制P型金氧半電晶體之第二端,而前述第二端用以接收高電壓電位。According to still another embodiment of the present invention, the driving circuit further includes a voltage supply N-type MOS transistor, including a first end and a second end, wherein the first end is electrically coupled to the control P type of the current control circuit. The second end of the MOS transistor and the second end are configured to receive a high voltage potential.
根據本發明再一實施例,前述峰值電流控制支路之前述電阻會對前述電容之第二端進行充電。According to still another embodiment of the present invention, the resistor of the peak current control branch charges the second end of the capacitor.
根據本發明又一實施例,前述第一電位為正電位,而前述第二電位大於前述第一電位。According to still another embodiment of the present invention, the first potential is a positive potential, and the second potential is greater than the first potential.
根據本發明另再一實施例,前述功率金氧半電晶體為高壓金氧半電晶體。According to still another embodiment of the present invention, the power MOS transistor is a high voltage MOS transistor.
因此,根據本發明之技術內容,本發明實施例藉由提供一種驅動電路及其中之電流控制電路,藉以改善功率電晶體之傳遞延遲(propagation delay)現象,並進一步將傳 遞延遲現象縮小至50奈秒以內。Therefore, according to the technical content of the present invention, an embodiment of the present invention provides a driving circuit and a current control circuit therein, thereby improving a propagation delay phenomenon of a power transistor, and further transmitting The delay is reduced to less than 50 nanoseconds.
為了使本揭示內容之敘述更加詳盡與完備,可參照所附之圖式及以下所述各種實施例,圖式中相同之號碼代表相同或相似之元件。但所提供之實施例並非用以限制本發明所涵蓋的範圍,而結構運作之描述非用以限制其執行之順序,任何由元件重新組合之結構,所產生具有均等功效的裝置,皆為本發明所涵蓋的範圍。In order to make the description of the present disclosure more complete and complete, reference is made to the accompanying drawings and the accompanying drawings. However, the embodiments provided are not intended to limit the scope of the invention, and the description of the operation of the structure is not intended to limit the order of its execution, and any device that is recombined by the components produces equal devices. The scope covered by the invention.
其中圖式僅以說明為目的,並未依照原尺寸作圖。另一方面,眾所週知的元件與步驟並未描述於實施例中,以避免對本發明造成不必要的限制。The drawings are for illustrative purposes only and are not drawn to the original dimensions. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessarily limiting the invention.
另外,關於本文中所使用之『耦接』或『連接』,均可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,亦可指二或多個元件相互操作或動作。In addition, the term "coupled" or "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or Multiple components operate or act upon each other.
第1圖係依照本發明一實施例繪示一種驅動電路的示意圖,其係用以驅動功率金氧半電晶體MP0。如圖所示,驅動電路100包含電流控制電路110與驅動級120,驅動級120又包含第一驅動支路122以及第二驅動支路124。1 is a schematic diagram of a driving circuit for driving a power MOS transistor MP0 according to an embodiment of the invention. As shown, the drive circuit 100 includes a current control circuit 110 and a drive stage 120. The drive stage 120 in turn includes a first drive branch 122 and a second drive branch 124.
於本實施例中,功率金氧半電晶體MP0為P型高壓金氧半電晶體。高壓金氧半電晶體(high voltage MOS;HVMOS)為可承受高電壓的電晶體,於一實施例中,是指可承受至約10伏特或以上的高壓,有別於一般常見的耐壓 (如3.3伏特或5伏特)。於一些半導體製造技術中,可製造出具有可承受高壓的源極與汲極,而閘極僅能承受較小電壓(如5伏特)的功率金氧半電晶體。以此方式設計的功率金氧半電晶體,將可在面積較小的情形下,達到使功率金氧半電晶體導通阻值(RDS (on))變小,進一步達到使功率金氧半電晶體之傳遞延遲減小與上升時間(rising time)及下降時間(falling time)變小的效果。In the present embodiment, the power MOS transistor MPO is a P-type high voltage MOS transistor. High voltage MOS (HVMOS) is a transistor that can withstand high voltage. In one embodiment, it refers to a high voltage that can withstand up to about 10 volts or more, which is different from the common normal withstand voltage ( Such as 3.3 volts or 5 volts). In some semiconductor fabrication techniques, a power MOS transistor having a source and a drain that can withstand high voltages and a gate that can only withstand a small voltage (eg, 5 volts) can be fabricated. The power MOS semi-transistor designed in this way will be able to reduce the on-resistance (R DS (on)) of the power MOS transistor in a small area, further achieving the power MOS half. The transmission delay of the transistor is reduced, and the rising time and the falling time are reduced.
為使上述類型的功率金氧半電晶體可以在驅動時,更進一步改善其傳遞延遲(propagation delay)現象,本發明實施例設計一驅動電路,藉由其整體電路架構的配置方式所衍生之電性操作,可符合此類型之功率金氧半電晶體的需求,並將功率金氧半電晶體之傳遞延遲現象縮小至50奈秒以內。以下將詳細說明本發明實施例之驅動電路的結構與電性操作方式,以使本發明之目的及功效更易於理解。In order to enable the above-mentioned type of power MOS semi-transistor to further improve the propagation delay phenomenon when driving, the embodiment of the present invention designs a driving circuit, which is derived from the configuration of the overall circuit architecture. Sexual operation can meet the requirements of this type of power MOS semi-transistor, and reduce the transmission delay phenomenon of power MOS semi-transistor to less than 50 nanoseconds. The structure and electrical operation mode of the driving circuit of the embodiment of the present invention will be described in detail below to make the object and effect of the present invention easier to understand.
首先,於整體操作概念上,係由電流控制電路110接收開關信號,並根據開關信號以輸出控制電流至驅動級120,藉使驅動級120相應地驅動功率金氧半電晶體MP0。First, in the overall operational concept, the switching signal is received by the current control circuit 110, and the control current is output to the driving stage 120 according to the switching signal, so that the driving stage 120 drives the power MOS transistor MP0 accordingly.
上述電流控制電路110包含電流鏡112、第一箝位P型金氧半電晶體MP3以及峰值電流控制支路114。如第1圖所示,進一步而言,電流鏡112包含第一P型金氧半電晶體MP1以及第二P型金氧半電晶體MP2,其中第一P型金氧半電晶體MP1位於第一電流支路上,而第二P型金氧半電晶體MP2位於第二電流支路上。此外,峰值電流控制支路114包含電容C1、電阻R1以及控制N型金氧半電晶體MN1。The current control circuit 110 includes a current mirror 112, a first clamped P-type MOS transistor MP3, and a peak current control branch 114. As shown in FIG. 1, further, the current mirror 112 includes a first P-type MOS transistor MP1 and a second P-type MOS transistor MP2, wherein the first P-type MOS transistor is located at the first A current branch, and the second P-type MOS transistor MP2 is located on the second current branch. In addition, the peak current control branch 114 includes a capacitor C1, a resistor R1, and a control N-type MOS transistor MN1.
於結構上,電流控制電路110的電流鏡112之第一電流支路以及第二電流支路之一端電性耦接於共同端點N1,此共同端點N1用以接收第一電位VGH。電流控制電路110的第一箝位P型金氧半電晶體MP3之控制端用以接收一參考電壓VM,而其第一端電性耦接於電流鏡112之第一電流支路。The first current branch of the current mirror 112 of the current control circuit 110 and one end of the second current branch are electrically coupled to the common terminal N1 for receiving the first potential VGH. The control terminal of the first clamped P-type MOS transistor MP3 of the current control circuit 110 is configured to receive a reference voltage VM, and the first end thereof is electrically coupled to the first current branch of the current mirror 112.
在電流控制電路110的峰值電流控制支路114中,電容C1的第一端用以接收開關信號IN,並由其第二端輸出耦合信號。電阻R1之第一端電性耦接於電容C1之第二端,而其第二端用以接收第二電位VSS。控制N型金氧半電晶體MN1之控制端電性耦接於電容C1之第二端,而其第一端電性耦接於第一箝位P型金氧半電晶體MP3第二端。In the peak current control branch 114 of the current control circuit 110, the first end of the capacitor C1 is for receiving the switching signal IN, and the second terminal outputs a coupling signal. The first end of the resistor R1 is electrically coupled to the second end of the capacitor C1, and the second end thereof is configured to receive the second potential VSS. The control terminal of the N-type MOS transistor MN1 is electrically coupled to the second end of the capacitor C1, and the first end thereof is electrically coupled to the second terminal of the first clamp P-type MOS transistor MP3.
在此需說明的是,本發明實施例中各式金氧半電晶體之控制端可為閘極,其第一端及第二端則可依照實際電路配置之需求,而選擇性地為源極或汲極。It should be noted that, in the embodiment of the present invention, the control terminal of each type of metal oxide semi-transistor may be a gate, and the first end and the second end thereof may be selectively used according to the requirements of the actual circuit configuration. Extreme or bungee.
於電性操作上,當電流控制電路110中峰值電流控制支路114之電容C1的第一端接收之開關信號IN為一高態時,控制N型金氧半電晶體MN1導通,電流鏡112之第一電流支路提供峰值電流,而電流鏡之第二電流支路相應地輸出控制電流至驅動級120之控制端點N2,藉使驅動級120輸出至功率金氧半電晶體MP0的控制端之驅動電壓下降,以開啟功率金氧半電晶體MP0。In the electrical operation, when the switch signal IN received by the first end of the capacitor C1 of the peak current control branch 114 in the current control circuit 110 is in a high state, the N-type MOS transistor MN1 is controlled to be turned on, and the current mirror 112 is turned on. The first current branch provides a peak current, and the second current branch of the current mirror accordingly outputs a control current to the control terminal N2 of the driver stage 120, whereby the output of the driver stage 120 to the power MOS transistor M0 is controlled. The driving voltage of the terminal is lowered to turn on the power MOS transistor MP0.
需進一步說明的是,電流控制電路110中電流鏡112之第一電流支路在一特定時間內提供峰值電流。因此,本 發明實施例之驅動電路100的電流控制電路110可在極短的時間內,迅速產生峰值電流,並於同時間內相應地輸出控制電流至驅動級120,以達到迅速開啟功率金氧半電晶體MP0之目的。然而,本實施例並非用以限定本發明,熟習此技藝者當可選擇性地採用適當之參數,而其概念與本發明相同者,即落入本發明之範圍中。It should be further noted that the first current branch of the current mirror 112 in the current control circuit 110 provides a peak current for a certain period of time. Therefore, this The current control circuit 110 of the driving circuit 100 of the embodiment of the invention can rapidly generate a peak current in a very short time, and correspondingly output a control current to the driving stage 120 at the same time to achieve a rapid turn-on power MOS transistor. The purpose of MP0. However, the present invention is not intended to limit the present invention, and those skilled in the art can selectively adopt appropriate parameters, and the concept is the same as the present invention, that is, falls within the scope of the present invention.
在一實施例中,當上述峰值電流衍生出迅速開啟功率金氧半電晶體MP0之效果後,電流控制電路110中峰值電流控制支路114之電阻R1會對電容C1的第二端進行放電,從而關閉控制N型金氧半電晶體MN1,此時,上述峰值電流也將一併消失,是以於迅速開啟功率金氧半電晶體MP0之後,由於控制N型金氧半電晶體MN1被關閉,電流控制電路110上將不會有無謂的電能耗損。In one embodiment, after the peak current derives the effect of rapidly turning on the power MOS transistor MP0, the resistor R1 of the peak current control branch 114 in the current control circuit 110 discharges the second end of the capacitor C1. Therefore, the N-type MOS transistor MN1 is turned off, and at this time, the peak current will also disappear together, so that after the power MOS transistor M0 is quickly turned on, the N-type MOS transistor MN1 is turned off. There will be no unnecessary electrical energy loss on the current control circuit 110.
上述驅動級120之第一驅動支路122包含電流源123、第二箝位P型金氧半電晶體MP4以及第一開關N型金氧半電晶體MN2。第二箝位P型金氧半電晶體MP4之控制端用以接收參考電壓VM,其第一端電性耦接於控制端點N2以及電流源123,而得以接收電流控制電路110中電流鏡112之第二電流支路輸出的控制電流。第一開關N型金氧半電晶體MN2之控制端用以接收一反相開關信號IN ,而其第一端電性耦接於第二箝位P型金氧半電晶體MP4之第二端。The first driving branch 122 of the driving stage 120 includes a current source 123, a second clamp P-type MOS transistor MP4, and a first switching N-type MOS transistor MN2. The control terminal of the second clamp P-type MOS transistor MP4 is configured to receive the reference voltage VM, the first end of which is electrically coupled to the control terminal N2 and the current source 123, and is configured to receive the current mirror in the current control circuit 110. The control current of the second current branch of 112 is output. The control end of the first switch N-type MOS transistor MN2 is configured to receive an inverted switch signal IN , and the first end thereof is electrically coupled to the second end of the second clamp P-type MOS transistor M4 .
再者,上述驅動級120之第二驅動支路124包含電流供應P型金氧半電晶體MP5、第三箝位P型金氧半電晶體MP6以及第二開關N型金氧半電晶體MN3。電流供應P 型金氧半電晶體MP5之控制端電性耦接於控制端點N2,而其第一端用以接收第一電位VGH。第三箝位P型金氧半電晶體MP6之控制端用以接收參考電壓VM,其第一端電性耦接於電流供應P型金氧半電晶體MP5之第二端,且其第一端輸出驅動電壓至功率金氧半電晶體MP0之控制端。第二開關N型金氧半電晶體MN3之控制端用以接收開關信號IN,而其第一端電性耦接於第三箝位P型金氧半電晶體MP6之第二端。Furthermore, the second driving branch 124 of the driving stage 120 includes a current supply P-type MOS transistor MP5, a third clamp P-type MOS transistor M6, and a second switch N-type MOS transistor MN3. . Current supply P The control terminal of the MOS transistor MP5 is electrically coupled to the control terminal N2, and the first terminal thereof is configured to receive the first potential VGH. The control terminal of the third clamp P-type MOS transistor 6 is configured to receive the reference voltage VM, and the first end thereof is electrically coupled to the second end of the current supply P-type MOS transistor 5, and the first end thereof The terminal outputs a driving voltage to the control terminal of the power MOS transistor MP0. The control terminal of the second switch N-type MOS transistor MN3 is configured to receive the switch signal IN, and the first end thereof is electrically coupled to the second end of the third clamp P-type MOS transistor.
在本實施例中,於電性操作上,當電流控制電路110中峰值電流控制支路114之電容C1的第一端接收之開關信號IN為一高態時,控制N型金氧半電晶體MN1導通,且驅動級120中第二驅動支路124之第二開關N型金氧半電晶體MN3導通,電流鏡112之第一電流支路提供峰值電流,而電流鏡112之第二電流支路相應地輸出控制電流至控制端點N2,控制端點N2的電壓抬升。由於控制端點N2的電壓即為電流供應P型金氧半電晶體MP5之控制端接收的電壓,因而電流供應P型金氧半電晶體MP5將在控制端點N2的電壓抬升下關閉。In this embodiment, in the electrical operation, when the switching signal IN received by the first end of the capacitor C1 of the peak current control branch 114 in the current control circuit 110 is in a high state, the N-type MOS transistor is controlled. MN1 is turned on, and the second switch N-type MOS transistor MN3 of the second driving branch 124 in the driving stage 120 is turned on, the first current branch of the current mirror 112 provides a peak current, and the second current branch of the current mirror 112 The circuit accordingly outputs a control current to the control terminal N2 to control the voltage rise of the terminal N2. Since the voltage of the control terminal N2 is the voltage received by the control terminal of the current supply P-type MOS transistor 55, the current supply P-type MOS transistor MP5 will be turned off at the voltage rise of the control terminal N2.
此時,第二驅動支路124之第二開關N型金氧半電晶體MN3的第一端會汲取輸出電壓Vp,藉使第三箝位P型金氧半電晶體MP6之第一端輸出至功率金氧半電晶體MP0的控制端之驅動電壓Vp下降,以開啟功率金氧半電晶體MP0。At this time, the first end of the second switch N-type MOS transistor MN3 of the second driving branch 124 draws the output voltage Vp, so that the first end of the third clamp P-type MOS transistor 6 is output. The driving voltage Vp of the control terminal of the power MOS transistor MPO is lowered to turn on the power MOS transistor MP0.
在一實施例中,上述第一電位VGH為正電位,而第二電位VSS小於第一電位VG。於一實施例中,第二電位VSS 可為接地電位。In one embodiment, the first potential VGH is a positive potential and the second potential VSS is less than the first potential VG. In an embodiment, the second potential VSS Can be ground potential.
第2圖係依照本發明一實施例繪示一種驅動電路的示意圖,其係用以驅動功率金氧半電晶體MN0。如圖所示,驅動電路200包含電流控制電路210與驅動級220,驅動級220又包含第一驅動支路222以及第二驅動支路224。2 is a schematic diagram of a driving circuit for driving a power MOS transistor MN0 according to an embodiment of the invention. As shown, the drive circuit 200 includes a current control circuit 210 and a drive stage 220. The drive stage 220 in turn includes a first drive branch 222 and a second drive branch 224.
於本實施例中,功率金氧半電晶體MN0為N型高壓金氧半電晶體,而高壓金氧半電晶體之特性已詳述於第1圖中,在此不做贅述。In the present embodiment, the power MOS semi-transistor MN0 is an N-type high-voltage MOS semi-transistor, and the characteristics of the high-voltage MOS semi-transistor have been described in detail in FIG. 1 and will not be described herein.
為使上述類型的功率金氧半電晶體可以在驅動時,更進一步改善其傳遞延遲(propagation delay)現象,本發明實施例設計一驅動電路,藉由其整體電路架構的配置方式所衍生之電性操作,可符合此類型之功率金氧半電晶體的需求,並將功率金氧半電晶體之傳遞延遲現象縮小至50奈秒以內。以下將詳細說明本發明實施例之驅動電路的結構與電性操作方式,以使本發明之目的及功效更易於理解。In order to enable the above-mentioned type of power MOS semi-transistor to further improve the propagation delay phenomenon when driving, the embodiment of the present invention designs a driving circuit, which is derived from the configuration of the overall circuit architecture. Sexual operation can meet the requirements of this type of power MOS semi-transistor, and reduce the transmission delay phenomenon of power MOS semi-transistor to less than 50 nanoseconds. The structure and electrical operation mode of the driving circuit of the embodiment of the present invention will be described in detail below to make the object and effect of the present invention easier to understand.
首先,於整體操作概念上,係由電流控制電路210接收開關信號,並根據開關信號以輸出控制電流至驅動級220,藉使驅動級220相應地驅動功率金氧半電晶體MN0。First, in the overall operational concept, the switching signal is received by the current control circuit 210, and the control current is output to the driving stage 220 according to the switching signal, so that the driving stage 220 drives the power MOS transistor MN0 accordingly.
上述電流控制電路210包含電流鏡212、第一箝位N型金氧半電晶體MN1以及峰值電流控制支路214。如第2圖所示,進一步而言,電流鏡212包含第一N型金氧半電晶體MN2以及第二N型金氧半電晶體MN3,其中第一N型金氧半電晶體MN2位於第一電流支路上,而第二N型金氧半電晶體MN3位於第二電流支路上。此外,峰值電流控制支路214包含電容C1、電阻R1以及控制P型金氧半 電晶體MP1。The current control circuit 210 includes a current mirror 212, a first clamp N-type MOS transistor MN1, and a peak current control branch 214. As shown in FIG. 2, further, the current mirror 212 includes a first N-type MOS transistor MN2 and a second N-type MOS transistor MN3, wherein the first N-type MOS transistor MN2 is located at A current branch, and the second N-type MOS transistor MN3 is located on the second current branch. In addition, the peak current control branch 214 includes a capacitor C1, a resistor R1, and a control P-type oxy-half. Transistor MP1.
於結構上,電流控制電路210的電流鏡212之第一電流支路以及第二電流支路之一端電性耦接於共同端點N1,此共同端點N1用以接收第一電位VEE。電流控制電路210的第一箝位N型金氧半電晶體MN1之控制端用以接收參考電壓VM,而其第一端電性耦接於電流鏡212之第一電流支路。The first current branch of the current mirror 212 of the current control circuit 210 and one end of the second current branch are electrically coupled to the common terminal N1 for receiving the first potential VEE. The control terminal of the first clamp N-type MOS transistor MN1 of the current control circuit 210 is configured to receive the reference voltage VM, and the first end thereof is electrically coupled to the first current branch of the current mirror 212.
在電流控制電路210的峰值電流控制支路214中,電容C1的第一端用以接收開關信號IN,並由其第二端輸出耦合信號。電阻R1之第一端電性耦接於電容C1之第二端,而其第二端用以接收第二電位VDDX。控制P型金氧半電晶體MP1之控制端電性耦接於電容C1之第二端,而其第一端電性耦接於第一箝位N型金氧半電晶體MN1之第二端。In the peak current control branch 214 of the current control circuit 210, the first end of the capacitor C1 is for receiving the switching signal IN and the second terminal is for outputting the coupling signal. The first end of the resistor R1 is electrically coupled to the second end of the capacitor C1, and the second end thereof is configured to receive the second potential VDDX. The control terminal of the P-type MOS transistor is electrically coupled to the second end of the capacitor C1, and the first end thereof is electrically coupled to the second end of the first clamp N-type MOS transistor MN1. .
於電性操作上,當電流控制電路210中峰值電流控制支路214之電容C1的第一端接收之開關信號IN為一低態時,電容C1輸出耦合信號以使控制P型金氧半電晶體MP1導通,此時,電流鏡212之第一電流支路提供峰值電流,而電流鏡之第二電流支路相應地由驅動級220之控制端點N2汲取電流,藉使驅動級220輸出至功率金氧半電晶體MN0的控制端之驅動電壓上升,以開啟功率金氧半電晶體MN0。In electrical operation, when the switch signal IN received by the first terminal of the capacitor C1 of the peak current control branch 214 in the current control circuit 210 is in a low state, the capacitor C1 outputs a coupling signal to control the P-type MOS. The crystal MP1 is turned on. At this time, the first current branch of the current mirror 212 provides a peak current, and the second current branch of the current mirror correspondingly draws current from the control terminal N2 of the driver stage 220, so that the driver stage 220 outputs The driving voltage of the control terminal of the power MOS transistor MN0 rises to turn on the power MOS transistor MN0.
需進一步說明的是,電流控制電路210中電流鏡212之第一電流支路在一特定時間內提供峰值電流。因此,本發明實施例之驅動電路200的電流控制電路210可在極短 的時間內,迅速產生峰值電流,並於同時間內相應地由驅動級220汲取電流,以達到迅速開啟功率金氧半電晶體MN0之目的。然而,本實施例並非用以限定本發明,熟習此技藝者當可選擇性地採用適當之參數,而其概念與本發明相同者,即落入本發明之範圍中。It should be further noted that the first current branch of the current mirror 212 in the current control circuit 210 provides a peak current for a certain period of time. Therefore, the current control circuit 210 of the driving circuit 200 of the embodiment of the present invention can be extremely short During the time, the peak current is rapidly generated, and the current is drawn by the driving stage 220 correspondingly at the same time to achieve the purpose of quickly turning on the power MOS transistor MN0. However, the present invention is not intended to limit the present invention, and those skilled in the art can selectively adopt appropriate parameters, and the concept is the same as the present invention, that is, falls within the scope of the present invention.
在一實施例中,當上述峰值電流衍生出迅速開啟功率金氧半電晶體MN0之效果後,電流控制電路210中峰值電流控制支路214之電阻R1會對電容C1之第二端進行充電,從而關閉控制P型金氧半電晶體MP1,此時,上述峰值電流也將一併消失,是以於迅速開啟功率金氧半電晶體MN0之後,由於控制P型金氧半電晶體MP1被關閉,電流控制電路210上將不會有無謂的電能耗損。In one embodiment, after the peak current derives the effect of rapidly turning on the power MOS transistor MN0, the resistor R1 of the peak current control branch 214 in the current control circuit 210 charges the second end of the capacitor C1. Therefore, the P-type MOS transistor MP1 is turned off, and at this time, the peak current will also disappear together, so that after the power MOS transistor MN0 is quickly turned on, the P-type MOS transistor is turned off. There will be no unnecessary electrical energy loss on the current control circuit 210.
在另一實施例中,電流控制電路210更包含電壓供應N型金氧半電晶體MN7,電壓供應N型金氧半電晶體MN7包含第一端以及第二端。前述第二端用以接收高電壓電位VGH,第一端電性耦接於峰值電流控制支路214的控制P型金氧半電晶體MP1之第二端,而其控制端可接受一外部電位VDD。舉例而言,第二電位VDDX可為VDD-Vth(閾值電壓)。In another embodiment, the current control circuit 210 further includes a voltage supply N-type MOS transistor MN7, and the voltage supply N-type MOS transistor MN7 includes a first end and a second end. The second end is configured to receive the high voltage potential VGH, the first end is electrically coupled to the second end of the P-type MOS transistor MP1 of the peak current control branch 214, and the control terminal can receive an external potential VDD. For example, the second potential VDDX may be VDD-Vth (threshold voltage).
在此設計架構下,當控制P型金氧半電晶體MP1導通時,電流鏡212第一支路上之第一N型金氧半電晶體MN2的第二端,由高電壓電位VGH汲取電流,而非向第二電位VDDX汲取電流以產生前述峰值電流。如此,可使整體電路運作更加穩定。Under the design architecture, when the P-type MOS transistor MP1 is controlled to be turned on, the second end of the first N-type MOS transistor MN2 on the first branch of the current mirror 212 is drawn by the high voltage potential VGH. Rather than drawing a current to the second potential VDDX to generate the aforementioned peak current. In this way, the overall circuit operation can be made more stable.
上述驅動級220之第一驅動支路222包含電流源223、 第二箝位N型金氧半電晶體MN4以及第一開關P型金氧半電晶體MP2。第二箝位N型金氧半電晶體MN4之控制端用以接收參考電壓VM,其第一端電性耦接於控制端點N2以及電流源223。第一開關P型金氧半電晶體MP2之控制端用以接收一反相開關信號IN,而其第一端電性耦接於第二箝位N型金氧半電晶體MN4之第二端。The first driving branch 222 of the driving stage 220 includes a current source 223, The second clamp N-type oxynitride MN4 and the first switch P-type MOS transistor M02. The control terminal of the second clamp N-type MOS transistor MN4 is configured to receive the reference voltage VM, and the first end thereof is electrically coupled to the control terminal N2 and the current source 223. The control end of the first switch P-type MOS transistor MP2 is configured to receive an inverted switch signal IN, and the first end thereof is electrically coupled to the second end of the second clamp N-type MOS transistor MN4 .
再者,上述驅動級220之第二驅動支路224包含電流供應N型金氧半電晶體MN6、第三箝位N型金氧半電晶體MN5以及第二開關P型金氧半電晶體MP3。電流供應N型金氧半電晶體MN6之控制端電性耦接於控制端點N2,而其第一端用以接收第一電位VEE。第三箝位N型金氧半電晶體MN5之控制端用以接收參考電壓VM,其第一端電性耦接於電流供應N型金氧半電晶體MN6之第二端,且其第一端輸出驅動電壓至功率金氧半電晶體MN0之控制端。第二開關P型金氧半電晶體MP3之控制端用以接收開關信號IN,而其第一端電性耦接於第三箝位N型金氧半電晶體MN5之第二端。Furthermore, the second driving branch 224 of the driving stage 220 includes a current supply N-type MOS transistor MN6, a third clamp N-type MOS transistor MN5, and a second switch P-type MOS transistor MP3. . The control terminal of the current supply N-type MOS transistor MN6 is electrically coupled to the control terminal N2, and the first terminal thereof is configured to receive the first potential VEE. The control terminal of the third clamp N-type MOS transistor MN5 is configured to receive the reference voltage VM, and the first end thereof is electrically coupled to the second end of the current supply N-type MOS transistor MN6, and the first end thereof The terminal outputs a driving voltage to the control terminal of the power MOS transistor MN0. The control end of the second switch P-type MOS transistor MP3 is configured to receive the switch signal IN, and the first end thereof is electrically coupled to the second end of the third clamp N-type MOS transistor MN5.
在本實施例中,於電性操作上,當電流控制電路210中峰值電流控制支路214之電容C1的第一端接收之開關信號IN為低態時,電容C1輸出耦合信號以使控制P型金氧半電晶體MP1導通,且驅動級220中第二驅動支路224之第二開關P型金氧半電晶體MP3導通,電流鏡212之第一電流支路產生峰值電流,而電流鏡212之第二電流支路相應地由控制端點N2汲取電流,控制端點N2的電壓下降。由於控制端點N2的電壓即為電流供應N型金氧半電晶體 MN6之控制端接收的電壓,因而電流供應N型金氧半電晶體MN6將在控制端點N2的電壓下降下關閉。In the embodiment, when the switching signal IN received by the first end of the capacitor C1 of the peak current control branch 214 in the current control circuit 210 is in a low state, the capacitor C1 outputs a coupling signal to make the control P. The MOS transistor MP1 is turned on, and the second switch P-type MOS transistor MP3 of the second driving branch 224 in the driving stage 220 is turned on, and the first current branch of the current mirror 212 generates a peak current, and the current mirror The second current branch of 212 accordingly draws current from control terminal N2, controlling the voltage drop at terminal N2. Since the voltage of the control terminal N2 is the current supply N-type MOS semi-transistor The voltage received by the control terminal of MN6, and thus the current supply N-type MOS transistor MN6, will be turned off at the voltage drop of control terminal N2.
此時,第二驅動支路224之第二開關P型金氧半電晶體MP3的第一端會提供電壓,藉使第三箝位N型金氧半電晶體MN5之第一端輸出至功率金氧半電晶體MN0的控制端之驅動電壓Vp上升,以開啟功率金氧半電晶體MN0。At this time, the first end of the second switch P-type MOS transistor MP3 of the second driving branch 224 supplies a voltage, so that the first end of the third clamp N-type MOS transistor MN5 is output to the power. The driving voltage Vp of the control terminal of the metal oxide semiconductor MN0 rises to turn on the power MOS transistor MN0.
在一實施例中,上述第一電位VEE為負電位,而第二電位VDDX大於第一電位VEE。In an embodiment, the first potential VEE is a negative potential, and the second potential VDDX is greater than the first potential VEE.
由上述本發明實施方式可知,應用本發明具有下列優點。本發明實施例藉由提供一種驅動電路及其中之電流控制電路,藉以改善功率電晶體之傳遞延遲(propagation delay)現象,並進一步將傳遞延遲現象縮小至50奈秒以內。再者,於迅速開啟功率金氧半電晶體之後,由於電流控制電路中峰值電流控制支路之控制金氧半電晶體會被關閉,因此,電流控制電路上將不會有無謂的電能耗損。It will be apparent from the above-described embodiments of the present invention that the application of the present invention has the following advantages. The embodiment of the present invention improves the propagation delay phenomenon of the power transistor by providing a driving circuit and a current control circuit therein, and further reduces the transmission delay phenomenon to within 50 nanoseconds. Furthermore, after the power MOS transistor is quickly turned on, the MOS transistor will be turned off due to the control of the peak current control branch in the current control circuit, so there will be no unnecessary power loss on the current control circuit.
雖然本揭示內容已以實施方式揭露如上,然其並非用以限定本揭示內容,任何熟習此技藝者,在不脫離本揭示內容之精神和範圍內,當可作各種之更動與潤飾,因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application.
100、200‧‧‧驅動電路100, 200‧‧‧ drive circuit
110、210‧‧‧電流控制電路110, 210‧‧‧ Current control circuit
112、212‧‧‧電流鏡112, 212‧‧‧current mirror
114、214‧‧‧峰值電流控制支路114, 214‧‧‧ Peak current control branch
120、220‧‧‧驅動級120, 220‧‧‧ drive level
122、222‧‧‧第一驅動支路122, 222‧‧‧ first drive branch
123、223‧‧‧電流源123, 223‧‧‧ current source
124、224‧‧‧第二驅動支路124, 224‧‧‧Second drive branch
為讓本揭示內容之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖為本揭示內容一實施例中,一種驅動電路之電 路示意圖;以及第2圖為本揭示內容另一實施例中,一種驅動電路之電路示意圖。The above and other objects, features, advantages and embodiments of the present disclosure will be more apparent and understood. The description of the drawings is as follows: FIG. 1 is a diagram showing the power of a driving circuit in an embodiment of the disclosure. A schematic diagram of a circuit; and FIG. 2 is a circuit diagram of a driving circuit in another embodiment of the disclosure.
100‧‧‧驅動電路100‧‧‧ drive circuit
110‧‧‧電流控制電路110‧‧‧ Current Control Circuit
112‧‧‧電流鏡112‧‧‧current mirror
114‧‧‧峰值電流控制支路114‧‧‧ Peak current control branch
120‧‧‧驅動級120‧‧‧Driver
122‧‧‧第一驅動支路122‧‧‧First drive branch
123‧‧‧電流源123‧‧‧current source
124‧‧‧第二驅動支路124‧‧‧Second drive branch
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TW101126806A TWI470398B (en) | 2012-07-25 | 2012-07-25 | Driver circuit and current control circuit thereof |
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TW201405275A TW201405275A (en) | 2014-02-01 |
TWI470398B true TWI470398B (en) | 2015-01-21 |
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TW101126806A TWI470398B (en) | 2012-07-25 | 2012-07-25 | Driver circuit and current control circuit thereof |
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TW201817169A (en) * | 2016-10-21 | 2018-05-01 | 燦瑞半導體有限公司 | Gate driving circuit for driving high voltage or negative voltage speeds up transmission of circuit signals by way of utilizing instantaneous current |
CN111124031B (en) * | 2018-10-31 | 2021-07-13 | 圣邦微电子(北京)股份有限公司 | Test control circuit of current-limiting circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5177374A (en) * | 1990-10-03 | 1993-01-05 | International Business Machines Corporation | Current mode gate drive for power mos transistors |
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5177374A (en) * | 1990-10-03 | 1993-01-05 | International Business Machines Corporation | Current mode gate drive for power mos transistors |
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