TWI410728B - Pixel structure and manufacturing method thereof - Google Patents
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本發明是有關於一種畫素結構及其製作方法，且特別是有關於一種邊界電場切換型(fringe field switching，FFS)顯示器的畫素結構及其製作方法。 The invention relates to a pixel structure and a manufacturing method thereof, and in particular to a pixel structure of a boundary electric field switching (FFS) display and a manufacturing method thereof.
目前市場對於薄膜電晶體液晶顯示面板(TFT liquid crystal display panel)皆朝向高對比、無灰階反轉、高亮度、高色飽和度、快速反應以及廣視角等方向發展。常見的廣視角技術包括：扭轉向列型(twisted nematic，TN)液晶加上廣視角膜(wide viewing film)、共平面切換型(in-plane switching，IPS)液晶顯示面板、邊界電場切換型液晶顯示面板與多域垂直配向型(multi-domain vertical alignment，MVA)液晶顯示面板。 At present, the TFT liquid crystal display panels are oriented toward high contrast, gray scale inversion, high brightness, high color saturation, fast response, and wide viewing angle. Common wide viewing angle technologies include: twisted nematic (TN) liquid crystal plus wide viewing film, in-plane switching (IPS) liquid crystal display panel, boundary electric field switching liquid crystal The display panel and the multi-domain vertical alignment (MVA) liquid crystal display panel.
以邊界電場切換型液晶顯示面板為例，其具有廣視角以及低色偏等優點特性。在低溫多晶矽邊界電場切換型液晶顯示面板的製程中，在製作畫素結構時，通常會使用到10至11道光罩製程(非晶矽邊界電場切換型液晶顯示面板製程則為7至8道製程)。如此一來，必須花費較多的製程時間以及較高的成本，且製程步驟也非常繁雜。 Taking the boundary electric field switching type liquid crystal display panel as an example, it has the advantages of wide viewing angle and low color shift. In the process of low-temperature polycrystalline germanium boundary electric field switching type liquid crystal display panel, 10 to 11 mask processes are usually used in the production of pixel structure (amorphous germanium boundary electric field switching type liquid crystal display panel process is 7 to 8 processes) ). As a result, it takes a lot of process time and high cost, and the process steps are very complicated.
此外，在邊界電場切換型液晶顯示面板的畫素結構中具有二層透明導電氧化層(例如銦錫氧化物(indium tin oxide，ITO)層)，且在形成第一層透明導電氧化層之前會 先形成一層平坦層，然後再將第一層透明導電氧化層形成於平坦層上，以及於第一層透明導電氧化層上依序形成保護層(passivation layer)與第二層透明導電氧化層上。因此，邊界電場切換型液晶顯示面板的畫素結構會有較多層次絕緣膜堆疊的問題，因而導致畫素結構的光穿透率下降。 In addition, in the pixel structure of the boundary electric field switching type liquid crystal display panel, there are two transparent conductive oxide layers (for example, an indium tin oxide (ITO) layer), and before forming the first transparent conductive oxide layer, Forming a flat layer first, then forming a first transparent conductive oxide layer on the flat layer, and sequentially forming a passivation layer and a second transparent conductive oxide layer on the first transparent conductive oxide layer. . Therefore, the pixel structure of the boundary electric field switching type liquid crystal display panel has a problem that a plurality of layers of the insulating film are stacked, and thus the light transmittance of the pixel structure is lowered.
另外，在上述的邊界電場切換型液晶顯示面板的製程中，在形成平坦層及第一層透明導電氧化層之後，通常會藉由化學氣相沈積製程來形成保護層，因為化學氣相沈積的高溫製程容易影響到其下方的平坦層而產生污染(如有機物、碳等)的問題。 In addition, in the above process of the boundary electric field switching type liquid crystal display panel, after the flat layer and the first transparent conductive oxide layer are formed, the protective layer is usually formed by a chemical vapor deposition process because of chemical vapor deposition. High-temperature processes tend to affect the flat layer beneath it and cause contamination (such as organic matter, carbon, etc.).
本發明提供一種畫素結構，其具有較少的膜層。 The present invention provides a pixel structure having fewer film layers.
本發明另提供一種畫素結構的製作方法，其具有較少的製程步驟。 The present invention further provides a method of fabricating a pixel structure having fewer process steps.
本發明提出一種畫素結構，其包括基板、薄膜電晶體、第一電極、平坦層以及第二電極。薄膜電晶體配置於基板上。薄膜電晶體具有汲極。第一電極配置於基板上，且第一電極覆蓋並且接觸汲極。平坦層配置於基板上，並且覆蓋薄膜電晶體以及第一電極。平坦層具有對應於第一電極的凹陷。第二電極配置於平坦層上。第二電極包括相互平行的多個條狀電極圖案。這些條狀電極圖案位於凹陷內。 The present invention provides a pixel structure including a substrate, a thin film transistor, a first electrode, a flat layer, and a second electrode. The thin film transistor is disposed on the substrate. The thin film transistor has a drain. The first electrode is disposed on the substrate, and the first electrode covers and contacts the drain. The flat layer is disposed on the substrate and covers the thin film transistor and the first electrode. The flat layer has a recess corresponding to the first electrode. The second electrode is disposed on the flat layer. The second electrode includes a plurality of strip electrode patterns that are parallel to each other. These strip electrode patterns are located within the recess.
依照本發明實施例所述之畫素結構，更包括圖案化半 導體層、閘絕緣層、圖案化第一導電層、中間介電層(interlayer dielectric，ILD)以及圖案化第二導電層。圖案化半導體層配置於基板上。圖案化半導體層包括半導體圖案以及下電極圖案，其中半導體圖案具有通道區以及位於通道區兩側的源極區以及汲極區。閘絕緣層配置於基板上，並且覆蓋半導體圖案與下電極圖案。圖案化第一導電層配置於閘絕緣層上。圖案化第一導電層包括閘極圖案以及上電極圖案，其中閘極圖案位於通道區的上方，而上電極圖案位於下電極圖案的上方。中間介電層配置於閘絕緣層上，並且覆蓋閘極圖案以及上電極圖案。圖案化第二導電層配置於中間介電層上。圖案化第二導電層包括源極圖案、汲極圖案以及接墊圖案。源極圖案經由貫穿中間介電層與閘絕緣層的第一貫孔而電性連接至源極區，以作為薄膜電晶體的源極。汲極圖案經由貫穿中間介電層與閘絕緣層的第二貫孔而電性連接至汲極區與下電極圖案，以作為薄膜電晶體的汲極，且汲極圖案的一部分與上電極圖案重疊。接墊圖案經由貫穿中間介電層的第三貫孔而電性連接至上電極圖案。第一電極配置於中間介電層上，且第一電極覆蓋並且接觸汲極圖案。平坦層配置於中間介電層上，並且覆蓋源極圖案、汲極圖案、第一電極以及接墊圖案。平坦層具有第四貫孔，此第四貫孔暴露出部分的接墊圖案。第二電極經由第四貫孔而電性連接至接墊圖案以及上電極圖案。 A pixel structure according to an embodiment of the invention further includes a patterned half a conductor layer, a gate insulating layer, a patterned first conductive layer, an intermediate dielectric layer (ILD), and a patterned second conductive layer. The patterned semiconductor layer is disposed on the substrate. The patterned semiconductor layer includes a semiconductor pattern and a lower electrode pattern, wherein the semiconductor pattern has a channel region and a source region and a drain region on both sides of the channel region. The gate insulating layer is disposed on the substrate and covers the semiconductor pattern and the lower electrode pattern. The patterned first conductive layer is disposed on the gate insulating layer. The patterned first conductive layer includes a gate pattern and an upper electrode pattern, wherein the gate pattern is above the channel region and the upper electrode pattern is above the lower electrode pattern. The intermediate dielectric layer is disposed on the gate insulating layer and covers the gate pattern and the upper electrode pattern. The patterned second conductive layer is disposed on the intermediate dielectric layer. The patterned second conductive layer includes a source pattern, a drain pattern, and a pad pattern. The source pattern is electrically connected to the source region via a first via hole penetrating the intermediate dielectric layer and the gate insulating layer to serve as a source of the thin film transistor. The drain pattern is electrically connected to the drain region and the lower electrode pattern via a second through hole penetrating the intermediate dielectric layer and the gate insulating layer to serve as a drain of the thin film transistor, and a portion of the drain pattern and the upper electrode pattern overlapping. The pad pattern is electrically connected to the upper electrode pattern via a third through hole penetrating the intermediate dielectric layer. The first electrode is disposed on the intermediate dielectric layer, and the first electrode covers and contacts the drain pattern. The flat layer is disposed on the intermediate dielectric layer and covers the source pattern, the drain pattern, the first electrode, and the pad pattern. The flat layer has a fourth through hole that exposes a portion of the pad pattern. The second electrode is electrically connected to the pad pattern and the upper electrode pattern via the fourth through hole.
依照本發明實施例所述之畫素結構，上述之半導體圖 案與下電極圖案相連接，而第二貫孔暴露出半導體圖案與下電極圖案的連接處，以使汲極圖案同時電性連接到半導體圖案與下電極圖案。 A pixel structure according to an embodiment of the present invention, the semiconductor pattern described above The method is connected to the lower electrode pattern, and the second through hole exposes a connection between the semiconductor pattern and the lower electrode pattern, so that the drain pattern is electrically connected to the semiconductor pattern and the lower electrode pattern at the same time.
依照本發明實施例所述之畫素結構，上述之半導體圖案例如為第一型摻雜，而下電極圖案例如為第二型摻雜。 According to the pixel structure of the embodiment of the invention, the semiconductor pattern is, for example, a first type doping, and the lower electrode pattern is, for example, a second type doping.
依照本發明實施例所述之畫素結構，上述之第一型摻雜例如為N型摻雜，而第二型摻雜例如為P型摻雜。 According to the pixel structure of the embodiment of the invention, the first type doping is, for example, N-type doping, and the second type doping is, for example, P-type doping.
依照本發明實施例所述之畫素結構，上述之圖案化半導體層的材質例如為多晶矽，其中對應於第一電極的凹陷處之平坦層的厚度例如介於5000 Å至10000 Å之間。 According to the pixel structure of the embodiment of the invention, the material of the patterned semiconductor layer is, for example, a polysilicon, wherein the thickness of the planar layer corresponding to the recess of the first electrode is, for example, between 5000 Å and 10000 Å.
依照本發明實施例所述之畫素結構，更包括圖案化第一導電層、閘絕緣層、圖案化半導體層以及圖案化第二導電層。圖案化第一導電層配置於基板上。圖案化第一導電層包括閘極圖案以及電極圖案。閘絕緣層配置於基板上，並且覆蓋圖案化第一導電層。圖案化半導體層配置於閘絕緣層上。圖案化半導體層包括半導體圖案，此半導體圖案位於閘極圖案的上方。圖案化第二導電層配置於閘絕緣層上。圖案化第二導電層包括源極圖案以及汲極圖案。源極圖案與汲極圖案分別位於半導體圖案的兩側，以分別作為薄膜電晶體的源極以及汲極，且汲極圖案的一部分與電極圖案重疊。第一電極配置於閘絕緣層上，且第一電極覆蓋並且接觸該汲極圖案。平坦層配置於閘絕緣層上，並且覆蓋源極圖案、汲極圖案以及第一電極。第二電極穿過平坦層與閘絕緣層而電性連接至電極圖案。 The pixel structure according to the embodiment of the invention further includes a patterned first conductive layer, a gate insulating layer, a patterned semiconductor layer, and a patterned second conductive layer. The patterned first conductive layer is disposed on the substrate. The patterned first conductive layer includes a gate pattern and an electrode pattern. The gate insulating layer is disposed on the substrate and covers the patterned first conductive layer. The patterned semiconductor layer is disposed on the gate insulating layer. The patterned semiconductor layer includes a semiconductor pattern that is over the gate pattern. The patterned second conductive layer is disposed on the gate insulating layer. The patterned second conductive layer includes a source pattern and a drain pattern. The source pattern and the drain pattern are respectively located on both sides of the semiconductor pattern to serve as a source and a drain of the thin film transistor, respectively, and a portion of the drain pattern overlaps the electrode pattern. The first electrode is disposed on the gate insulating layer, and the first electrode covers and contacts the drain pattern. The flat layer is disposed on the gate insulating layer and covers the source pattern, the drain pattern, and the first electrode. The second electrode is electrically connected to the electrode pattern through the flat layer and the gate insulating layer.
依照本發明實施例所述之畫素結構，上述之圖案化半導體層的材質例如為非晶矽。 According to the pixel structure of the embodiment of the invention, the material of the patterned semiconductor layer is, for example, amorphous germanium.
本發明提出一種畫素結構的製作方法，此方法是先提供半成品。此半成品包括基板以及薄膜電晶體。薄膜電晶體配置於基板上，且薄膜電晶體具有汲極。然後，形成第一電極於基板上，此第一電極覆蓋並且接觸部分的汲極。接著，形成平坦層於基板上，此平坦層覆蓋薄膜電晶體以及第一電極。平坦層具有凹陷，此凹陷對應於第一電極。之後，形成第二電極於平坦層上，此第二電極包括相互平行的多個條狀電極圖案，且這些條狀電極圖案位於凹陷內。 The invention provides a method for fabricating a pixel structure, which first provides a semi-finished product. This semi-finished product includes a substrate and a thin film transistor. The thin film transistor is disposed on the substrate, and the thin film transistor has a drain. Then, a first electrode is formed on the substrate, and the first electrode covers and contacts a portion of the drain. Next, a flat layer is formed on the substrate, the flat layer covering the thin film transistor and the first electrode. The flat layer has a recess corresponding to the first electrode. Thereafter, a second electrode is formed on the flat layer, the second electrode including a plurality of strip electrode patterns parallel to each other, and the strip electrode patterns are located in the recess.
依照本發明實施例所述之畫素結構的製作方法，上述之半成品的形成方法例如是先形成半導體材料層於基板上。然後，對半導體材料層的第一部分進行第一型通道摻雜(channel doping)或第二型通道摻雜。接著，對半導體材料層的第二部分進行第二型摻雜，以形成下電極圖案。而後，形成閘絕緣層於基板上，此閘絕緣層覆蓋半導體材料層。繼之，形成圖案化第一導電層於閘絕緣層上，此圖案化第一導電層包括閘極圖案以及上電極圖案，且上電極圖案位於下電極圖案的上方。隨後，以閘極圖案為罩幕來對第一部分的半導體材料層進行第一型摻雜，以形成半導體圖案，此半導體圖案具有通道區以及位於通道區兩側的源極區以及汲極區。然後，形成中間介電層於閘絕緣層上。接著，形成貫穿中間介電層與閘絕緣層的第一貫孔、貫穿中間介電層與閘絕緣層的第二貫孔以及貫穿中間介電層的 第三貫孔。第一貫孔暴露出部分的源極區，第二貫孔暴露出部分的汲極區與部分的下電極圖案，而第三貫孔暴露出部分的上電極圖案。而後，形成圖案化第二導電層於中間介電層上，圖案化第二導電層包括源極圖案、汲極圖案以及接墊圖案。源極圖案經由第一貫孔而電性連接至源極區，以作為薄膜電晶體的源極。汲極圖案經由第二貫孔而電性連接至汲極區與下電極圖案，以作為薄膜電晶體的汲極，且汲極圖案的一部分與上電極圖案重疊。接墊圖案經由第三貫孔而電性連接至上電極圖案。之後，形成貫穿平坦層的第四貫孔，此第四貫孔暴露出部分的接墊圖案，以使第二電極經由第四貫孔而電性連接至接墊圖案以及上電極圖案。 According to the method for fabricating the pixel structure according to the embodiment of the invention, the method for forming the semi-finished product is, for example, first forming a semiconductor material layer on the substrate. A first type of channel doping or a second type of channel doping is then performed on the first portion of the layer of semiconductor material. Next, a second type of doping of the second portion of the layer of semiconductor material is performed to form a lower electrode pattern. Then, a gate insulating layer is formed on the substrate, and the gate insulating layer covers the semiconductor material layer. Then, a patterned first conductive layer is formed on the gate insulating layer, the patterned first conductive layer includes a gate pattern and an upper electrode pattern, and the upper electrode pattern is located above the lower electrode pattern. Subsequently, the first portion of the semiconductor material layer is first doped with a gate pattern as a mask to form a semiconductor pattern having a channel region and a source region and a drain region on both sides of the channel region. Then, an intermediate dielectric layer is formed on the gate insulating layer. Next, a first through hole penetrating through the intermediate dielectric layer and the gate insulating layer, a second through hole penetrating through the intermediate dielectric layer and the gate insulating layer, and a through hole penetrating through the intermediate dielectric layer are formed. The third through hole. The first uniform hole exposes a portion of the source region, the second via exposes a portion of the drain region and a portion of the lower electrode pattern, and the third via exposes a portion of the upper electrode pattern. Then, a patterned second conductive layer is formed on the intermediate dielectric layer, and the patterned second conductive layer includes a source pattern, a drain pattern, and a pad pattern. The source pattern is electrically connected to the source region via the first via hole to serve as a source of the thin film transistor. The drain pattern is electrically connected to the drain region and the lower electrode pattern via the second via hole as a drain of the thin film transistor, and a portion of the drain pattern overlaps with the upper electrode pattern. The pad pattern is electrically connected to the upper electrode pattern via the third through hole. Thereafter, a fourth through hole penetrating through the flat layer is formed, and the fourth through hole exposes a portion of the pad pattern such that the second electrode is electrically connected to the pad pattern and the upper electrode pattern via the fourth through hole.
依照本發明實施例所述之畫素結構的製作方法，上述之第一型通道摻雜與第一型摻雜例如為N型摻雜，而第二型通道摻雜與第二型摻雜例如為P型摻雜。 According to the method for fabricating the pixel structure according to the embodiment of the invention, the first type channel doping and the first type doping are, for example, N-type doping, and the second type channel doping and the second type doping, for example. It is doped with P type.
依照本發明實施例所述之畫素結構的製作方法，上述之平坦層之凹陷的形成方法例如是對平坦層進行曝光與微影製程，其中對應於第一電極的該凹陷處之該平坦層的厚度例如介於5000 Å至10000 Å之間。 According to the method for fabricating the pixel structure according to the embodiment of the present invention, the method for forming the recess of the flat layer is, for example, performing an exposure and lithography process on the flat layer, wherein the flat layer corresponding to the recess of the first electrode The thickness is, for example, between 5000 Å and 10000 Å.
依照本發明實施例所述之畫素結構的製作方法，上述之半成品的形成方法例如是先形成圖案化第一導電層於基板上，此圖案化第一導電層包括閘極圖案以及電極圖案。然後，形成閘絕緣層於基板上，以覆蓋圖案化第一導電層。接著，形成圖案化半導體層於閘絕緣層上，此圖案化半導 體層包括半導體圖案，此半導體圖案位於閘極圖案的上方。而後，形成圖案化第二導電層於閘絕緣層上，此圖案化第二導電層包括源極圖案以及汲極圖案。源極圖案與汲極圖案分別位於半導體圖案的兩側，以分別作為薄膜電晶體的源極以及汲極，且汲極圖案的一部分與電極圖案重疊。之後，形成貫穿平坦層以及閘絕緣層的貫孔，此貫孔暴露出部分的電極圖案，以使第二電極經由貫孔而電性連接至電極圖案。 According to the method for fabricating the pixel structure according to the embodiment of the invention, the method for forming the semi-finished product is, for example, first forming a patterned first conductive layer on the substrate, and the patterned first conductive layer comprises a gate pattern and an electrode pattern. Then, a gate insulating layer is formed on the substrate to cover the patterned first conductive layer. Then, forming a patterned semiconductor layer on the gate insulating layer, the patterned semiconductor The bulk layer includes a semiconductor pattern that is above the gate pattern. Then, a patterned second conductive layer is formed on the gate insulating layer, and the patterned second conductive layer includes a source pattern and a drain pattern. The source pattern and the drain pattern are respectively located on both sides of the semiconductor pattern to serve as a source and a drain of the thin film transistor, respectively, and a portion of the drain pattern overlaps the electrode pattern. Thereafter, a through hole penetrating through the flat layer and the gate insulating layer is formed, and the through hole exposes a portion of the electrode pattern such that the second electrode is electrically connected to the electrode pattern via the through hole.
基於上述，本發明將作為源極/汲極的導電層與第一電極皆形成於同一層介電層上，且在第一電極與第二電極之間形成平坦層來代替習知技術中的保護層，因此與習知技術相比具有較少的製程步驟以及減少了光罩的使用數目。 Based on the above, the present invention forms a conductive layer as a source/drain and a first electrode on the same dielectric layer, and forms a flat layer between the first electrode and the second electrode instead of the prior art. The protective layer therefore has fewer process steps and reduces the number of reticle uses compared to conventional techniques.
此外，在本發明的畫素結構中，由於源極/汲極的導電層與第一電極皆形成於同一層介電層上，因此不用其他絕緣膜將源極/汲極的導電層與第一電極隔開，可以有效地減少畫素結構中其他絕緣膜的使用，進而提高畫素結構的光穿透率。 In addition, in the pixel structure of the present invention, since the source/drain conductive layer and the first electrode are both formed on the same dielectric layer, the source/drain conductive layer and the first insulating layer are not used. The separation of one electrode can effectively reduce the use of other insulating films in the pixel structure, thereby improving the light transmittance of the pixel structure.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the present invention will be more apparent from the following description.
圖1A至圖1I為依照本發明之第一實施例所繪示的畫素結構的製作流程的上視示意圖。圖2A至圖2I為依照本 發明之第一實施例所繪示的畫素結構的製作流程的剖面示意圖。在本實施例中，為了便於說明，僅繪示出一個畫素區，但本發明並不限於此。 1A to FIG. 1I are schematic top views of a process of fabricating a pixel structure according to a first embodiment of the present invention. 2A to 2I are in accordance with this A schematic cross-sectional view showing a process of fabricating a pixel structure according to the first embodiment of the invention. In the present embodiment, for convenience of explanation, only one pixel area is illustrated, but the present invention is not limited thereto.
首先，請同時參照圖1A與圖2A，於基板100上形成絕緣層102。基板100的材料例如為玻璃、塑膠或其他合適的材料。絕緣層102的材料例如為氧化物或氮化物。然後，在基板100的畫素區100a中，於絕緣層102上形成圖案化半導體材料層104。圖案化半導體材料層104的材料例如為多晶矽。在圖1A中，為了使圖式清楚，因此未將絕緣層102繪示出。 First, please refer to FIG. 1A and FIG. 2A simultaneously to form an insulating layer 102 on the substrate 100. The material of the substrate 100 is, for example, glass, plastic or other suitable material. The material of the insulating layer 102 is, for example, an oxide or a nitride. Then, a patterned semiconductor material layer 104 is formed on the insulating layer 102 in the pixel region 100a of the substrate 100. The material of the patterned semiconductor material layer 104 is, for example, polysilicon. In FIG. 1A, the insulating layer 102 is not shown in order to make the drawing clear.
接著，請同時參照圖1B與圖2B，對圖案化半導體材料層104的第一部分進行摻雜，以形成摻雜區104a，此摻雜可為第一型或第二型摻雜，在本實施例中係以第一型摻雜為例，但不以此為限。部分的摻雜區104a可作為薄膜電晶體的通道區，因此上述的摻雜亦可稱為通道摻雜。在圖1B中，為了使圖式清楚，因此未將絕緣層102繪示出。 Next, referring to FIG. 1B and FIG. 2B, the first portion of the patterned semiconductor material layer 104 is doped to form a doped region 104a, which may be a first type or a second type doping, in this implementation. In the example, the first type doping is taken as an example, but not limited thereto. A portion of the doped region 104a can serve as a channel region for the thin film transistor, and thus the above doping can also be referred to as channel doping. In FIG. 1B, the insulating layer 102 is not shown in order to make the drawing clear.
而後，請同時參照圖1C與圖2C，對圖案化半導體材料層104的第二部分進行第二型摻雜，以形成下電極圖案104b。在本實施例中，第一型摻雜為N型摻雜，而第二型摻雜為P型摻雜。繼之，於基板100上形成閘絕緣層106。閘絕緣層106覆蓋未經摻雜的圖案化半導體材料層104、摻雜區104a、下電極圖案104b與絕緣層102。閘絕緣層106的材料例如為氧化物、氮化物或其他合適的介電材料。在圖1C中，為了使圖式清楚，因此未將絕緣層102 與閘絕緣層106繪示出。 Then, referring to FIG. 1C and FIG. 2C simultaneously, the second portion of the patterned semiconductor material layer 104 is doped in a second type to form the lower electrode pattern 104b. In this embodiment, the first type doping is N-type doping, and the second type doping is P-type doping. Next, a gate insulating layer 106 is formed on the substrate 100. The gate insulating layer 106 covers the undoped patterned semiconductor material layer 104, the doped region 104a, the lower electrode pattern 104b, and the insulating layer 102. The material of the gate insulating layer 106 is, for example, an oxide, a nitride or other suitable dielectric material. In FIG. 1C, in order to make the drawing clear, the insulating layer 102 is not The gate insulating layer 106 is depicted.
然後，請同時參照圖1D與圖2D，於閘絕緣層106上形成圖案化第一導電層108。圖案化第一導電層108的材料例如為金屬。圖案化第一導電層108包括閘極圖案108a以及上電極圖案108b。上電極圖案108b位於下電極圖案104b的上方而與其至少部份重疊。接著，以閘極圖案108a為罩幕來對圖案化半導體材料層104的第一部分(即摻雜區104a)進行第一型摻雜，以形成半導體圖案。此半導體圖案具有通道區(位於閘極圖案108a下方且在此步驟中未被摻雜的摻雜區104a)以及位於通道區兩側的摻雜區104c。摻雜區104c作為薄膜電晶體的源極區與汲極區。在圖1D中，為了使圖式清楚，因此未將絕緣層102與閘絕緣層106繪示出。 Then, referring to FIG. 1D and FIG. 2D simultaneously, a patterned first conductive layer 108 is formed on the gate insulating layer 106. The material of the patterned first conductive layer 108 is, for example, a metal. The patterned first conductive layer 108 includes a gate pattern 108a and an upper electrode pattern 108b. The upper electrode pattern 108b is located above the lower electrode pattern 104b and at least partially overlaps it. Next, the first portion of the patterned semiconductor material layer 104 (ie, the doped region 104a) is first doped with the gate pattern 108a as a mask to form a semiconductor pattern. This semiconductor pattern has a channel region (doped regions 104a under the gate pattern 108a and not doped in this step) and doped regions 104c on both sides of the channel region. The doped region 104c serves as a source region and a drain region of the thin film transistor. In FIG. 1D, the insulating layer 102 and the gate insulating layer 106 are not depicted for clarity of the drawing.
特別一提的是，在圖1D與圖2D所述的步驟中，所形成的上電極圖案108b位於下電極圖案104b的上方，因此上電極圖案108b、下電極圖案104b以及位於二者之間的閘絕緣層106即可構成儲存電容結構。 In particular, in the steps described in FIGS. 1D and 2D, the formed upper electrode pattern 108b is located above the lower electrode pattern 104b, thus the upper electrode pattern 108b, the lower electrode pattern 104b, and the The gate insulating layer 106 can constitute a storage capacitor structure.
而後，請同時參照圖1E與圖2E，於閘絕緣層106上形成中間介電層110。中間介電層110覆蓋閘極圖案108a、上電極圖案108b以及閘絕緣層106。中間介電層110的材料例如為氧化物、氮化物或其他合適的介電材料。繼之，形成貫穿中間介電層110與閘絕緣層106的第一貫孔112與第二貫孔114以及貫穿中間介電層110的第三貫孔116。第一貫孔112暴露出部分的摻雜區104c。第二貫孔 114同時暴露出部分的摻雜區104c與部分的下電極圖案104b。第三貫孔116暴露出部分的上電極圖案108b。在圖1E中，為了使圖式清楚，因此未將絕緣層102、閘絕緣層106與中間介電層110繪示出。 Then, referring to FIG. 1E and FIG. 2E, an intermediate dielectric layer 110 is formed on the gate insulating layer 106. The intermediate dielectric layer 110 covers the gate pattern 108a, the upper electrode pattern 108b, and the gate insulating layer 106. The material of the intermediate dielectric layer 110 is, for example, an oxide, a nitride or other suitable dielectric material. Then, a first through hole 112 and a second through hole 114 penetrating through the intermediate dielectric layer 110 and the gate insulating layer 106 and a third through hole 116 penetrating through the intermediate dielectric layer 110 are formed. The first uniform hole 112 exposes a portion of the doped region 104c. Second through hole 114 simultaneously exposes a portion of the doped region 104c and a portion of the lower electrode pattern 104b. The third through hole 116 exposes a portion of the upper electrode pattern 108b. In FIG. 1E, the insulating layer 102, the gate insulating layer 106, and the intermediate dielectric layer 110 are not depicted for clarity of the drawing.
接著，請同時參照圖1F與圖2F，於中間介電層110上形成圖案化第二導電層118。圖案化第二導電層118的材料例如為金屬。圖案化第二導電層118包括源極圖案118a、汲極圖案118b、接墊圖案118c以及資料線圖案118d。源極圖案118a經由第一貫孔112而電性連接至作為源極區的摻雜區104c，以作為薄膜電晶體的源極。汲極圖案118b經由第二貫孔114而電性連接至作為汲極區的下電極圖案104b與摻雜區104c，以作為薄膜電晶體的汲極。此外，汲極圖案118b的一部分與上電極圖案108b重疊，因此汲極圖案118b、上電極圖案108b以及位於二者之間的中間介電層110構成儲存電容結構。接墊圖案118c經由第三貫孔116而電性連接至上電極圖案108b。在圖1F中，為了使圖式清楚，因此未將絕緣層102、閘絕緣層106與中間介電層110繪示出。 Next, please refer to FIG. 1F and FIG. 2F to form a patterned second conductive layer 118 on the intermediate dielectric layer 110. The material of the patterned second conductive layer 118 is, for example, a metal. The patterned second conductive layer 118 includes a source pattern 118a, a drain pattern 118b, a pad pattern 118c, and a data line pattern 118d. The source pattern 118a is electrically connected to the doping region 104c as a source region via the first via hole 112 as a source of the thin film transistor. The drain pattern 118b is electrically connected to the lower electrode pattern 104b and the doping region 104c as the drain regions via the second through holes 114 to serve as the drain of the thin film transistor. Further, a part of the drain pattern 118b overlaps with the upper electrode pattern 108b, and thus the drain pattern 118b, the upper electrode pattern 108b, and the intermediate dielectric layer 110 located therebetween constitute a storage capacitor structure. The pad pattern 118c is electrically connected to the upper electrode pattern 108b via the third through hole 116. In FIG. 1F, the insulating layer 102, the gate insulating layer 106, and the intermediate dielectric layer 110 are not depicted in order to clarify the drawing.
至此，由上述步驟所形成的結構在本發明中可稱為半成品，其包括基板100以及由閘極(閘極圖案108a)、閘絕緣層106、源極(源極圖案118a以及與其連接的摻雜區104c)與汲極(汲極圖案118b以及與其連接的下電極圖案104b與摻雜區104c)所構成的薄膜電晶體。 So far, the structure formed by the above steps can be referred to as a semi-finished product in the present invention, and includes a substrate 100 and a gate (gate pattern 108a), a gate insulating layer 106, a source (source pattern 118a, and a blend thereof). The impurity region 104c) is a thin film transistor composed of a drain electrode (the drain pattern 118b and the lower electrode pattern 104b and the doped region 104c connected thereto).
然後，請同時參照圖1G與圖2G，形成第一電極120 於基板100上。第一電極120覆蓋並且接觸部分的汲極圖案118b。第一電極120為透明電極，其材料例如為銦錫氧化物。在圖1G中，為了使圖式清楚，因此未將絕緣層102、閘絕緣層106與中間介電層110繪示出。 Then, referring to FIG. 1G and FIG. 2G simultaneously, the first electrode 120 is formed. On the substrate 100. The first electrode 120 covers and contacts a portion of the drain pattern 118b. The first electrode 120 is a transparent electrode, and its material is, for example, indium tin oxide. In FIG. 1G, the insulating layer 102, the gate insulating layer 106, and the intermediate dielectric layer 110 are not depicted in order to clarify the drawing.
特別一提的是，在本實施例中，由於圖案化第二導電層118與第一電極120皆形成於中間介電層110上，因此不用其他絕緣膜將第二導電層118與第一電極120隔開，可以有效地減少畫素結構中其他絕緣膜的使用，以提高畫素結構的光穿透率。 In particular, in this embodiment, since the patterned second conductive layer 118 and the first electrode 120 are both formed on the intermediate dielectric layer 110, the second conductive layer 118 and the first electrode are not used by other insulating films. 120 spacing, can effectively reduce the use of other insulating films in the pixel structure to improve the light transmittance of the pixel structure.
接著，請同時參照圖1H與圖2H，於基板100上形成平坦層122。平坦層122覆蓋上述的薄膜電晶體以及第一電極120。平坦層122的材料例如為感光材料。平坦層122具有對應於第一電極120的凹陷124。對應於凹陷124處之平坦層122厚度例如介於5000 Å至10000 Å之間。凹陷124的形成方法例如是對平坦層122中對應於第一電極120的部分進行曝光與微影製程，例如利用半調光罩製程(Half-tone)。然後，形成貫穿平坦層122的第四貫孔126。第四貫孔126暴露出部分的接墊圖案118c。在圖1H中，為了使圖式清楚，因此未將絕緣層102、閘絕緣層106、中間介電層110與平坦層122繪示出。 Next, please refer to FIG. 1H and FIG. 2H simultaneously to form a flat layer 122 on the substrate 100. The flat layer 122 covers the thin film transistor described above and the first electrode 120. The material of the flat layer 122 is, for example, a photosensitive material. The planarization layer 122 has a recess 124 corresponding to the first electrode 120. The thickness of the planar layer 122 corresponding to the recess 124 is, for example, between 5,000 Å and 10,000 Å. The method of forming the recess 124 is, for example, performing an exposure and lithography process on a portion of the planarization layer 122 corresponding to the first electrode 120, for example, using a half-tone process. Then, a fourth through hole 126 is formed through the flat layer 122. The fourth through hole 126 exposes a portion of the pad pattern 118c. In FIG. 1H, the insulating layer 102, the gate insulating layer 106, the intermediate dielectric layer 110, and the planar layer 122 are not depicted in order to clarify the drawing.
之後，請同時參照圖1I與圖2I，於平坦層122上形成第二電極128。第二電極128為透明電極，其材料例如為銦錫氧化物。部分的第二電極128經由第四貫孔126而電性連接至接墊圖案118c以及上電極圖案108b。此外， 第二電極128還包括相互平行的多個條狀電極圖案，且這些條狀電極圖案位於凹陷124內。在圖1I中，為了使圖式清楚，因此未將絕緣層102、閘絕緣層106、中間介電層110與平坦層122繪示出。 Thereafter, please refer to FIG. 1I and FIG. 2I simultaneously to form the second electrode 128 on the flat layer 122. The second electrode 128 is a transparent electrode, and its material is, for example, indium tin oxide. A portion of the second electrode 128 is electrically connected to the pad pattern 118c and the upper electrode pattern 108b via the fourth through hole 126. In addition, The second electrode 128 further includes a plurality of strip electrode patterns parallel to each other, and the strip electrode patterns are located in the recess 124. In FIG. 1I, the insulating layer 102, the gate insulating layer 106, the intermediate dielectric layer 110, and the planar layer 122 are not depicted in order to clarify the drawing.
特別一提的是，在凹陷124中，第二電極128、第一電極120以及位於二者之間的平坦層122構成儲存電容結構，且由於凹陷124中平坦層122的厚度較薄，因此可以有效地提高儲存電容結構的效能。至於凹陷124之外的平坦層122，因具有較厚的厚度，故可以有效地降低雜散電容。 In particular, in the recess 124, the second electrode 128, the first electrode 120, and the flat layer 122 located therebetween constitute a storage capacitor structure, and since the thickness of the flat layer 122 in the recess 124 is thin, Effectively improve the performance of the storage capacitor structure. As for the flat layer 122 other than the recess 124, since it has a thick thickness, the stray capacitance can be effectively reduced.
此外，在本實施例中，圖案化第二導電層118與第一電極120皆形成於中間介電層110上，其省略了習知技術中於圖案化第二導電層118與第一電極120之間形成平坦層的步驟，且在第一電極120與第二電極128之間形成平坦層來代替習知技術中的保護層，因此與習知技術相比，本實施例有效地簡化了製程步驟而提高了產能，且減少了光罩的使用數目而降低了生產成本。 In addition, in the present embodiment, the patterned second conductive layer 118 and the first electrode 120 are both formed on the intermediate dielectric layer 110, which omits the prior art in patterning the second conductive layer 118 and the first electrode 120. The step of forming a flat layer is formed, and a flat layer is formed between the first electrode 120 and the second electrode 128 instead of the protective layer in the prior art, so the embodiment effectively simplifies the process compared with the prior art. The steps increase the throughput and reduce the number of use of the mask and reduce the production cost.
另外，在本實施例中，由於在形成平坦層122之後不需再藉由化學氣相沈積製程來形成習知技術中的保護層，因此可以有效地避免因化學氣相沈積的高溫製程，容易影響到其下方的平坦層而產生污染(如有機物、碳等)的問題。 In addition, in the present embodiment, since the protective layer in the prior art is formed by the chemical vapor deposition process after the formation of the flat layer 122, the high temperature process due to chemical vapor deposition can be effectively avoided. A problem that affects the flat layer below it and causes pollution (such as organic matter, carbon, etc.).
圖3A至圖3F為依照本發明之第二實施例所繪示的畫 素結構的製作流程的上視示意圖。圖4A至圖4F為依照本發明之第二實施例所繪示的畫素結構的製作流程的剖面示意圖。在本實施例中，為了便於說明，僅繪示出一個畫素區，但本發明並不限於此。 3A to 3F are drawings according to a second embodiment of the present invention. A top view of the production process of the prime structure. 4A-4F are schematic cross-sectional views showing a process of fabricating a pixel structure according to a second embodiment of the present invention. In the present embodiment, for convenience of explanation, only one pixel area is illustrated, but the present invention is not limited thereto.
首先，請同時參照圖3A與圖4A，於基板300上形成圖案化第一導電層302。基板300的材料例如為玻璃、塑膠或其他合適的材料。圖案化第一導電層302的材料例如為金屬。圖案化第一導電層302包括閘極圖案302a以及電極圖案302b。 First, please refer to FIG. 3A and FIG. 4A simultaneously to form a patterned first conductive layer 302 on the substrate 300. The material of the substrate 300 is, for example, glass, plastic or other suitable material. The material of the patterned first conductive layer 302 is, for example, a metal. The patterned first conductive layer 302 includes a gate pattern 302a and an electrode pattern 302b.
然後，請同時參照圖3B與圖4B，於基板300上形成閘絕緣層304，以覆蓋圖案化第一導電層302。閘絕緣層304的材料例如為氧化物、氮化物或其他合適的介電材料。接著，於閘絕緣層304上形成圖案化半導體層306。圖案化半導體層306包括半導體圖案，且此半導體圖案位於閘極圖案302a的上方。在本實施例中，此半導體圖案包括半導體材料層306a以及位於其上的歐姆接觸材料層306b。半導體材料層306a的材料例如為非晶矽。半導體材料層306a作為薄膜電晶體的通道層。歐姆接觸材料層306b的材料例如為n+摻雜非晶矽。在圖3B中，為了使圖式清楚，因此未將閘絕緣層304繪示出。 Then, referring to FIG. 3B and FIG. 4B simultaneously, a gate insulating layer 304 is formed on the substrate 300 to cover the patterned first conductive layer 302. The material of the gate insulating layer 304 is, for example, an oxide, a nitride or other suitable dielectric material. Next, a patterned semiconductor layer 306 is formed over the gate insulating layer 304. The patterned semiconductor layer 306 includes a semiconductor pattern, and the semiconductor pattern is located above the gate pattern 302a. In the present embodiment, the semiconductor pattern includes a layer of semiconductor material 306a and an ohmic contact material layer 306b thereon. The material of the semiconductor material layer 306a is, for example, amorphous germanium. The semiconductor material layer 306a serves as a channel layer of the thin film transistor. The material of the ohmic contact material layer 306b is, for example, n + doped amorphous germanium. In FIG. 3B, the gate insulating layer 304 is not shown in order to make the drawing clear.
接著，請同時參照圖3C與圖4C，於閘絕緣層304上形成第二導電層(未繪示)。第二導電層的材料例如為金屬。接著，將第二導電層以及位於其下方的歐姆接觸材料層306b圖案化，以形成圖案化第二導電層308以及歐姆接 觸層306c。圖案化第二導電層308包括源極圖案308a、汲極圖案308b以及資料線圖案308c。源極圖案308a與汲極圖案308b分別位於半導體圖案(圖案化半導體層306)的兩側，以分別作為薄膜電晶體的源極以及汲極，且汲極圖案308b的一部分與電極圖案302b重疊。因此，汲極圖案308b、電極圖案302b以及位於二者之間的閘絕緣層304構成儲存電容結構。在圖3C中，為了使圖式清楚，因此未將閘絕緣層304繪示出。 Next, please refer to FIG. 3C and FIG. 4C simultaneously to form a second conductive layer (not shown) on the gate insulating layer 304. The material of the second conductive layer is, for example, a metal. Next, the second conductive layer and the ohmic contact material layer 306b underneath are patterned to form a patterned second conductive layer 308 and an ohmic junction Touch layer 306c. The patterned second conductive layer 308 includes a source pattern 308a, a drain pattern 308b, and a data line pattern 308c. The source pattern 308a and the drain pattern 308b are respectively located on both sides of the semiconductor pattern (patterned semiconductor layer 306) to serve as a source and a drain of the thin film transistor, respectively, and a portion of the drain pattern 308b overlaps the electrode pattern 302b. Therefore, the drain pattern 308b, the electrode pattern 302b, and the gate insulating layer 304 located therebetween constitute a storage capacitor structure. In FIG. 3C, the gate insulating layer 304 is not depicted in order to make the drawing clear.
至此，由上述步驟所形成的結構在本發明中可稱為半成品，其包括基板300以及由閘極(閘極圖案302a)、閘絕緣層304、通道層(半導體材料層306a)、歐姆接觸層306c、源極(源極圖案308a)與汲極(汲極圖案308b)所構成的薄膜電晶體。 Heretofore, the structure formed by the above steps may be referred to as a semi-finished product in the present invention, and includes a substrate 300 and a gate (gate pattern 302a), a gate insulating layer 304, a channel layer (semiconductor material layer 306a), and an ohmic contact layer. 316c, a thin film transistor composed of a source (source pattern 308a) and a drain (drain pattern 308b).
然後，請同時參照圖3D與圖4D，形成第一電極310於基板300上。第一電極310覆蓋並且接觸部分的汲極圖案308b。第一電極310為透明電極，其材料例如為銦錫氧化物。在圖3D中，為了使圖式清楚，因此未將閘絕緣層304繪示出。 Then, referring to FIG. 3D and FIG. 4D simultaneously, the first electrode 310 is formed on the substrate 300. The first electrode 310 covers and contacts a portion of the drain pattern 308b. The first electrode 310 is a transparent electrode, and its material is, for example, indium tin oxide. In FIG. 3D, the gate insulating layer 304 is not depicted in order to make the drawing clear.
接著，請同時參照圖3E與圖4E，於基板300上形成平坦層312。平坦層312覆蓋上述的薄膜電晶體以及第一電極310。平坦層312的材料例如為感光材料。平坦層312具有對應於第一電極310的凹陷314。對應於凹陷314處之平坦層312厚度例如介於5000 Å至10000 Å之間。凹陷314的形成方法例如是對平坦層312中對應於第一電極310 的部分進行曝光與微影製程，例如利用半調光罩製程。然後，形成貫穿平坦層312以及閘絕緣層304的貫孔316。貫孔316暴露出部分的電極圖案302b。在圖3E中，為了使圖式清楚，因此未將閘絕緣層304與平坦層312繪示出。 Next, please refer to FIG. 3E and FIG. 4E simultaneously to form a flat layer 312 on the substrate 300. The flat layer 312 covers the thin film transistor described above and the first electrode 310. The material of the flat layer 312 is, for example, a photosensitive material. The planarization layer 312 has a recess 314 corresponding to the first electrode 310. The thickness of the planar layer 312 corresponding to the recess 314 is, for example, between 5,000 Å and 10,000 Å. The forming method of the recess 314 is, for example, corresponding to the first electrode 310 in the flat layer 312. Part of the exposure and lithography process, such as the use of a half dimming process. Then, a through hole 316 is formed through the flat layer 312 and the gate insulating layer 304. The through hole 316 exposes a portion of the electrode pattern 302b. In FIG. 3E, the gate insulating layer 304 and the flat layer 312 are not shown in order to make the drawing clear.
之後，請同時參照圖3F與圖4F，於平坦層312上形成第二電極318。第二電極318為透明電極，其材料例如為銦錫氧化物。部分的第二電極318經由貫孔316而電性連接至電極圖案302b。此外，第二電極318還包括相互平行的多個條狀電極圖案，且這些條狀電極圖案位於凹陷314內。在圖3F中，為了使圖式清楚，因此未將閘絕緣層304與平坦層312繪示出。 Thereafter, please refer to FIG. 3F and FIG. 4F simultaneously to form the second electrode 318 on the flat layer 312. The second electrode 318 is a transparent electrode, and its material is, for example, indium tin oxide. A portion of the second electrode 318 is electrically connected to the electrode pattern 302b via the through hole 316. In addition, the second electrode 318 further includes a plurality of strip electrode patterns parallel to each other, and the strip electrode patterns are located in the recess 314. In FIG. 3F, the gate insulating layer 304 and the flat layer 312 are not shown in order to make the drawing clear.
特別一提的是，在凹陷314中，第二電極318、第一電極310以及位於二者之間的平坦層312構成儲存電容結構，且由於凹陷314中的平坦層312的厚度較薄，因此可以有效地提高儲存電容結構的效能。至於凹陷314之外的平坦層312，因具有較厚的厚度，故可以有效地降低雜散電容。 In particular, in the recess 314, the second electrode 318, the first electrode 310, and the flat layer 312 located therebetween constitute a storage capacitor structure, and since the thickness of the flat layer 312 in the recess 314 is thin, It can effectively improve the performance of the storage capacitor structure. As for the flat layer 312 other than the recess 314, since it has a thick thickness, the stray capacitance can be effectively reduced.
此外，在本實施例中，圖案化第二導電層308與第一電極310皆形成於閘絕緣層304上，其省略了習知技術中於圖案化第二導電層308與第一電極310之間形成平坦層的步驟，且在第一電極310與第二電極318之間形成平坦層312來代替習知技術中的保護層，因此與習知技術相比，本實施例有效地簡化了製程步驟而提高了產能，且減少了光罩的使用數目而降低了生產成本。 In addition, in the present embodiment, the patterned second conductive layer 308 and the first electrode 310 are both formed on the gate insulating layer 304, which omits the prior art in patterning the second conductive layer 308 and the first electrode 310. The step of forming a flat layer, and forming a flat layer 312 between the first electrode 310 and the second electrode 318 instead of the protective layer in the prior art, thus the present embodiment effectively simplifies the process compared to the prior art. The steps increase the throughput and reduce the number of use of the mask and reduce the production cost.
另外，在本實施例中，由於在形成平坦層312之後不需再藉由化學氣相沈積製程來形成習知技術中的保護層，因此可以有效地避免因化學氣相沈積的高溫製程，容易影響到其下方的平坦層而產生污染(如有機物、碳等)的問題。 In addition, in the present embodiment, since the protective layer in the prior art is formed by the chemical vapor deposition process after the formation of the planarization layer 312, the high temperature process by chemical vapor deposition can be effectively avoided. A problem that affects the flat layer below it and causes pollution (such as organic matter, carbon, etc.).
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100、300‧‧‧基板 100, 300‧‧‧ substrate
100a‧‧‧畫素區 100a‧‧‧ pixel area
102‧‧‧絕緣層 102‧‧‧Insulation
104‧‧‧圖案化半導體材料層 104‧‧‧ patterned semiconductor material layer
104a、104c‧‧‧摻雜區 104a, 104c‧‧‧ doped area
104b‧‧‧下電極圖案 104b‧‧‧lower electrode pattern
106、304‧‧‧閘絕緣層 106, 304‧‧‧ brake insulation
108、302‧‧‧圖案化第一導電層 108, 302‧‧‧ patterned first conductive layer
108a、302a‧‧‧閘極圖案 108a, 302a‧‧‧ gate pattern
108b‧‧‧上電極圖案 108b‧‧‧Upper electrode pattern
110‧‧‧中間介電層 110‧‧‧Intermediate dielectric layer
112‧‧‧第一貫孔 112‧‧‧ first through hole
114‧‧‧第二貫孔 114‧‧‧Second through hole
116‧‧‧第三貫孔 116‧‧‧Through hole
118、308‧‧‧圖案化第二導電層 118, 308‧‧‧ patterned second conductive layer
118a、308a‧‧‧源極圖案 118a, 308a‧‧‧ source pattern
118b、308b‧‧‧汲極圖案 118b, 308b‧‧‧ bungee pattern
118c‧‧‧接墊圖案 118c‧‧‧ pads pattern
118d、308c‧‧‧資料線圖案 118d, 308c‧‧‧ data line pattern
120、310‧‧‧第一電極 120, 310‧‧‧ first electrode
122、312‧‧‧平坦層 122, 312‧‧‧ flat layer
124、314‧‧‧凹陷 124, 314‧‧‧ dent
126‧‧‧第四貫孔 126‧‧‧4th through hole
128、318‧‧‧第二電極 128, 318‧‧‧ second electrode
302b‧‧‧電極圖案 302b‧‧‧electrode pattern
306‧‧‧圖案化半導體層 306‧‧‧ patterned semiconductor layer
306a‧‧‧半導體材料層： 306a‧‧‧Semiconductor material layer:
306b‧‧‧歐姆接觸材料層 306b‧‧‧ Ohmic contact material layer
306c‧‧‧歐姆接觸層 306c‧‧‧ Ohmic contact layer
316‧‧‧貫孔 316‧‧‧through holes
圖1A至圖1I為依照本發明之第一實施例所繪示的畫素結構的製作流程的上視示意圖。 1A to FIG. 1I are schematic top views of a process of fabricating a pixel structure according to a first embodiment of the present invention.
圖2A至圖2I為依照本發明之第一實施例所繪示的畫素結構的製作流程的剖面示意圖。 2A to 2I are schematic cross-sectional views showing a process of fabricating a pixel structure according to a first embodiment of the present invention.
圖3A至圖3F為依照本發明之第二實施例所繪示的畫素結構的製作流程的上視示意圖。 3A-3F are top schematic views showing a process of fabricating a pixel structure according to a second embodiment of the present invention.
圖4A至圖4F為依照本發明之第二實施例所繪示的畫素結構的製作流程的剖面示意圖。 4A-4F are schematic cross-sectional views showing a process of fabricating a pixel structure according to a second embodiment of the present invention.
100‧‧‧基板 100‧‧‧Substrate
102‧‧‧絕緣層 102‧‧‧Insulation
104a、104c‧‧‧摻雜區 104a, 104c‧‧‧ doped area
104b‧‧‧下電極圖案 104b‧‧‧lower electrode pattern
106‧‧‧閘絕緣層 106‧‧‧Brake insulation
108a‧‧‧閘極圖案 108a‧‧‧ gate pattern
108b‧‧‧上電極圖案 108b‧‧‧Upper electrode pattern
110‧‧‧中間介電層 110‧‧‧Intermediate dielectric layer
112‧‧‧第一貫孔 112‧‧‧ first through hole
114‧‧‧第二貫孔 114‧‧‧Second through hole
116‧‧‧第三貫孔 116‧‧‧Through hole
118‧‧‧圖案化第二導電層 118‧‧‧ patterned second conductive layer
118a‧‧‧源極圖案 118a‧‧‧Source pattern
118b‧‧‧汲極圖案 118b‧‧‧汲polar pattern
118c‧‧‧接墊圖案 118c‧‧‧ pads pattern
118d‧‧‧資料線圖案 118d‧‧‧ data line pattern
120‧‧‧第一電極 120‧‧‧first electrode
Claims (13)
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| US6281953B1 (en) * | 1998-08-24 | 2001-08-28 | Hyundai Electronics Industries Co., Ltd. | Liquid crystal display having high aperture ratio and high transmittance and method of manufacturing the same |
| CN101614915A (en) * | 2008-06-25 | 2009-12-30 | 乐金显示有限公司 | The liquid crystal indicator of fringe field switching mode and array base palte thereof |
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| TW460731B (en) * | 1999-09-03 | 2001-10-21 | Ind Tech Res Inst | Electrode structure and production method of wide viewing angle LCD |
| TWI414864B (en) * | 2007-02-05 | 2013-11-11 | Hydis Tech Co Ltd | Fringe field switching mode lcd |
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| CN101614915A (en) * | 2008-06-25 | 2009-12-30 | 乐金显示有限公司 | The liquid crystal indicator of fringe field switching mode and array base palte thereof |
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