TWI400676B - Display, and gate pulse generation method and circuit for display - Google Patents

Display, and gate pulse generation method and circuit for display Download PDF

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TWI400676B
TWI400676B TW97141485A TW97141485A TWI400676B TW I400676 B TWI400676 B TW I400676B TW 97141485 A TW97141485 A TW 97141485A TW 97141485 A TW97141485 A TW 97141485A TW I400676 B TWI400676 B TW I400676B
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signal
display
gate
cpv
delay
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TW201017612A (en
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Hsuan Lin Pan
Po Sheng Shi
Chien Yung Cheng
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Hannstar Display Corp
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Description

顯示器及用於顯示器的閘極波型產生方法與電路Display and gate wave generation method and circuit for display

本案係指一種閘極波型產生方法及其電路,特別是一種用於液晶顯示器的閘極波型產生方法及其電路。The present invention relates to a gate wave type generating method and a circuit thereof, and particularly to a gate wave type generating method and a circuit thereof for a liquid crystal display.

近年來,液晶顯示器的技術突飛猛進,所呈現的畫質也愈來愈佳,以目前垂直配向(Vertical Alignment)的HVA技術來說,請參照圖1,其為本發明之發明人的美國專利申請案公開號20050083279中所顯示的HVA技術的畫素結構,其中Gn ,Gn-1 ,Gn-2 分別為第n、第n-1及第n-2條閘極線(Gate Lines),分別用來傳輸閘極第n、第n-1及第n-2訊號,而Dm ,Dm-1 ,Dm-2 則分別為第m、第m-1及第m-2條資料線(Data Lines),分別用來傳輸資料第m、第m-1及第m-2訊號。每個畫素當中會有兩個薄膜電晶體(T1 及T2 ),分別連接到不同的電極,而電極之間會有相互連接的電容(C1 ,C2 及C3 )。依據此種畫素架構,為了能夠完整地顯示畫面,在面板的邊緣部位將會需要額外的閘極線(Gate Line,data-in or data-end edge),來傳輸閘極第零訊號,以提供完整的訊號而使面板可正常操作。In recent years, the technology of liquid crystal displays has advanced by leaps and bounds, and the quality of the presented images has become better and better. For the current vertical alignment HVA technology, please refer to FIG. 1, which is a US patent application of the inventor of the present invention. The pixel structure of the HVA technique shown in the publication No. 20050083279, in which G n , G n-1 , and G n-2 are the nth, n-1th, and n- 2th gate lines, respectively. , respectively, for transmitting the nth, n-1th, and n-2th gates, and D m , D m-1 , and D m-2 are m, m-1, and m-2, respectively. Data Lines are used to transmit m, m-1 and m-2 signals respectively. There are two thin-film transistors (T 1 and T 2 ) in each pixel, which are connected to different electrodes, and there are interconnected capacitors (C 1 , C 2 and C 3 ) between the electrodes. According to the pixel structure, in order to display the picture completely, an additional gate line (Gate Line, data-in or data-end edge) is needed at the edge of the panel to transmit the gate zero signal. Provide a complete signal for the panel to operate properly.

圖2為習知的液晶顯示器的HVA驅動方式的示意圖。請參照圖2,其中CPV(Vertical Shift Clock)訊號為垂直時脈訊號,STV(Vertical Start Pulse)訊號為垂直起始脈衝訊號。以28吋HVA技術的液晶顯示器為例,當解析度為1920×1200,表示需要1201條 Gate Lines(G0~G1200),來傳送閘極第零訊號(G0訊號)、閘極第1訊號(G1訊號)、閘極第2訊號(G2訊號)…閘極第1200訊號(G1200訊號),以符合HVA驅動方式,同時正確地顯示畫面。2 is a schematic diagram of a conventional HVA driving method of a liquid crystal display. Referring to FIG. 2, the vertical PV signal of the CPV (Vertical Shift Clock) signal is a vertical start pulse signal. Taking a liquid crystal display with 28 吋 HVA technology as an example, when the resolution is 1920×1200, it means that 1201 pieces are needed. Gate Lines (G0~G1200), to transmit the gate zero signal (G0 signal), the gate first signal (G1 signal), the gate second signal (G2 signal), the gate 1200 signal (G1200 signal), In order to conform to the HVA drive mode, the screen is displayed correctly.

但是現行的閘極驅動積體電路(Gate Driver IC)多為2階驅動且是300 pins或400 pins的架構,若使用在搭載HVA技術的面板上,將使得IC的使用顆數增加,進而造成成本的增加。圖3A為習知HVA技術300 pin雙邊驅動的閘極驅動積體電路模組的示意圖;圖3B則為習知HVA技術400 pin雙邊驅動的閘極驅動積體電路模組的示意圖。由圖3A及3B中可以發現:模組3a及3b皆需多2顆IC(僅用在處理G1200訊號),因此造成成本上增加,並不符合經濟效益。However, the current gate driver integrated circuit (Gate Driver IC) is mostly a 2nd-order drive and is 300 pins or 400 pins. If it is used on a panel equipped with HVA technology, the number of ICs used will increase, resulting in The increase in cost. FIG. 3A is a schematic diagram of a gate drive integrated circuit module of a 300-pin bilateral drive of a conventional HVA technology; FIG. 3B is a schematic diagram of a gate drive integrated circuit module of a 400-pin bilateral drive of a conventional HVA technology. It can be found from FIGS. 3A and 3B that both modules 3a and 3b require two more ICs (used only to process the G1200 signal), which results in an increase in cost and is not economical.

綜合上述可知,習知的顯示器的HVA驅動方式及電路,亟待進一步改善。本案發明團隊經深入研究分析,終於開發出一套革新且有效的驅動方式及電路,並經多次的實驗與改良,能以更經濟且有效的技術方案,根本解決上述的問題,造福一般大眾使用者。In summary, the HVA driving method and circuit of the conventional display need to be further improved. After in-depth research and analysis, the invention team of the case finally developed an innovative and effective driving method and circuit, and after many experiments and improvements, it can solve the above problems with a more economical and effective technical solution for the benefit of the general public. user.

本案之目的為提供一種用於顯示器的閘極波型產生方法,其中該顯示器具有一垂直起始脈衝(STV)訊號,該方法包括:利用該STV訊號來產生一第一延遲訊號,其中該第一延遲訊號較該STV訊號延遲一第一時間差;利用該第一延遲訊號來產生一第二延遲訊號,其中該第二延遲訊號較該第一延遲訊號延遲一第二時間 差;以及利用該第一延遲訊號來產生一閘極第零訊號,其中該閘極第零訊號與該第一延遲訊號同步。The purpose of the present invention is to provide a gate wave type generating method for a display, wherein the display has a vertical start pulse (STV) signal, the method comprising: using the STV signal to generate a first delay signal, wherein the A delay signal is delayed by a first time difference from the STV signal; the first delay signal is used to generate a second delay signal, wherein the second delay signal is delayed by a second time from the first delay signal And using the first delay signal to generate a gate zero signal, wherein the gate zero signal is synchronized with the first delay signal.

根據上述構想,其中該顯示器更具有一垂直時脈(CPV)訊號,其具有一週期,而該第二時間差為該CPV訊號的該週期的一半。According to the above concept, the display further has a vertical clock (CPV) signal having a period, and the second time difference is half of the period of the CPV signal.

根據上述構想,其中該顯示器更包括一第一D型正反器,其接收該STV訊號及該CPV訊號,並輸出該第一延遲訊號。According to the above concept, the display further includes a first D-type flip-flop that receives the STV signal and the CPV signal and outputs the first delay signal.

根據上述構想,其中該顯示器更包括一反向器,其接收該CPV訊號,並將該CPV訊號作相位轉換,以輸出一反相訊號。According to the above concept, the display further includes an inverter that receives the CPV signal and phase-converts the CPV signal to output an inverted signal.

根據上述構想,其中該顯示器更包括一第二D型正反器,其接收該第一延遲訊號及該反相訊號,並以該反相訊號為時脈,以輸出該第二延遲訊號。According to the above concept, the display further includes a second D-type flip-flop that receives the first delayed signal and the inverted signal, and uses the inverted signal as a clock to output the second delayed signal.

根據上述構想,其中該顯示器更包括一位準移位元件,其接收該第一延遲訊號、一高參考位準及一低參考位準,以輸出該閘極第零訊號,並基於該高參考位準及該低參考位準,使得該第一延遲訊號的電壓值與該閘極第零訊號的電壓值不同。According to the above concept, the display further includes a quasi-shifting component that receives the first delay signal, a high reference level, and a low reference level to output the gate zero signal, and based on the high reference The level and the low reference level are such that the voltage value of the first delay signal is different from the voltage value of the gate zero signal.

本案之另一目的為提供一種顯示器,其具有一垂直起始脈衝(STV)訊號及一垂直時脈(CPV)訊號,該顯示器包括一閘極波型產生電路,其包括:一第一D型正反器,接收該STV訊號及該CPV訊號,並輸出一第一延遲訊號;一反向器,接收該CPV訊號,並輸出一反相訊號;一第二D型正反器,分別電連接至該第一D型正反器及該反向器,其中該第二D型正反器接收該第一延遲訊號及該反相訊號,並輸出一第二延遲訊號;以及一位準移位元件,電連接至該第一D型正反器,接收該第一延遲訊號,並輸出一閘 極第零訊號。Another object of the present invention is to provide a display having a vertical start pulse (STV) signal and a vertical clock (CPV) signal, the display including a gate wave type generating circuit including: a first D type The flip-flop receives the STV signal and the CPV signal and outputs a first delay signal; an inverter receives the CPV signal and outputs an inverted signal; and a second D-type flip-flop is electrically connected And the first D-type flip-flop and the inverter, wherein the second D-type flip-flop receives the first delay signal and the inverted signal, and outputs a second delay signal; and a quasi-shift The component is electrically connected to the first D-type flip-flop, receives the first delay signal, and outputs a gate The very zero signal.

根據上述構想,其中該顯示器為一液晶顯示器、一電漿顯示器、一發光二極體顯示器、一有機發光二極體顯示器或一奈米碳管顯示器。According to the above concept, the display is a liquid crystal display, a plasma display, a light emitting diode display, an organic light emitting diode display or a carbon nanotube display.

本案之又一目的為提供一種電路,用於一顯示器,該顯示器具有一垂直起始脈衝(STV)訊號及一垂直時脈(CPV)訊號,該電路包括:一第一D型正反器,接收該STV訊號及該CPV訊號,並輸出一第一延遲訊號;一反向器,接收該CPV訊號,並輸出一反相訊號;一第二D型正反器,分別電連接至該第一D型正反器及該反向器,其中該第二D型正反器接收該第一延遲訊號及該反相訊號,並輸出一第二延遲訊號;以及一位準移位元件,電連接至該第一D型正反器,接收該第一延遲訊號,並輸出一閘極第零訊號。Another object of the present invention is to provide a circuit for a display having a vertical start pulse (STV) signal and a vertical clock (CPV) signal, the circuit comprising: a first D-type flip-flop, Receiving the STV signal and the CPV signal, and outputting a first delay signal; an inverter receiving the CPV signal and outputting an inverted signal; and a second D-type flip-flop electrically connected to the first a D-type flip-flop and the inverter, wherein the second D-type flip-flop receives the first delay signal and the inverted signal, and outputs a second delay signal; and a quasi-shift component, electrically connected And the first D-type flip-flop receives the first delay signal and outputs a gate zero signal.

根據上述構想,其中,該第一D型正反器以該CPV訊號為時脈,利用該STV訊號,以輸出該第一延遲訊號;該反向器對該CPV訊號作相位轉換,以輸出該反相訊號;以及該第二D型正反器以該反相訊號為時脈,利用該第一延遲訊號,以輸出該第二延遲訊號。According to the above concept, the first D-type flip-flop uses the CPV signal as a clock, and uses the STV signal to output the first delay signal; the inverter performs phase conversion on the CPV signal to output the And the second D-type flip-flop uses the first delay signal as a clock to output the second delay signal.

根據上述構想,其中該顯示器更包括N條閘極線及一閘極驅動電路,其中N≧3,該閘極驅動電路接收該第二延遲訊號,以產生一閘極第一訊號、一閘極第二訊號…一閘極第N訊號。According to the above concept, the display further includes N gate lines and a gate driving circuit, wherein N ≧ 3, the gate driving circuit receives the second delay signal to generate a gate first signal and a gate The second signal... a gated Nth signal.

根據上述構想,其中該第一延遲訊號較該STV訊號延遲一第一時間差,而該位準移位元件更接收一高參考位準及一低參考位 準,且基於該高參考位準及該低參考位準,使得該第一延遲訊號的電壓值與該閘極第零訊號的電壓值不同。According to the above concept, the first delay signal is delayed by a first time difference from the STV signal, and the level shifting element further receives a high reference level and a low reference bit. And based on the high reference level and the low reference level, the voltage value of the first delay signal is different from the voltage value of the gate zero signal.

根據上述構想,其中該第二延遲訊號較該第一延遲訊號延遲一第二時間差,該CPV訊號具有一週期,而該第二時間差為該CPV訊號的該週期的一半。According to the above concept, the second delay signal is delayed by a second time difference from the first delay signal, the CPV signal has a period, and the second time difference is half of the period of the CPV signal.

根據上述構想,其中該顯示器為具有一薄膜電晶體結構的顯示器。According to the above concept, wherein the display is a display having a thin film transistor structure.

本發明將藉由下述之較佳實施例並配合圖示,作進一步之詳細說明。The invention will be further described in detail by the following preferred embodiments and illustrated by the accompanying drawings.

[第一實施例][First Embodiment]

圖4為本發明第一實施例的液晶顯示器的HVA驅動方式的示意圖。請參照圖4,其中CPV(Vertical Shift Clock)訊號為垂直時脈訊號,其週期為TCPV ,而STV(Vertical Start Pulse)訊號為垂直起始脈衝訊號。在本實施例的閘極波型產生方法中,首先利用STV訊號延遲第一時間差TD1,以產生第一延遲訊號(STV-1訊號)。然後利用此STV-1訊號來產生閘極第零訊號(G0訊號),並使得STV-1訊號與G0訊號同步,如圖4所示。接著利用此STV-1訊號延遲第二時間差TD2,以產生第二延遲訊號(STV-2訊號)。4 is a schematic view showing an HVA driving method of a liquid crystal display according to a first embodiment of the present invention. Referring to FIG. 4, the CPV (Vertical Shift Clock) signal is a vertical clock signal, and the period is T CPV , and the STV (Vertical Start Pulse) signal is a vertical start pulse signal. In the gate mode generating method of the present embodiment, the first time difference TD1 is first delayed by the STV signal to generate a first delay signal (STV-1 signal). Then use the STV-1 signal to generate the gate zero signal (G0 signal), and synchronize the STV-1 signal with the G0 signal, as shown in FIG. Then, the second time difference TD2 is delayed by the STV-1 signal to generate a second delay signal (STV-2 signal).

在本實施例中,第二時間差TD2的時間長短可設為CPV訊號週期TCPV 的一半。本實施例中的顯示器為液晶顯示器,當然也可以是其它具有薄膜電晶體結構的顯示器,例如是:電漿顯示器、 發光二極體顯示器、有機發光二極體顯示器或奈米碳管顯示器等。In this embodiment, the length of time of the second time difference TD2 can be set to be half of the CPV signal period T CPV . The display in this embodiment is a liquid crystal display, and of course, other displays having a thin film transistor structure, such as a plasma display, a light emitting diode display, an organic light emitting diode display, or a carbon nanotube display.

利用本實施例的閘極波型產生方法,可產生G0訊號,所以閘極驅動積體電路(Gate Driver IC)不須處理G0訊號,因此可以省下IC使用顆數。圖5A為利用本發明第一實施例方法的300 pin雙邊驅動的閘極驅動積體電路模組的示意圖,圖5B則為利用本發明第一實施例方法的400 pin雙邊驅動的閘極驅動積體電路模組的示意圖,其中的液晶顯示器的解析度與圖3A及3B的液晶顯示器的解析度同樣為1920×1200,以與習知技術作比較。請同時參照圖3A、3B、5A及5B,由圖3A、3B、5A及5B中可以發現:利用本實施例方法之模組5a及5b皆較使用習知方法之模組3a及3b節省了2顆IC,因此能夠顯著地降低成本,並使得IC的利用更符合經濟效益,解決習知技術所存在的問題。With the gate wave type generating method of the embodiment, the G0 signal can be generated, so the gate driver integrated circuit (Gate Driver IC) does not need to process the G0 signal, thereby saving the number of ICs used. 5A is a schematic diagram of a 300 pin bilaterally driven gate drive integrated circuit module using the method of the first embodiment of the present invention, and FIG. 5B is a 400 pin bilaterally driven gate drive product using the method of the first embodiment of the present invention. A schematic diagram of a bulk circuit module in which the resolution of the liquid crystal display is the same as that of the liquid crystal display of FIGS. 3A and 3B is 1920×1200, which is compared with the prior art. Referring to FIGS. 3A, 3B, 5A and 5B, it can be seen from FIGS. 3A, 3B, 5A and 5B that the modules 5a and 5b using the method of the present embodiment are saved compared to the modules 3a and 3b using the conventional method. With two ICs, it can significantly reduce costs and make the use of ICs more economical and solve the problems of conventional technologies.

〔第二實施例〕[Second embodiment]

圖6為本發明第二實施例的液晶顯示器的HVA驅動方式的示意圖。請參照圖6,本實施例仍採用第一實施例的方法,並進一步選擇使用一D型正反器(Flip-Flop)(未示於圖6中),用來接收STV訊號及CPV訊號,並以CPV訊號為時脈,以輸出STV-1訊號。此STV-1訊號較STV訊號延遲了第一時間差TD1。此STV-1訊號可傳送至位準移位(Level Shift)元件,並由位準移位元件進行電壓值的調整,以輸出脈衝電壓高低值分別為Vgh及Vgl的閘極第零訊號(如圖6所示)至面板電路,而Gate Driver IC(未示於圖中)不須處理此G0訊號,因此可以省下IC使用顆數,達成降低成本的功效。FIG. 6 is a schematic diagram of an HVA driving method of a liquid crystal display according to a second embodiment of the present invention. Referring to FIG. 6, the method of the first embodiment is still used in this embodiment, and a D-type flip-flop (not shown in FIG. 6) is further selected for receiving the STV signal and the CPV signal. The CPV signal is used as the clock to output the STV-1 signal. This STV-1 signal is delayed by the first time difference TD1 from the STV signal. The STV-1 signal can be transmitted to a level shifting (Level Shift) component, and the voltage value is adjusted by the level shifting component to output a gate zero signal with a pulse voltage of Vgh and Vgl, respectively. Figure 6 shows the circuit to the panel circuit, and the Gate Driver IC (not shown) does not need to process this G0 signal, so it can save the number of ICs and achieve cost reduction.

另外,選擇使用反向器(Inverter)(未示於圖6中),用來接收CPV訊號,並將CPV訊號作相位轉換,以輸出反相訊號(CPV-R訊號),如圖6所示。然後,可選擇另一D型正反器(未示於圖6中),用來接收STV-1訊號及CPV-R訊號,並以CPV-R訊號為時脈,輸出STV-2訊號至Gate Driver IC,其中STV-2訊號較STV-1訊號延遲了第二時間差TD2,而TD2的時間長短可設為CPV訊號週期TCPV 的一半。Gate Driver IC則對接收到的STV-2訊號進行處理,依序產生閘極第1訊號、閘極第2訊號…閘極第1200訊號。當然,當顯示器的解析度不同時,閘極訊號數便會不同,例如當解析度為全高畫質(Full HD),即1920×1080,則便需要有閘極第1至第1080訊號。In addition, an inverter (not shown in FIG. 6) is selected for receiving the CPV signal, and the CPV signal is phase-converted to output an inverted signal (CPV-R signal), as shown in FIG. . Then, another D-type flip-flop (not shown in FIG. 6) can be selected to receive the STV-1 signal and the CPV-R signal, and the CPV-R signal is used as the clock to output the STV-2 signal to the Gate. Driver IC, in which the STV-2 signal is delayed by the second time difference TD2 compared to the STV-1 signal, and the length of the TD2 can be set to half of the CPV signal period T CPV . The Gate Driver IC processes the received STV-2 signal, and sequentially generates the gate first signal, the gate second signal, and the gate 1200 signal. Of course, when the resolution of the display is different, the number of gate signals will be different. For example, when the resolution is Full HD, that is, 1920×1080, the first to the 1080th signals of the gate are required.

〔第三實施例〕[Third embodiment]

圖7為本發明第三實施例之閘極波型產生電路的示意圖。請參照圖7,本實施例的電路70可用於第一及第二實施例中的閘極波型產生方法。電路70包括第一D型正反器10、第二D型正反器20、反向器30及位準移位元件40。其中,第二D型正反器20分別與第一D型正反器10與反向器30電性連接;位準移位元件40則與第一D型正反器10電性連接。Fig. 7 is a schematic view showing a gate mode generating circuit of a third embodiment of the present invention. Referring to Fig. 7, the circuit 70 of the present embodiment can be applied to the gate mode generating method in the first and second embodiments. The circuit 70 includes a first D-type flip-flop 10, a second D-type flip-flop 20, an inverter 30, and a level shifting element 40. The second D-type flip-flops 20 are electrically connected to the first D-type flip-flops 10 and the inverters 30 respectively; the level shifting elements 40 are electrically connected to the first D-type flip-flops 10.

請同時參照圖6及圖7,本實施例中的第一D型正反器10接收STV訊號及CPV訊號,並以CPV訊號為時脈,輸出STV-1訊號至位準移位元件40,其中STV-1訊號較STV訊號延遲了第一時間差TD1。位準移位元件40則根據輸入的電壓高低值Vgh及Vgl,對接收到的STV-1訊號的脈衝電壓值進行調整,以輸出具有脈衝 電壓高低值為Vgh及Vgl的G0訊號,所以使得STV-1訊號與G0訊號的電壓值不同,並且G0訊號與STV-1訊號同步。G0訊號可傳送至面板電路,而Gate Driver IC(未示於圖中)不須處理此G0訊號,因此可以省下IC使用顆數,達成降低成本的功效。Referring to FIG. 6 and FIG. 7 simultaneously, the first D-type flip-flop 10 in the embodiment receives the STV signal and the CPV signal, and outputs the STV-1 signal to the level shifting component 40 by using the CPV signal as a clock. The STV-1 signal is delayed by the first time difference TD1 from the STV signal. The level shifting element 40 adjusts the pulse voltage value of the received STV-1 signal according to the input voltage high and low values Vgh and Vgl to output the pulse. The voltage value is the G0 signal of Vgh and Vgl, so the voltage value of the STV-1 signal and the G0 signal are different, and the G0 signal is synchronized with the STV-1 signal. The G0 signal can be transmitted to the panel circuit, and the Gate Driver IC (not shown) does not need to process the G0 signal, so the number of ICs can be saved, and the cost reduction effect can be achieved.

請繼續參照圖6及圖7,反向器30接收CPV訊號,並對CPV訊號作相位轉換,以輸出CPV反相訊號(CPV-R訊號)至第二D型正反器20。第二D型正反器20接收STV-1訊號及CPV-R訊號,並輸出STV-2訊號至Gate Driver IC,其中STV-2訊號較STV-1訊號延遲了第二時間差TD2,此TD2的時間長短可設為CPV訊號週期TCPV 的一半。Gate Driver IC則對接收到的STV-2訊號進行處理,依序產生閘極第1訊號、閘極第2訊號…閘極第1200訊號等顯示器所需的閘極波型訊號,此處假設顯示器的解析度為1920×1200。Referring to FIG. 6 and FIG. 7 , the inverter 30 receives the CPV signal and performs phase conversion on the CPV signal to output a CPV inverted signal (CPV-R signal) to the second D-type flip-flop 20 . The second D-type flip-flop 20 receives the STV-1 signal and the CPV-R signal, and outputs the STV-2 signal to the Gate Driver IC, wherein the STV-2 signal is delayed by the second time difference TD2 from the STV-1 signal, the TD2 The length of time can be set to half of the CPV signal period T CPV . The Gate Driver IC processes the received STV-2 signal, and sequentially generates the gate wave type signal required for the display such as the gate first signal, the gate second signal, the gate 1200 signal, etc. The resolution is 1920 × 1200.

綜上所述,本案提供一種閘極波型產生電路及其方法,以新穎的技術思維,來產生顯示器所需的所有閘極波型訊號,並同時能夠減少閘極驅動IC的使用顆數,以達到節省資源及降低成本的功效。對廣大的顯示器使用者大眾來說,乃一大福音,並對環境保護做出貢獻。In summary, the present invention provides a gate wave type generating circuit and a method thereof, which generate novel gate wave signals required for a display by novel technical thinking, and at the same time, can reduce the number of gate driving ICs used. In order to save resources and reduce costs. For the majority of display users, it is a great boon and contributes to environmental protection.

本案得由熟悉本技藝之人士任施匠思而為諸般修飾,然皆不脫如附申請專利範圍所欲保護者。This case has been modified by people who are familiar with the art, but it is not intended to be protected by the scope of the patent application.

圖1為習知的HVA技術的畫素結構的示意圖。1 is a schematic diagram of a pixel structure of a conventional HVA technique.

圖2為習知的液晶顯示器的HVA驅動方式的示意圖。2 is a schematic diagram of a conventional HVA driving method of a liquid crystal display.

圖3A為習知HVA技術300 pin雙邊驅動的閘極驅動積體電路模組的示意圖。FIG. 3A is a schematic diagram of a gate drive integrated circuit module of a 300-pin bilateral drive of a conventional HVA technology. FIG.

圖3B為習知HVA技術400 pin雙邊驅動的閘極驅動積體電路模組的示意圖。FIG. 3B is a schematic diagram of a gate drive integrated circuit module of a 400-pin bilateral drive of a conventional HVA technology. FIG.

圖4為本發明第一實施例的液晶顯示器的HVA驅動方式的示意圖。4 is a schematic view showing an HVA driving method of a liquid crystal display according to a first embodiment of the present invention.

圖5A為利用本發明第一實施例方法的300 pin雙邊驅動的閘極驅動積體電路模組的示意圖。FIG. 5A is a schematic diagram of a 300 pin bilaterally driven gate drive integrated circuit module using the method of the first embodiment of the present invention. FIG.

圖5B為利用本發明第一實施例方法的400 pin雙邊驅動的閘極驅動積體電路模組的示意圖。FIG. 5B is a schematic diagram of a 400 pin bilaterally driven gate drive integrated circuit module using the method of the first embodiment of the present invention. FIG.

圖6為本發明第二實施例的液晶顯示器的HVA驅動方式的示意圖。FIG. 6 is a schematic diagram of an HVA driving method of a liquid crystal display according to a second embodiment of the present invention.

圖7為本發明第三實施例之閘極波型產生電路的示意圖。Fig. 7 is a schematic view showing a gate mode generating circuit of a third embodiment of the present invention.

【主要部分代表符號說明】[Main part representative symbol description]

10‧‧‧第一D型正反器10‧‧‧First D-type flip-flop

20‧‧‧第二D型正反器20‧‧‧Second D-type flip-flop

30‧‧‧反向器30‧‧‧ reverser

3a、3b、5a、5b‧‧‧閘極驅動積體電路模組3a, 3b, 5a, 5b‧‧‧ gate drive integrated circuit module

40‧‧‧位準移位元件40‧‧‧ position shifting element

70‧‧‧電路70‧‧‧ Circuitry

C1 、C2 、C3 ‧‧‧電容C 1 , C 2 , C 3 ‧‧‧ capacitors

CPV‧‧‧垂直時脈訊號CPV‧‧‧ vertical clock signal

CPV-R‧‧‧反相垂直時脈訊號CPV-R‧‧‧ inverted vertical clock signal

Dm 、Dm-1 、Dm-2 ‧‧‧資料線D m , D m-1 , D m-2 ‧‧‧ data line

G0、G1、G1199、G1200‧‧‧閘極線訊號G0, G1, G1199, G1200‧‧‧ gate signal

Gn 、Gn-1 、Gn-2 ‧‧‧閘極線G n , G n-1 , G n-2 ‧‧ ‧ gate line

STV‧‧‧垂直起始脈衝訊號STV‧‧‧Vertical start pulse signal

STV-1、STV-2‧‧‧STV的延遲訊號Delay signal for STV-1, STV-2‧‧‧STV

T1 、T2 ‧‧‧電晶體T 1 , T 2 ‧‧‧ transistors

TCPV ‧‧‧CPV訊號的週期T CPV ‧‧‧CPV signal cycle

TD1、TD2‧‧‧時間差TD1, TD2‧‧‧ time difference

Vgh、Vgl‧‧‧電壓值Vgh, Vgl‧‧‧ voltage value

10‧‧‧第一D型正反器10‧‧‧First D-type flip-flop

20‧‧‧第二D型正反器20‧‧‧Second D-type flip-flop

30‧‧‧反向器30‧‧‧ reverser

40‧‧‧位準移位元件40‧‧‧ position shifting element

70‧‧‧電路70‧‧‧ Circuitry

CPV‧‧‧垂直時脈訊號CPV‧‧‧ vertical clock signal

CPV-R‧‧‧反相垂直時脈訊號CPV-R‧‧‧ inverted vertical clock signal

G0‧‧‧閘極第零訊號G0‧‧‧The second zero signal

STV‧‧‧垂直起始脈衝訊號STV‧‧‧Vertical start pulse signal

STV-1、STV-2‧‧‧STV的延遲訊號Delay signal for STV-1, STV-2‧‧‧STV

Vgh、Vgl‧‧‧電壓值Vgh, Vgl‧‧‧ voltage value

Claims (20)

一種用於顯示器的閘極波型產生方法,其中該顯示器具有一垂直起始脈衝(STV)訊號,該方法包括:利用該STV訊號來產生一第一延遲訊號,其中該第一延遲訊號較該STV訊號延遲一第一時間差;利用該第一延遲訊號來產生一第二延遲訊號,其中該第二延遲訊號較該第一延遲訊號延遲一第二時間差;以及利用該第一延遲訊號來產生一閘極第零訊號,其中該閘極第零訊號與該第一延遲訊號同步。A gate wave type generating method for a display, wherein the display has a vertical start pulse (STV) signal, the method comprising: generating a first delay signal by using the STV signal, wherein the first delay signal is The STV signal is delayed by a first time difference; the first delay signal is used to generate a second delay signal, wherein the second delay signal is delayed by a second time difference from the first delay signal; and the first delay signal is used to generate a second delay signal a gate zero signal, wherein the gate zero signal is synchronized with the first delay signal. 如申請專利範圍第1項之方法,其中該顯示器更具有一垂直時脈(CPV)訊號,其具有一週期,而該第二時間差為該CPV訊號的該週期的一半。The method of claim 1, wherein the display further has a vertical clock (CPV) signal having a period, and the second time difference is half of the period of the CPV signal. 如申請專利範圍第2項之方法,其中該顯示器更包括一第一D型正反器,其接收該STV訊號及該CPV訊號,並輸出該第一延遲訊號。The method of claim 2, wherein the display further comprises a first D-type flip-flop that receives the STV signal and the CPV signal and outputs the first delay signal. 如申請專利範圍第2項之方法,其中該顯示器更包括一反向器,其接收該CPV訊號,並將該CPV訊號作相位轉換,以輸出一反相訊號。The method of claim 2, wherein the display further comprises an inverter that receives the CPV signal and phase-converts the CPV signal to output an inverted signal. 如申請專利範圍第4項之方法,其中該顯示器更包括一第二D型正反器,其接收該第一延遲訊號及該反相訊號,並以該反相訊號為時脈,以輸出該第二延遲訊號。The method of claim 4, wherein the display further comprises a second D-type flip-flop that receives the first delay signal and the inverted signal, and uses the inverted signal as a clock to output the The second delay signal. 如申請專利範圍第5項之方法,其中該顯示器更包括N條閘極線及一閘極驅動電路,其中N≧3,該閘極驅動電路接收該 第二延遲訊號,以產生一閘極第一訊號、一閘極第二訊號…一閘極第N訊號。The method of claim 5, wherein the display further comprises N gate lines and a gate driving circuit, wherein N ≧ 3, the gate driving circuit receives the The second delay signal is to generate a gate first signal, a gate second signal... a gate N signal. 如申請專利範圍第1項之方法,其中該顯示器更包括一位準移位元件,其接收該第一延遲訊號、一高參考位準及一低參考位準,以輸出該閘極第零訊號,並基於該高參考位準及該低參考位準,使得該第一延遲訊號的電壓值與該閘極第零訊號的電壓值不同。The method of claim 1, wherein the display further comprises a quasi-shifting component that receives the first delay signal, a high reference level, and a low reference level to output the gate zero signal And based on the high reference level and the low reference level, the voltage value of the first delay signal is different from the voltage value of the gate zero signal. 如申請專利範圍第1項之方法,其中該顯示器為具有一薄膜電晶體結構的顯示器。The method of claim 1, wherein the display is a display having a thin film transistor structure. 如申請專利範圍第1項之方法,其中該顯示器為一液晶顯示器、一電漿顯示器、一發光二極體顯示器、一有機發光二極體顯示器或一奈米碳管顯示器。The method of claim 1, wherein the display is a liquid crystal display, a plasma display, a light emitting diode display, an organic light emitting diode display or a carbon nanotube display. 一種顯示器,其具有一垂直起始脈衝(STV)訊號及一垂直時脈(CPV)訊號,該顯示器包括:一閘極波型產生電路,其包括;一第一D型正反器,接收該STV訊號及該CPV訊號,並輸出一第一延遲訊號;一反向器,接收該CPV訊號,並輸出一反相訊號;一第二D型正反器,分別電連接至該第一D型正反器及該反向器,其中該第二D型正反器接收該第一延遲訊號及該反相訊號,並輸出一第二延遲訊號;以及一位準移位元件,電連接至該第一D型正反器,接收該第一延遲訊號,並輸出一閘極第零訊號。A display having a vertical start pulse (STV) signal and a vertical clock (CPV) signal, the display comprising: a gate wave type generating circuit, comprising: a first D-type flip-flop, receiving the The STV signal and the CPV signal output a first delay signal; an inverter receives the CPV signal and outputs an inverted signal; and a second D-type flip-flop is electrically connected to the first D-type a flip-flop and the inverter, wherein the second D-type flip-flop receives the first delay signal and the inverted signal, and outputs a second delay signal; and a quasi-displacement element electrically connected to the The first D-type flip-flop receives the first delay signal and outputs a gate zero signal. 如申請專利範圍第10項之顯示器,更包括N條閘極線及一閘極驅動電路,其中N≧3,該閘極驅動電路接收該第二延遲訊號,以產生一閘極第一訊號、一閘極第二訊號…一閘極第N訊號。 The display of claim 10, further comprising N gate lines and a gate driving circuit, wherein N ≧ 3, the gate driving circuit receives the second delay signal to generate a gate first signal, A second signal of the gate... a gate N signal. 如申請專利範圍第10項之顯示器,其中該第一延遲訊號較該STV訊號延遲一第一時間差,而該位準移位元件更接收一高參考位準及一低參考位準,且基於該高參考位準及該低參考位準,使得該第一延遲訊號的電壓值與該閘極第零訊號的電壓值不同。 The display of claim 10, wherein the first delay signal is delayed by a first time difference from the STV signal, and the level shifting component further receives a high reference level and a low reference level, and based on the The high reference level and the low reference level are such that the voltage value of the first delay signal is different from the voltage value of the gate zero signal. 如申請專利範圍第10項之顯示器,其中該第二延遲訊號較該第一延遲訊號延遲一第二時間差,該CPV訊號具有一週期,而該第二時間差為該CPV訊號的該週期的一半。 The display of claim 10, wherein the second delay signal is delayed by a second time difference from the first delay signal, the CPV signal has a period, and the second time difference is half of the period of the CPV signal. 如申請專利範圍第10項之顯示器,其中該顯示器為一液晶顯示器、一電漿顯示器、一發光二極體顯示器、一有機發光二極體顯示器或一奈米碳管顯示器。 The display of claim 10, wherein the display is a liquid crystal display, a plasma display, a light emitting diode display, an organic light emitting diode display or a carbon nanotube display. 一種用於一顯示器的電路,該電路包括:一第一D型正反器,接收一垂直起始脈衝(STV)訊號及一垂直時脈(CPV)訊號,並輸出一第一延遲訊號;一反向器,接收該CPV訊號,並輸出一反相訊號;一第二D型正反器,分別電連接至該第一D型正反器及該反向器,其中該第二D型正反器接收該第一延遲訊號及該反相訊號,並輸出一第二延遲訊號;以及一位準移位元件,電連接至該第一D型正反器,接收該 第一延遲訊號,並輸出一閘極第零訊號。 A circuit for a display, the circuit comprising: a first D-type flip-flop, receiving a vertical start pulse (STV) signal and a vertical clock (CPV) signal, and outputting a first delay signal; The inverter receives the CPV signal and outputs an inverted signal; a second D-type flip-flop is electrically connected to the first D-type flip-flop and the inverter, wherein the second D-type is positive The counter receives the first delay signal and the inverted signal, and outputs a second delay signal; and a quasi-shifting component electrically connected to the first D-type flip-flop to receive the The first delay signal and output a gate zero signal. 如申請專利範圍第15項之電路,其中:該第一D型正反器以該CPV訊號為時脈,利用該STV訊號,以輸出該第一延遲訊號;該反向器對該CPV訊號作相位轉換,以輸出該反相訊號;以及該第二D型正反器以該反相訊號為時脈,利用該第一延遲訊號,以輸出該第二延遲訊號。 The circuit of claim 15, wherein: the first D-type flip-flop uses the CPV signal as a clock, and uses the STV signal to output the first delay signal; the inverter performs the CPV signal Phase switching to output the inverted signal; and the second D-type flip-flop uses the inverted signal as a clock to utilize the first delayed signal to output the second delayed signal. 如申請專利範圍第15項之電路,其中該顯示器更包括N條閘極線及一閘極驅動電路,其中N≧3,該閘極驅動電路接收該第二延遲訊號,以產生一閘極第一訊號、一閘極第二訊號…一閘極第N訊號。 The circuit of claim 15, wherein the display further comprises N gate lines and a gate driving circuit, wherein N ≧ 3, the gate driving circuit receives the second delay signal to generate a gate One signal, one gate second signal... one gate N signal. 如申請專利範圍第15項之電路,其中該第一延遲訊號較該STV訊號延遲一第一時間差,而該位準移位元件更接收一高參考位準及一低參考位準,且基於該高參考位準及該低參考位準,使得該第一延遲訊號的電壓值與該閘極第零訊號的電壓值不同。 The circuit of claim 15, wherein the first delay signal is delayed by a first time difference from the STV signal, and the level shifting component further receives a high reference level and a low reference level, and based on the The high reference level and the low reference level are such that the voltage value of the first delay signal is different from the voltage value of the gate zero signal. 如申請專利範圍第15項之電路,其中該第二延遲訊號較該第一延遲訊號延遲一第二時間差,該CPV訊號具有一週期,而該第二時間差為該CPV訊號的該週期的一半。 The circuit of claim 15, wherein the second delay signal is delayed by a second time difference from the first delay signal, the CPV signal has a period, and the second time difference is half of the period of the CPV signal. 如申請專利範圍第15項之電路,其中該顯示器為具有一薄膜電晶體結構的顯示器。 The circuit of claim 15, wherein the display is a display having a thin film transistor structure.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6476789B1 (en) * 1998-11-20 2002-11-05 Sharp Kabushiki Kaisha System construction of semiconductor devices and liquid crystal display device module using the same
TWI225234B (en) * 2002-08-27 2004-12-11 Sharp Kk Display device, control device of display drive circuit, and driving method of display device
TW200739490A (en) * 2006-04-07 2007-10-16 Au Optronics Corp Shift register and driving method
US7342576B2 (en) * 2003-12-30 2008-03-11 Boe Hydis Technology Co., Ltd. Driving circuit of liquid crystal display

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6476789B1 (en) * 1998-11-20 2002-11-05 Sharp Kabushiki Kaisha System construction of semiconductor devices and liquid crystal display device module using the same
TWI225234B (en) * 2002-08-27 2004-12-11 Sharp Kk Display device, control device of display drive circuit, and driving method of display device
US7342576B2 (en) * 2003-12-30 2008-03-11 Boe Hydis Technology Co., Ltd. Driving circuit of liquid crystal display
TW200739490A (en) * 2006-04-07 2007-10-16 Au Optronics Corp Shift register and driving method

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