TWI344106B

TWI344106B - Artifact-free transitions between dual display controllers

Info

Publication number: TWI344106B
Application number: TW096110222A
Authority: TW
Inventors: Mark J Foster
Original assignee: One Laptop Per Child Ass Inc
Priority date: 2006-03-23
Filing date: 2007-03-23
Publication date: 2011-06-21
Also published as: JP2007298962A; WO2007112019A3; TW200745940A; WO2007112019A2; KR20070096914A; KR100910683B1; JP4992140B2

Description

1344106 九、發明說明：【务明所屬之技術領域】其二;係=一種具有雙顯示控制器之顯示系統及的顯=及:：:在雙顯示控恢間無失真傳輸【先前技術】號至統中’中央處理器（咖)輸出一信出-信號進而驅二⑽過運算處理之後輸而在-雙二= : = :件輸出影像。哭廿、就必須設置兩個顯示抻制 :及C要顯示控制器及第二顯示控制器，且：主及弟一顯不控制器各自獨立的接受中央 . 且該顯示元件可被JL中任一個§ 、。、、控制，切換該主要制器所控制。然而在秧这主要及第一顯不控制器的同時，以同步化以避免該顯示元件顯示金^輸出仏號加什,貝不旦面有失真的情況。目則有夕種技術可使該主要及第二顯示控制 :::二:所熟知的「—」技術’該技術讓主要及第不控制裔同時運作’並將其輸出之訊號加以合 —不兀件輸出—完整的影像；但這種同步化且號的技術需要昂貴且複雜的電子電路系統。輸出另一種傳統的技術，則是將主要顯；控制段晝面傳輸至第二顯示控制器並進行調同功效，而該片段畫面均可以在任-個顯示控;器=: 5 整，但此種片段畫面需要被傳輪及調整的技術理器連續性的運作。要處然而’上述的技術不免都會有下列缺點，由於傳統方高要兩個顯示控制器同時運作，且處理器也需要做連嘖 :斷的處理’導致系統必須消耗大量能源;但的二 :技術方案可以不需要處理器做連續性的運作後雜且昂貴的電路設計。尤万、二!t述的論點，必須針對主要及第二顯示控制器同 ‘作、加以改進；首先’必須減少處理器做連續性的 =的==不需r連續性的運作;再者，不需應用又使·^體系統更具經濟效益；此外，低耗月匕的系統也是欲追求的目標。 - 【發明内容】示系==要目的係提供一種具有雙顯示控制器之顯本發明之再：法，可利θ用該顯示系統控制-顯示裝置。示系統及1驅動方提供一種具有雙顯示控制器之顯達成顯示裝置不勵_輪的運作就可1344106 IX. Description of invention: [Technical field to which it belongs] Second; system = display system with dual display controller and display = and ::: no distortion transmission between dual display control [previous technology] In the system, the central processor (coffee) outputs a letter-out signal and then drives the second (10) after the arithmetic processing and then inputs the -double two = := : piece output image. To cry, you must set up two display systems: and C to display the controller and the second display controller, and: the main and the younger ones are not independently controlled by the center. And the display element can be used by JL. One§ , . , control, switch the control of the main controller. However, in the meantime, the main and the first display controller are synchronized to prevent the display element from displaying the gold output nickname, and the beauties are distorted. The purpose is to enable the primary and secondary display controls:: 2: The well-known "-" technology 'this technology allows the primary and the first non-controllings to operate simultaneously' and combines the signals they output - no Component output - a complete image; but this synchronized and numbered technology requires expensive and complex electronic circuitry. Another traditional technique is to transmit the main control; the control segment is transmitted to the second display controller and the modulating effect is performed, and the segment picture can be displayed in any one of the display controls; The fragment picture needs to be operated by the relay and the technical continuity of the adjustment. However, the above-mentioned technology will inevitably have the following shortcomings, because the traditional Fang Gao requires two display controllers to operate at the same time, and the processor also needs to do the trick: the broken processing 'causes the system must consume a lot of energy; but the second: The technical solution can eliminate the need for the processor to perform a complicated operation and then the complicated circuit design. The arguments of Youwan and II!t must be improved for the main and second display controllers; firstly, the operator must reduce the continuity of the == without the need for r continuity; It is more economical to use the system without any application; in addition, the system with low monthly consumption is also the goal to be pursued. - [Description of the Invention] The system is to provide a dual display controller with the dual display controller. The method can be used to control the display device with the display system. The display system and the 1 driver provide an operation with a dual display controller to achieve the operation of the display device

古本I月提出多個實施方式藉以達到以上的目M UL 制器之顯示系統，其包括:-處：二第不卫制态，—第二顯示控制器；一— 用之畫面緩衝哭.一楚__ ° ，·肩不控制器所使器，·以及十㈣帛-不控制器所使用之晝面缓衝 ^裝置。其中，該處理器送出複數個顯示畫面給该第—顯示控制器；控制器傳送給該第二顯示=不-面再透過該第-顯示在沒有對該等顯示書面做==該第二顯示控制器可正動作的情況顯不晝面做至少—個矯在琴處理：裝置輪出之影像。在。亥處理益將複數個顯示所使用之晝面緩衝器的情：’第：:第-顯示控制器輸出影像，，若動邊第一顯示控制器所使用之畫面被寫入器則將先前的該等顯示晝面在】’3亥弟二顯示控制用之畫面緩衝器，接著該第二孽于;示控制器所使脈：該影像時脈之傳該第:顯示㈣g轉_ i , 處理2該第—顯示㈣11可被切換成閒置模式。七該即使該處理器未將任何農置顯示影像，使用之蚩旦面寫入5亥第一顯示控制器所旦_态。當該第二顯示控制器以同一畫面訊號二制置顯示影像一段預定的時間後，該第二顯‘ 換成閒置模式。而不論任何時間，當一新的被寫入該第二顯示控制器所使用之晝面緩衝器不裳置的控制權就會緊跟著垂直同步脈衝的後緣以第―顯示控制器回到該第—顯示控制器。在本發明實Guben I month proposed a number of implementations to achieve the above display system of the M UL system, including: - at: two non-defense state, - second display controller; one - use the picture buffer cry. Chu __ ° , · Should not be the controller of the controller, · and ten (four) 帛 - no buffer used by the controller. Wherein, the processor sends a plurality of display screens to the first display controller; the controller transmits the second display = no-face and then transmits the first-display without writing the display to the second display == the second display The situation in which the controller can be positively operated is not at least one-handed in the piano: the image of the device is rotated. in. The processing will be used to display the number of buffers used in the display: '第::第-display controller output image, if the screen used by the first display controller is moved to the previous The display screen is in the screen buffer of the '3 haidi two display control, and then the second 孽 is; the controller is pulsing: the image clock is transmitted by the first: display (four) g to _ i, processing 2 The first - display (four) 11 can be switched to the idle mode. VII. Even if the processor does not display any farm display image, the used surface is written to the state of the first display controller. After the second display controller displays the image for the predetermined time with the same picture signal, the second display is replaced with the idle mode. At any time, when a new buffer that is written to the second display controller is not present, the control will be followed by the trailing edge of the vertical sync pulse to return to the display controller. The first - display controller. In the present invention

lJ^lUO •，例中，當該處理器接收到外部裝置的弟二顯示控制哭可由門罢f _4、Ί °就Τ，5亥 Μ 1 切切換成啟動模式。所有的訊號傳輸，例如該第一顧:=二的=執行面。既妙Γ^Γ 錄而可達成無失真的顯示書均為自訊號的傳輸、紀錄以及控制權的切換巧自動執仃’故不f要該處理器做 = 亥弟頰不控制器與該第二顯示 =:=r減少能量的消耗。综== =:ί統及其制器之顯示系-種具有雙顯示控統以控制顯示裝置、可在第一^由低耗能的顯示系 *達成無失真影像輸出硬體而更適用於價才夂導、而要卬貝且複雜之知格導向或能源消耗導向之應用面【實施方式】本發明提出的實施例係為一統，該顯示系統則可被運用在一，:异構中的顯不系驅動領亍梦罟在系，、先、方法及電腦程式以第===影;。_系統包括:-處理器;- 所使用之畫=衝口制器；一第一顯示控制器衝器；以及1亍μ—弟二顯示控制器所使用之畫面緩 .，、、頁不裝置。該顯示裝置可被該第—顯示控制 13.44106 ^不役刺益所驅動而顯示影像，旦面被寫入該第一顯示控制器所使用之：Ί 示裝置的控制權，由該第—顯衝為’該顯 t ”、、貝不控制态切換為贫筮-相- 3 該第二顯示控制器進行將該顯示裝置的V:權：該第-顯示控制器切換到該第瑕置的控制權由緊跟者垂直同步脈衝的後緣乍為進行，二== 入該另：實施例中’當一個新的顯示晝面被寫，制權就合：;，所使用之晝面緩衝器’該顯示裝置的 :.mL 示控制器切換到該第-顯示控制 :行同樣的’此控制權切換的動作是在垂直遮沒期間之間入/請參考第—圖，其為此發明全系統1GG之示意圖，节二可應用：本發明多個實施方式。該全系統丨〇〇 • i 7囡口十异機運异裝置，然而一個典型 •置包括：一處理器⑽、-第-顯示控制器刚、示控制器106及一顯干驻罢1ne 斗士一、次』不义置⑽。έ亥處理器-102可分别控制该第-顯示控制器】04與該第二顯示控制】〇6 ;該第一顯不控制器104可内建於該處理器]〇2，也可以以不同功能的電路與該處理器1〇2有所區別。而該計算機運算裝置 J為筆記型電腦、掌上型電腦、桌上型電腦、計算器、攜帶式電話或個人數位助理(PDA)等；同樣地，該顯示裳^ ι〇8可為液晶顯示器（LCD)、陰極射線管（CRT)或電漿顯示 9 1344106 • » 器；該處理器102可以典型的設置於計算機運算裝置的中央處理單元（CPU)，而該第一顯示控制器104與該第二顯示控制器106可為一傳統視訊圖形陣列（VGA)控制器或是特殊應用積體電路(ASIC)控制器，上述例子均為可能之硬體裝置但並不以此為限。於此實施例中，為該第二顯示控制器106支援六種介面；第一介面為薄膜電晶體（TFT)輸入埠，用以接收該第一顯示控制器104所輸出之顯示畫面；第二介面為雙源電晶體對電晶體邏輯（double edged transistor-transistor logic, DETTL)液晶輸出埠，其直接與積體電路之薄膜電晶體面板驅動器連接，用以在適當的薄膜電晶體顯示裝置上輸出液晶顯示；第三介面為雙向系統管理匯流排（system management bus, SMBUS)序列瑋，其工作頻率至少為 ΙΟΟΚΗζ並與該第二顯示控制器106内部的設定暫存器連接，且可對該暫存器進行讀取、寫入的動作；第四介面為一組單輸入/輸出或多輸入/輸出的端子介面，可管理在第一顯示控制器104與該第二顯示控制器106之間的臨界時序切換；第五介面為同步動態隨機存取記憶體（SDRAM)介面埠，可與低功率的同步動態隨機存取記憶體連接以儲存單一完整之顯示晝面，該第二顯示控制器106可藉由從該同步動態隨機存取記憶體擷取顯示畫面以使顯示裝置108 進行自發性更新晝面的動作；第六介面直接與一個 14.31818 MHz的晶體連接，該晶體可忽略影像輸入埠的狀態而提供一個獨立的畫面更新的像素時脈，該獨立的畫面 1344106 更新之像素時脈在畫面更新率為5 UHz的愔’牙丁氣 5w。此外’該獨立的晝面更新之 2 上述用以儲存齡晝面之，動態隨機存取記㈣= 介面時序（interface timing)。 _ ’、而根據本發明之另一實施例，兮筮_ ._ 八各1該弟—顯示控制器106 更包’其為多數個端子以連接於 1〇2’該連接關係可以在該處理器102在接处為 :時，將該第二顯示控制器106由閒置模式切換= 此外’该第二顯不控制器106具有多樣的運曾該第二顯示控制器106支援，，顏色混合替° swiping)”可讓該顯示裝置1〇8表現出如同傳統μ位⑺时顯示面版。該，，顏色混合替換(c〇1〇r swizznng)”技巧可$的覺上不造成差異的情況下減少位元數目。該第二顯示拎視态更具有反鋸齒（anti_aliasing)的能力，可增加該lJ^lUO • In the example, when the processor receives the external device, the second display control crying can be stopped by the door f _4, Ί °, and 5 Μ 1 switch to the startup mode. All signal transmissions, such as the first: = two = execution face. Both the wonderful and the Γ^ Γ 而可可可可可可可无无无无无无无无无无无无无无无无无无无无无无无无无无无无无无无无无无无无无The second display =: = r reduces the energy consumption. Comprehensive == =: ί system and its display system - with dual display control system to control the display device, can be achieved in the first low-energy display system * to achieve distortion-free image output hardware and more suitable for The application of the present invention is based on the embodiment of the present invention. The display system can be used in one, heterogeneous The display is not driven by the system, the first, the method and the computer program with the === shadow; _ system includes: - processor; - the painting used = punch controller; a first display controller punch; and 1 亍 μ - brother two display controller used to slow the picture,,, page not installed . The display device can be driven by the first display control 13.44106 ^ inactive to display an image, and the surface is written into the first display controller: the control device of the display device, the first display For the 'display', the switch is switched to the lean-phase- 3, the second display controller performs the V: weight of the display device: the first display controller is switched to the control of the first set The weight is performed by the trailing edge of the vertical sync pulse of the follower, and the second == into the other: In the embodiment, 'When a new display is written, the weight is combined:;, the buffer used 'The display device: .mL indicates that the controller switches to the first-display control: the same line 'this control right switching action is between the vertical blanking period / please refer to the first figure, which is the invention A schematic diagram of the system 1GG, section 2 is applicable: a plurality of embodiments of the present invention. The system-wide i i port is a different device, but a typical device includes: a processor (10), a - display Controller just, the controller 106 and a display station 1ne fighters one, the second" no The device (10) can control the first display controller 04 and the second display control 〇6; the first display controller 104 can be built in the processor 〇2, It is also possible to distinguish between the different functions of the circuit and the processor 1. The computer computing device J is a notebook computer, a palmtop computer, a desktop computer, a calculator, a portable telephone or a personal digital assistant (PDA). Similarly, the display device 8 can be a liquid crystal display (LCD), a cathode ray tube (CRT) or a plasma display 9 1344106; the processor 102 can be typically disposed in a computer computing device. a central processing unit (CPU), and the first display controller 104 and the second display controller 106 can be a conventional video graphics array (VGA) controller or an application specific integrated circuit (ASIC) controller, the above example It is a possible hardware device, but not limited thereto. In this embodiment, the second display controller 106 supports six interfaces; the first interface is a thin film transistor (TFT) input port for receiving The output of the first display controller 104 The second interface is a double edged transistor-transistor logic (DETTL) liquid crystal output port, which is directly connected to the thin film transistor panel driver of the integrated circuit for use in a suitable thin film transistor. The liquid crystal display is outputted on the display device; the third interface is a system management bus (SMBUS) sequence, which has an operating frequency of at least ΙΟΟΚΗζ and is connected to the setting register inside the second display controller 106, and The register can be read and written; the fourth interface is a set of single input/output or multiple input/output terminal interfaces, which can be managed by the first display controller 104 and the second display controller The critical timing switching between 106; the fifth interface is a synchronous dynamic random access memory (SDRAM) interface, which can be connected with a low power synchronous dynamic random access memory to store a single complete display surface, the second The display controller 106 can cause the display device 108 to perform a spontaneous update by capturing a display screen from the synchronous DRAM. The sixth interface is directly connected to a crystal of 14.31818 MHz, which can ignore the state of the image input port and provide a separate picture update pixel clock. The independent picture 1344106 updates the pixel clock at the picture update rate of 5 UHz's 愔' teeth are 5w. In addition, the independent facet update 2 is used to store the age, dynamic random access (4) = interface timing. _ ', and according to another embodiment of the present invention, 兮筮_._八一一一弟 - display controller 106 further package 'which is a plurality of terminals to connect to 1 〇 2' the connection relationship can be in the process When the interface is::, the second display controller 106 is switched from the idle mode = in addition, the second display controller 106 has various functions, and the second display controller 106 supports the color mixing. ° swiping)" allows the display device 1〇8 to display a faceplate as in the conventional μ position (7). This, the color mixing replacement (c〇1〇r swizznng) technique can be perceived as not causing a difference. Reduce the number of bits. The second display 拎 state is more anti-aliasing, which can be increased

裝置108顯示文字的銳利度；再者，該第二顯示控制二\ = 可支援單色調模式（monochrome)以將自動定位書去階模式。 …、轉成灰另外’該第二顯示控制器1〇6可在一傳遞模气 (pass-through m〇de)下使一接下來的顯示晝面透^ (transparency) ’ 亦即在傳送模式（pass_thr0Ugh m〇de)下該第二顯示控制器1〇6會將該顯示晝面傳送該第一顯示控制哭 104而不做任何操作演算（mai^_ati〇ns)。如此就可達成一個簡單基本的LCD時序控制晶片與自動化的飛越模式 1344106 (%妨mode);飛越模式（fly-by mode)可避免同步動態隨機存取記憶體緩衝器的不必要寫入，便可以減少整體的能量消耗’而可應用於最小耗電量的設定。該第二顯示控制器 106可支援三原色(RGB)面板的除錯，也具有在生產線端的 =我測試(self_test)功能。由於該第二顯示控制器1〇6可被〇又疋為在傳遞模式（pass-through mode)下不會對該顯示書面做任何操作演算（manipulations)，這樣就可以在生產時測試該第二顯示控制器1〇6是否正常。上述針對第二顯示控制器106的討論可與第二圖相配合。々月β考卓一圖，其為本發明顯示糸統200的示音圖，第厂顯示控制器1〇4連接多個時脈產生器2〇6以及一晝面緩衝态202 ;然而為了方便說明，該等時脈產生器2〇6係内建於該第—顯示控制器104内部，該第一顯示控制器104 =含至少—個暫存器（叫丨ster)(圖未示）；—第二顯示控制 :而：連接多個時脈產生器2〇8以及一晝面緩衝器2〇4; ...... 了方便說明，該等時脈產生器208係π#%%# - =Η)6内部，且該第二顯示控制器1%更包含一子21〇、一第二端子212、一第二端子216、—筮7 乐一鳊子214、一第四未示)。 ^子218以及至少-個暫存器㈣is㈣(圖示控制ί = :〇2係輸出複數個顯示顯示晝面給該第-顯 ⑽所第二顯示控制器1〇6以刷新-顯示裝置該顯示裝置=:該等顯示顯示畫面的數量，足以刷新置1〇8的顯示，而該等顯示晝面則是由顯示於該 12 1344106 > ψ ，.，、貝不裝置Κ)8之影像的畫素資料（pixel_by_pixel _所组成，且該晝面緩衝器2〇2、2〇4係用以儲存該等顯示晝面，而該顯示裝置108可被該第一顯示控制器〗〇4與該第二顯示控制器H)6之中任一個控制器所驅動；該等端子係用以控制該顯示裝置108於該第一顯示控制器1〇4與該第二顯不控制盗1G6之控制權間的切換。該處理器1Q2係輸出複數個顯不晝面顯示畫面給該第一顯示控處理器1〇2將顯示畫面寫入該畫面緩衝器2〇2，則顯示控制器H)4負責驅動該顯示裝置1〇8刷新畫面；若該處理器102未將顯示畫面寫入該晝面緩衝器搬，則該顯 :襄置⑽的控觸職切換至該第二顯示控制器】％。 2處理器1〇2再次將顯示晝面寫入該晝面緩衝器202, 示裝置⑽的控制權回到該第—顯示控制器⑽。顯示裝置⑽的控制權在該第一顯示控制器刚 ^二顯示控制器1G6〇切換時，可能會導致書面的 facts)，本發明所提出之切換方式可避免失真的情況，請參閱第三至五圖。，牛==本發明驅動該顯示裝置108的方法流程圖，收圭面顯示控制器104自該處理器102接衝器= 且該顯示晝面資料被儲存於該晝面緩步驟304 ’該題+壯班 ⑻响ng int叫於'=第2 _108的控制權在遮沒期間控制器106之_切換期1〇4與該第二顯示又』間（blanking interval)是指在 1344106 垂直同步脈衝（v-syncpuise)或水平同步脈衝(H_Syncpulse) 的後緣與下一條掃瞄線起始的時間間隔，掃瞄線會顯示該顯示裝置108所顯示晝面的整列畫素資料；此處是使用垂直遮沒期間’且該切換的動作是在垂直同步脈衝的後端發生0 在一實施例中，該顯示裝置1〇8被該第一顯示控制器 1。〇4所驅動’且沒有任何顯示畫面資料被寫入該畫面緩衝The device 108 displays the sharpness of the text; further, the second display control two \ = can support the monochrome mode (monochrome) to automatically locate the book in the de-order mode. ..., turning into ash and additionally 'the second display controller 1 〇 6 can make a subsequent display transparency (transparency) under a pass-through m 'de, that is, in the transfer mode (pass_thr0Ugh m〇de) The second display controller 1〇6 will transmit the first display control cry 104 to the display face without any operation calculation (mai^_ati〇ns). In this way, a simple basic LCD timing control chip and an automated fly-by mode 1344106 can be achieved; the fly-by mode avoids unnecessary writing of the synchronous DRAM buffer. It can reduce the overall energy consumption' and can be applied to the setting of minimum power consumption. The second display controller 106 can support the debugging of the three primary color (RGB) panels, and also has the = self test (self_test) function at the production line end. Since the second display controller 1〇6 can be turned into a pass-through mode, no operation calculations are performed on the display, so that the second can be tested at the time of production. Whether the controller 1〇6 is normal is displayed. The above discussion of the second display controller 106 can be coordinated with the second figure. 々月β考卓图, which is a sound diagram of the display system 200 of the present invention, the first display controller 1〇4 is connected to a plurality of clock generators 2〇6 and a buffered state 202; however, for convenience It is noted that the clock generators 2〇6 are built in the first display controller 104, and the first display controller 104=includes at least one register (not shown) (not shown); - second display control: and: connecting a plurality of clock generators 2 〇 8 and a buffer buffer 2 〇 4; ...... For convenience of explanation, the clock generators 208 are π#%% # - =Η6 internal, and the second display controller 1% further includes a sub- 21 〇, a second terminal 212, a second terminal 216, a 筮7 乐一鳊子214, a fourth not shown ). ^ child 218 and at least one register (four) is (four) (illustration control ί = : 〇 2 system outputs a plurality of display display screens to the first display (10) of the second display controller 1 〇 6 to refresh - display device display Device=: The number of display screens is sufficient to refresh the display of 1〇8, and the display surface is displayed by the image of the 12 1344106 > ψ , . The pixel data (pixel_by_pixel_) is composed, and the buffer buffers 2〇2, 2〇4 are used to store the display surfaces, and the display device 108 can be used by the first display controller The controller is driven by any one of the second display controllers H) 6; the terminals are used to control the control of the display device 108 on the first display controller 1〇4 and the second display control 1G6 Switch between. The processor 1Q2 outputs a plurality of display screens for the first display control processor 1〇2 to write the display screen to the screen buffer 2〇2, and the display controller H)4 is responsible for driving the display device. 1〇8 refreshes the screen; if the processor 102 does not write the display screen to the buffer buffer, the display of the display (10) switches to the second display controller]%. The processor 1 〇 2 again writes the display face to the face buffer 202, and the control of the display device (10) returns to the first display controller (10). The control right of the display device (10) may cause written facts when the first display controller just switches the display controller 1G6〇, and the switching mode proposed by the present invention can avoid distortion, please refer to the third to Five maps. , cattle == the flow chart of the method for driving the display device 108 of the present invention, the display controller 104 receives the buffer from the processor 102 = and the display face data is stored in the face buffer step 304 ' + Zhuangban (8) ring ng int called '= 2nd _108 control right during the occlusion period controller 106 _ switching period 1 〇 4 and the second display 』 (blanking interval) refers to the vertical synchronization pulse at 1344106 (v-syncpuise) or the time interval between the trailing edge of the horizontal sync pulse (H_Syncpulse) and the next scan line, the scan line will display the entire column of pixel data displayed by the display device 108; here is the use The vertical blanking period 'and the switching action occurs at the rear end of the vertical sync pulse. In one embodiment, the display device 1〇8 is used by the first display controller 1. 〇4 is driven' and no display picture data is written to the picture buffer

器202，貝該顯示裝f 1〇8的控制權則被士刀換至該第二顯示？制器106。相反地，該顯示裝置1〇8被該第二顯示控制器106所驅動，且有新的顯示顯示晝面寫人該晝面緩衝器202,則該顯示裝£】〇8的控制權回舰第一顯示控制器104。步驟306巾，在控制權被切換之後，該顯示裝置 1 〇 8會根據該擁有控制權之顯示控制器的驅動而刷新顯示畫面二該顯示裝置1〇8的控制權在該第一顯示控制器1〇4 與該第二顯示控制器1G6之中士刀換的方法將在第四圖及五圖做更詳細的說明。第四A圖及第四B圖為該顯示裝置1〇8的控制權由該第-顯不控制器H)4切換到該第二顯示控制器1〇6的方法流程圖。當該畫面緩衝器搬持續被寫人新的顯示書面， ::該第-顯示控制器104負責驅動該顯示裝置ι〇8顯示時該Γ顯示控制器104會將顯示晝面傳輸至該 _ 丹由"弟一”、、員不控制器106將該顯晝面緩衝器2〇4 ;此後’該第二顯示控制器曰由该畫面緩衡器2〇4擷取顯示畫面用以驅動該顯 14 1344106 « · 示裝置108。而該第二顯示控制器106可對該等顯示畫面執行至少一個之操作演算（manipulations)，例如調整輸出晝面之頻率、執行顏色混合替換（color swizzling)、反鑛齒 (anti-aliasing)等運算，並用以刷新該顯示裝置108。然而根據本發明的另一實施例，該第二顯示控制器 106可在不將該顯示畫面記錄至畫面緩衝器204的情況下，對該等顯示畫面執行至少一個之操作演算 (manipulations)，例如調整輸出晝面之頻率、執行顏色混合替換(color swizzling)、反鑛齒（anti-aliasing)等運算，並用以刷新該顯示裝置108。復參閱第四A圖，在步驟402中，第一顯示控制器104 負責驅動該顯示裝置108顯示影像；步驟404則判斷有無新的顯示晝面被寫入該畫面緩衝器202,若該畫面緩衝器 202持續被寫入新的顯示畫面，則依步驟402，由該第一顯示控制器104負責驅動該顯示裝置108顯示影像；相反地，若無新的顯示晝面被寫入該晝面緩衝器202，則進行步驟 406,將該第二顯示控制器106的第一端子210設定至一低階狀態（low state);接著步驟408,將一新的顯示畫面寫入該畫面緩衝器204;以下說明，該第二顯示控制器106會在垂直同步脈衝（V-Sync pulse)的後緣執行一顯示循環（display load cycle)。而該顯示循環(display load cycle)即包括將一新的顯示晝面寫入該晝面緩衝器204的步驟，此寫入的動作會在一垂直同步脈衝(V-Sync pulse)的後緣開始，並於下一垂直同步脈衝(V-Sync pulse)的後緣終止，而垂直同步脈 1344106 衝(V-Sync pulse)的後緣則是指一在顯示中顯示畫面的終端和一新的顯示畫面的起始端；意即該第二顯示控制器 1〇6會從第一掃瞄線開始紀錄畫素資料(pixd data)到一垂直同步脈衝(V-Syncpuhe)的後緣為止，而該垂直同步脈衝 (V-Sync puise)的後緣或該第二顯示控制器1〇6輸出顯示畫面的時序均由該處理器透過第二端子212輸入至該第二顯示控制器106，該第二端子212從第一掃瞄線開始到一垂直同步脈衝(V-Sync pulse)的後緣為止均保持在一低階狀態（low state)。 _ 該第二端子212在一垂直遮沒期間均保持在一高階狀態（high state)。該處理器丨〇2則是利用該第二端子2】2所在的狀態進行在第-顯示控制器1〇4與該第二顯示控制器之間控制權的切換之同步化，當一完整的畫面被寫二 A畫面緩衝S 204 ’該第二顯示控制器酬就會執行將控制權切換回該第二顯示控制器1〇6本身。在步驟410，該第二顯示控制器106會將複數個第_ 顯示控制n m之時序賴成複數個第三顯示控制器1〇6 之時序，根據本發明，上述之轉換動作會緊接在一垂直同步脈衝(V-Sync puise)的後緣，意即在垂直同步脈衝叫c Ρ·)開始到垂直遮沒期間的結束之間的時間。此外，該第 ^顯示控制器⑽也可將時脈產生器施所產生的時脈切換成時脈產生ϋ2〇8所產生的時脈，時脈產生器2〇6與道 I以有相_解，但時脈產生器漁料作並不與時脈生益206同步。然而，先輸入先輸出（Fim in First 16 M44106 FIF〇)的功能可以將由該第一顯示控制器104所輸入至第〜顯示控制器106的顯示晝面的時序修正而成與第二顯示，制态106的時序相匹配。但在本發明的另一實施例，該第—顯示控制器104之時序及第二顯示控制器1〇6之時序會分別在水平同步脈衝（H-Sync pulse)的遮沒期間 (blanking interval)進行調變，而畫面的同步化可由鎖相迴，(Phase Locked Loop，PLL)所達成也因此可連續性的進行顯示。在步驟412，②第二顯示控制n 1Q6會將該第一顯示 f制裔104中之複數個暫存器（register)及該第二顯示控制。。106中之複數個暫存器（register)重置^以㈨。而在步驟 “該第一顯示控制器i 〇6會將該晝面緩衝器2⑽由入 2切換成讀取模式。在本發明之—實施例中，此切換動像時相調變同時進行，即在完成影像時序的調 2: 不控制器1〇6使用該等暫存器與時脈產生器哭一影像輪出。該影像輸出包括擷取自該畫面緩衝 .4的員示晝面，而該顯示晝面可經操作演算 ^anlpu^_s)所得或完全不經操作演算(_咖_二 ^且°玄顯不裝置108的控制權切換之後，上述暫存 :時脈產生器〜在下一亀線起始的開端上在步驟416β 控制器ΚΗ切換至^示裝置:的控制權由該第—顯示制器丨〇6就從下!'弟二顯示控制器106 ’而該第二顯示控條掃瞄線起始的開端開始刷新該顯示裝 1344,106 置108的晝面，而該第二顯示控制器1〇6係獨立地根據該晝面緩衝器204的顯示晝面刷新該顯示裝置1〇8的畫面；在步驟418，5亥處理& 1〇2與該第一顯示控制胃被切換成閒置模式（inactive mode);相反地，在本發明的另一實施方式’該第-顯示控制器！〇4被切換成閒置模式（i咖二 mode)，但該處理器！ 02職持在一啟動模式⑽ve出㈣。而當該第二顯示控制器1〇6在使用相同的顯示畫面刷新該顯示裝置⑽達到—狀之次數時，該第二顯示控制器:〇6可被切換成閒置模式（inactive m〇de);而該預定之次數係儲存在該第二顯示控制器1〇6之暫存器中。第五圖為該顯示裝置1〇8的控制權由該第二益1〇6切換到該第一顯示控制器的方法流程圖。在S =〇:，該顯示裝置⑽係由該第二顯示控制器ι〇6負責 2新。步驟504，則會_是否有新的顯示晝面被寫入^ 旦面緩衝器202;若沒有（N〇)，則回到步驟5〇2由二 =示控制器腸負責刷新該顯示裝置1〇8;相反地⑽ =^進入步驟篇，該第一端子⑽被設定於狀恕（high state)，此狀鲅將佶兮楚θε _ ^ 白 I 使^—顯不控制器⑽位於 :型瞻騰d則高能寫人狀態，而此寫人的 =弟二顯示控制器106將該畫面緩衝器202中的顯示佥面存入該畫面緩衝器204。 ’ ’、旦在步驟508,該第二顯示控制器觸進行控制器104之時序盘該第_ g .，肩不變動作;同時，該第:二=厂控制器1〇6時序之間的調第一顯不控制器106進行時脈產生器施 18 1344106 與208的调變。在本發明之一實施例中，該調變會緊接在一垂直同步脈衝(V-Sync pulse)的後緣進行；相反地，在另一實施例，該調變則會在水平同步脈衝(H_Syncpulse)的遮沒期間（blanking interval)進行。The control of the display device f1〇8 is changed to the second display by the knife. Controller 106. Conversely, the display device 1〇8 is driven by the second display controller 106, and there is a new display to display the face buffer 202, and the display device is controlled to return to the ship. The first display controller 104. Step 306, after the control is switched, the display device 1 刷新 8 refreshes the display screen 2 according to the driving control of the display controller having control of the display device 1 〇 8 at the first display controller. The method of replacing the knives with the second display controller 1G6 will be explained in more detail in the fourth and fifth figures. The fourth A diagram and the fourth B diagram are flowcharts of the method in which the control right of the display device 1〇8 is switched to the second display controller 1〇6 by the first-display controller H)4. When the picture buffer is continuously written by the writer, the following display controller 104 is responsible for driving the display device ι 8 to display the display controller 104 to transmit the display to the _ dan The display buffer 2〇4 is used by the "弟一", the controller controller 106; thereafter, the second display controller 撷 captures the display screen by the screen balancer 2〇4 to drive the display 14 1344106 « Display device 108. The second display controller 106 can perform at least one operation calculation on the display screen, for example, adjusting the frequency of the output face, performing color swizzling, and An operation such as anti-aliasing is used to refresh the display device 108. However, according to another embodiment of the present invention, the second display controller 106 may not record the display screen to the picture buffer 204. Performing at least one operation calculation on the display screen, for example, adjusting the frequency of the output face, performing color swizzling, anti-aliasing, etc., and using To refresh the display device 108. Referring to FIG. 4A, in step 402, the first display controller 104 is responsible for driving the display device 108 to display an image; and step 404 is to determine whether a new display surface is written to the image buffer. If the picture buffer 202 is continuously written into the new display screen, the first display controller 104 is responsible for driving the display device 108 to display the image according to step 402; conversely, if there is no new display When the buffer buffer 202 is written, step 406 is performed to set the first terminal 210 of the second display controller 106 to a low state; then, in step 408, a new display screen is written. The screen buffer 204 is inserted; as described below, the second display controller 106 performs a display load cycle at the trailing edge of the vertical sync pulse (V-Sync pulse). The display load cycle That is, the step of writing a new display face to the face buffer 204, the write operation starts at the trailing edge of a vertical sync pulse (V-Sync pulse) and is next to the vertical sync pulse ( V-Sync pulse) The trailing edge of the vertical sync pulse 1344106 (V-Sync pulse) refers to the terminal that displays the picture in the display and the beginning of a new display picture; that is, the second display controller 1〇6 will Starting from the first scan line, recording pixd data to the trailing edge of a vertical sync pulse (V-Syncpuhe), and the trailing edge of the vertical sync pulse (V-Sync puise) or the second display control The timing of the output display screen of the device 1〇6 is input by the processor to the second display controller 106 through the second terminal 212, and the second terminal 212 starts from the first scan line to a vertical sync pulse (V-Sync). The trailing edge of pulse) is kept in a low state. The second terminal 212 is maintained in a high state during a vertical blanking period. The processor 丨〇2 synchronizes the control rights between the first display controller 1〇4 and the second display controller by using the state of the second terminal 2]2, when a complete The picture is written to the second A picture buffer S 204 'the second display controller is executed to switch control back to the second display controller 1 6 itself. In step 410, the second display controller 106 determines the timing of the plurality of _th display control nm as the timing of the plurality of third display controllers 〇6. According to the present invention, the above-mentioned conversion action is immediately followed by The trailing edge of the vertical sync pulse (V-Sync puise), that is, the time between the start of the vertical sync pulse called c Ρ·) and the end of the vertical blanking period. In addition, the first display controller (10) can also switch the clock generated by the clock generator to the clock generated by the clock generation ϋ2〇8, and the clock generator 2〇6 and the track I have a phase _ Solution, but the clock generator is not synchronized with the clock benefit 206. However, the function of first outputting (Fim in First 16 M44106 FIF〇) can be used to correct the timing of the display surface input by the first display controller 104 to the display controller 106 and the second display. The timing of state 106 is matched. However, in another embodiment of the present invention, the timing of the first display controller 104 and the timing of the second display controller 1〇6 are respectively in a blanking interval of a horizontal synchronization pulse (H-Sync pulse). Modulation is performed, and the synchronization of the picture can be achieved by phase-locked back (Phase Locked Loop, PLL) and thus can be displayed continuously. In step 412, the second display control n 1Q6 will control the plurality of registers in the first display f and the second display control. . A plurality of registers in 106 are reset to (9). In the step "the first display controller i 〇 6 switches the buffer 2 (10) from the input 2 to the read mode. In the embodiment of the present invention, the switching phase modulation is performed simultaneously. That is, the adjustment of the image timing is completed: 2, the controller 1〇6 uses the buffers and the clock generator to cry an image wheel. The image output includes the player's face extracted from the screen buffer. The display surface can be obtained by operation calculation ^anlpu^_s) or completely without operation calculation (_咖_二^ and °Xuanxian does not control the switching of the device 108, the above temporary storage: clock generator ~ under At the beginning of a line start, in step 416, the controller ΚΗ switches to the control device: the control device is controlled by the first display controller 丨〇6 from the bottom! The second display controller 106' and the second display The beginning of the control scan line begins to refresh the face of the display device 1344, 106, and the second display controller 1 6 independently refreshes the display according to the display of the face buffer 204. The screen of the device 1〇8; in step 418, the 5H processing & 1〇2 and the first display control stomach are switched Inactive mode; conversely, in another embodiment of the present invention, the first display controller! 〇4 is switched to the idle mode (i cafe mode), but the processor! 02 is held in one The startup mode (10) ve is out (4), and when the second display controller 1〇6 refreshes the display device (10) to the number of times using the same display screen, the second display controller: 〇6 can be switched to the idle mode. (inactive m〇de); and the predetermined number of times is stored in the temporary register of the second display controller 1〇6. The fifth figure shows that the control right of the display device 1〇8 is controlled by the second benefit. 6 is a flow chart of the method of switching to the first display controller. At S = 〇:, the display device (10) is responsible for 2 new by the second display controller ι 6 . Step 504, then _ whether there is a new display The face is written to the face buffer 202; if not (N〇), then return to step 5〇2, the second display controller is responsible for refreshing the display device 1〇8; conversely (10) =^ enter the step The first terminal (10) is set in a high state, and the state will be θε _ ^ white I The controller (10) is located in the high-energy write state of the model, and the display controller 106 stores the display buffer in the picture buffer 202 in the picture buffer 204. ' ' In step 508, the second display controller touches the timing plate of the controller 104 to perform the first _g., and the shoulder does not change; at the same time, the first:==the factory controller 1〇6 adjusts the first display between the timings. The controller 106 performs the modulation of the clock generators 18 1344106 and 208. In one embodiment of the invention, the modulation is performed immediately after the trailing edge of a vertical sync pulse (V-Sync pulse); In another embodiment, the modulation is performed during a blanking interval of a horizontal sync pulse (H_Syncpulse).

當第一顯示控制器】04在一低階狀態（1〇w state)，該等時脈產生β 206 ’影像時序和該第一顯示控制器刚所包含之該等暫存器（register)會被該處理器1〇2重新初始化 (re-initialized) ’且同時該處理器M 〇2也會同步地將該等時脈產生器206與綱重新初始化。根據本發明的另一實施例。亥等時脈產生益· 2〇6,影像時序和該第一顯示控制器 ι〇4所包含之該等暫存器（register)會由一第三端子川所輸入的中斷(interrupt)而重新初始化，該第三端子214可在一預定掃聪線開始時執行中斷’且該第二顯示控制器】〇6 = =根據中斷的種類執行複數個功能，該中斷的疋错由一第四端子216指示該處理器102。而據本發明的再一實施例，該第二顯 x 子指示該中斷的種類。而在⑽疋透過複數個端始化後，該㈣示控;;咖在步㈣。，該二;置二會執行剩 1Λ.，、置08之控制權被切換到該第處==接著該第一顯示控制陶根據該為102寫入遠畫面緩衝器2〇2 接下來’:：線:該= 生器寫就可產生影二:存难gister)與該等時脈產 19 !3441〇6 弟六圖為將該第二顯示控制器1〇6自閒置模式 (_twe _de)啟動之方法流程圖。在步驟_，㈣二顯示控制器1G6保持在-閒置模式（inaetivemQde);步驟When the first display controller 04 is in a low-order state (1〇w state), the clocks generate β 206 'image timing and the register that the first display controller has just included The processor 1 〇 2 is re-initialized 'and at the same time the processor M 〇 2 also reinitializes the clock generators 206 and the clusters synchronously. According to another embodiment of the invention. The clock is generated by the clock, and the image sequence and the register included in the first display controller ι4 are re-interrupted by an interrupt input by a third terminal. Initialization, the third terminal 214 can perform an interrupt at the beginning of a predetermined sweep line and the second display controller 〇6 == performs a plurality of functions according to the type of the interrupt, the error of the interrupt is determined by a fourth terminal 216 indicates the processor 102. According to still another embodiment of the present invention, the second display x indicates the type of the interrupt. And after (10) 疋 through a plurality of initializations, the (4) is controlled; the coffee is in step (4). , the second; the second will execute the remaining 1 Λ., the control of the set 08 is switched to the first place == then the first display control tao according to the write 102 to the far picture buffer 2 〇 2 Next ': : Line: The = burner can produce shadow 2: save the gister) and the clock production 19!3441〇6 brother six figure is the second display controller 1〇6 from idle mode (_twe _de) Flow chart of the method of starting. In step _, (4) two, the controller 1G6 is kept in the idle mode (inaetivemQde);

刚，則會偵測該處理器⑽是否自—輪人裝置接收一輸入訊號，例如-鍵盤、-觸控板、一*線觸發事件(⑽〇、一游標控制板或一滑鼠；若該處理器1〇2没有自一輸入裝置接收一輸入訊號(No)，則回到步驟6〇2，即該第二顯^ ，制為106保持在一閒置模式（—_和广而若該處理裔102自一輸入裝置接收—輸入訊號(Yes)，則進入步驟 606’-第五端子會被該處理器1〇2㉗定為_高階狀態（_ state)並將該第二顯示控制器1〇6由閒置模式加⑽丨… mode)轉成啟動模式（activemode);當第五端子設定在一高階狀態（high state)且該第二顯示控制器106處於啟動模式 (active mode)，第二顯示控制器1〇6就會將顯示計時終止暫存器（display timeout register)重置，該顯示計時終止暫存斋儲存s玄第一顯示控制器1 〇6可刷新一顯示畫面的時間值，而在該時間值過後，該第二顯示控制器1〇6會切換^ 間置模式（inactive mode);而根據本發明之另一實施方式，當該處理器102自一輸入裝置接收一輸入訊號，該處理器 102内建的軟體即會將驅使該第二顯示控制器1〇6從閒置模式（inactive mode)啟動。步驟608 ’則會偵測該處理器】〇2是否將一新的顯示畫面更新該晝面緩衝器202 ;若無（No)，則進入步驟614 : #亥第二顯示控制器106僅根據該晝面緩衝器204所儲存之 20 1344106 零》顯不晝面開始進行更新該顯示裝置】4 卜顯示控制$ 1G6以重置，右有，則該第二 m知暫存器⑽咖blankingImmediately, it will detect whether the processor (10) receives an input signal from the wheel device, such as a keyboard, a touchpad, a *line trigger event ((10)〇, a cursor control panel or a mouse; The processor 1〇2 does not receive an input signal (No) from an input device, and returns to step 6〇2, that is, the second display is maintained in an idle mode (__ and wide). 102 receives an input signal from an input device (Yes), then proceeds to step 606'-the fifth terminal is determined by the processor 1 227 as a _high state (_state) and the second display controller is 〇 6 is changed from the idle mode to (10) 丨 ... mode) to the active mode (active mode); when the fifth terminal is set to a high state and the second display controller 106 is in the active mode, the second display The controller 1〇6 will reset the display timeout register, and the display timing terminates the temporary storage. The first display controller 1 〇6 can refresh the time value of a display screen, and After the time value has elapsed, the second display controller 1〇6 switches the inter-mode In another mode, in accordance with another embodiment of the present invention, when the processor 102 receives an input signal from an input device, the software built into the processor 102 drives the second display controller. 6 is initiated from the inactive mode. Step 608 'detects the processor 〇 2 whether to update a new display screen to the buffer buffer 202; if not (No), then proceeds to step 614: # The second display controller 106 starts to update the display device according to the 20 1344106 zero stored in the buffer buffer 204. 4 display control $1G6 to reset, right, then the second m know the register (10) coffee blanking

不暫存器動作的情況下，該第二制11106會驅使該顯示裝置⑽顯示Μ書面而 ^ = 3示暫存器則可使該顯示裝置⑽恢復正常的第。"^驟_的結果為是（Yes)則進入步驟610，該子Μ:會執行—中斷而使該第二顯*控制11 106執 :一』不循環(display iGad cyele)，而後進人步驟612，該 =顯示控制器觸執行一顯示循環(dis㈣一 eyde); :在步驟_614該第二顯示控制器⑽獨立地驅動該顯示 :1〇8顯示畫面。而針對本方法驅動顯示裝m乂及系統中7L件狀態與時間的關係，將於以下第七到第九圖做更詳細的說明。 “第七圓為本發明之一實施例中，該顯示裝置1〇8的控制權由該第一顯示控制器104切換至第二顯示控制器】恥對應於時間變化的關係圖，該圖顯示在一垂直遮沒期間 (vertical blanking interval)該顯示裝置1〇8的控制權之切換’而此圖也進一步顯示此顯示系統2〇〇中不同元件，包括第一顯示控制器104、第二顯示控制器106、畫面緩衝器 2〇4、時脈產生器2〇6、第一端子2〗〇及第二端子212的狀蟋（staie)與時間的關係，·在第七圖t，X軸表示時間的變化’ Y軸則是各元件的狀態。 1344106 第八圖為本發明之一實施例中，該顯示裝置ι〇8的护制權由第二顯示控制器106切換至第一顯示控制哭1〇4$ 應於時間變化的關係圖，該圖顯示在一垂直遮沒期間 (vertical blanking interval)該顯示裝置 1〇8 的控制二之二換，而此圖也進一步顯示此顯示系統2〇〇中不^元件，包括第一顯示控制器104、第二顯示控制器1〇6、時脈產生^ 2〇6、第一端子210、第二端子212及第三端子214的狀: (办㈨與時間的關係·，在第八圖中，χ軸表示時間的變化二 Υ軸則是各元件的狀態。第九圖顯示本發明之-實施例中將第二顯示控制器 ⑽由閒置模式(inactive m〇de)起始㈣與時間的關係:而此圖也進-步顯示此顯示系統細中不同元件，包括第-顯不控制器104、第二顯示控制器·、畫面緩衝哭 2〇2、晝面缓衝器綱、第三端？214及第五端？ 218的二態（她)與時間的關係；在第九圖中，Μ表示時間的變化’ Υ軸則是各元件的狀態。而舉例來说，顯示控制器可由一（ASIC)、可程式化之邏輯控制器或一可攜裝置加以實現。而為了加以解釋’在此將對本發明的實現（帛二顯示控制器106)做-詳細的說明，包括硬體，如處理器、積體電路，子及暫存裔的設定。以下的設定將可讓熟知此技藝之人員貫現本發明之技術。第二顯示控制器】〇6之暫存器設定： 22 ^44106 暫存器種類索引碼預設值第二顯示控制器106之識別與校對 0 dcoih 第二顯示控制器106之顯示模式 1 0012H 水平解析度(Horizontal Resolution) 2 0458H (1200 Decimal) 水平總數目（Horizontal Total) 3 04E8H (1256 Decimal) 水平同步(Horizontal Sync) 4 1808H (24，8 Decimal) 垂直解析度(Vertical Resolution) 5 0340H (900 Decimal) 垂直總數目(Vertical Total) 6 0390H (912 Decimal) 水平同步(Vertical Sync) 7 0403H (4，3 Decimal) 顯示計時停止(Display Timeout) 8 FFFFH 掃猫中斷(Scanline Interrupt) 9 0000H 背光免Brightness) 10 XXXFH 預留(Reserved) 11-127 第二顯示控制器106之使用者輸入輪出（1/〇)端子定義：第二顯示控制器106之特殊應用電路(ASIC)輸出端子 -lM(512Kx 16) 同步動態隨機存取記憶體(SDRAM)之組態 Geode顯示介面端子 Geode 畫素時脈(Pixei clock) GFDOTCLK 1 Geode 红色資料(Red Data) GFRDAT0-5 6 Geode 綠色資料(Green Data) GFGDATO-6 7 Geode 藍色資料(Blue Data) GFBDAT0-5 6 23 1344106 ' V ·In the case of a non-register operation, the second system 11106 will drive the display device (10) to display the file and the display device (10) will return to the normal state. If the result of "^ _ is yes, then go to step 610, the sub-Μ: will execute - interrupt and make the second display * control 11 106: one does not loop (display iGad cyele), and then enter the person Step 612, the = display controller touches a display cycle (dis (four) - eyde); at step _614 the second display controller (10) independently drives the display: 1 〇 8 display screen. For the method of driving the display device and the relationship between the state and time of the 7L device in the system, the seventh to ninth drawings will be described in more detail below. "The seventh circle is an embodiment of the present invention, the control right of the display device 1 由 8 is switched by the first display controller 104 to the second display controller] shame corresponds to a time change relationship diagram, the figure shows Switching of control of the display device 1〇8 during a vertical blanking interval. The figure further shows different components in the display system 2, including the first display controller 104, the second display. The relationship between the controller 106, the picture buffer 2〇4, the clock generator 2〇6, the first terminal 2 and the second terminal 212, and the time, in the seventh figure t, the X-axis Representing the change of time 'Y axis is the state of each component. 1344106 The eighth figure is an embodiment of the present invention, the protection right of the display device ι 8 is switched by the second display controller 106 to the first display control Cry 1〇4$ should be a time-varying relationship diagram showing the control of the display device 1〇8 in a vertical blanking interval, and this figure further shows the display system 2不中不^Component, including the first display The controller 104, the second display controller 1〇6, the clock generation ^2〇6, the first terminal 210, the second terminal 212, and the third terminal 214 are in the form of: (9) and time relationship, in the eighth In the figure, the χ axis represents the change of time, and the Υ axis is the state of each component. The ninth figure shows that the second display controller (10) of the present invention is started by the idle mode (in) The relationship of time: This figure also shows the different components of this display system, including the first-display controller 104, the second display controller, the picture buffer cry 2, 2, the buffer buffer, The third state? 214 and the fifth end? 218 two states (her) relationship with time; in the ninth figure, Μ represents the change of time 'Υ axis is the state of each component. For example, display control The device may be implemented by an (ASIC), programmable logic controller or a portable device. For purposes of explanation, 'the implementation of the present invention (second display controller 106) will be described in detail, including hard Body, such as processor, integrated circuit, sub- and temporary settings. The following settings will allow The person skilled in the art can realize the technology of the present invention. The second display controller 〇6 register setting: 22 ^ 44106 register type index code preset value second display controller 106 identification and proofreading 0 dcoih Display mode of the second display controller 106 1 0012H Horizontal Resolution 2 0458H (1200 Decimal) Horizontal Total 3 04E8H (1256 Decimal) Horizontal Sync 4 1808H (24,8 Decimal ) Vertical Resolution 5 0340H (900 Decimal) Vertical Total 6 0390H (912 Decimal) Horizontal Sync 7 0403H (4,3 Decimal) Display Timeout 8 FFFFH Scanline Interrupt 9 0000H backlight-free brightness 10 XXXFH Reserved 11-127 User input wheel-out (1/〇) terminal definition of the second display controller 106: Second display controller 106 Special Application Circuit (ASIC) Output Terminal - lM (512Kx 16) Synchronous Dynamic Random Access Memory (SDRAM) Configuration Geode Display Interface Terminal Geode Pixel Clock (Pixei clo Ck) GFDOTCLK 1 Geode Red Data GFRDAT0-5 6 Geode Green Data GFGDATO-6 7 Geode Blue Data GFBDAT0-5 6 23 1344106 'V ·

Geode垂直同步(VSync) GFVSYNC 1 Geode水平同步(HSync) GFHSYNC 1 Geode FP_LDE GFP一LDE 1 5]2Kxl6 SDRAM之介面端子 FBRAM Data FBD0-15 16 FBRAM Address FBDA0-10 11 FB Column Addr Strobe FBCAS/ 1 FB Row Addr Strobe FBRAS/ 1 FB Data Masks FBDM0-1 2 FBRAM Chip Select FBCS/ 1 FBRAM Write Enable FBWE/ 1 FBRAM Clock FBCLK 1 FBRAM Clock Enable FBCLKE 1 Crystal for secondary display controller 106 Self-Refresh Display XTAL In DCONXI 1 Display XTAL Out DCONXO 1 系統介面端子(System Interface Pins) 系統重置(System Reset) RESET 1 EC Power On Request ECPWRRQST 1 第二顯示控制器106中斷輸出 (Interrupt Output) DCONIRQ/ 1 第二顯示控制器106顯示載入命令要求（Load Command Request) DCONLOAD 1 第二顯示控制器106狀態端子 (Status Pins) DCONSTAT 2 第二顯示控制器1 06隱沒狀態 (Blanking Status) DCONBLNK 1 24 1344106 » * ·Geode Vertical Synchronization (VSync) GFVSYNC 1 Geode Horizontal Synchronization (HSync) GFHSYNC 1 Geode FP_LDE GFP-LDE 1 5] 2Kxl6 SDRAM Interface Terminal FBRAM Data FBD0-15 16 FBRAM Address FBDA0-10 11 FB Column Addr Strobe FBCAS/ 1 FB Row Addr Strobe FBRAS/ 1 FB Data Masks FBDM0-1 2 FBRAM Chip Select FBCS/ 1 FBRAM Write Enable FBWE/ 1 FBRAM Clock FBCLK 1 FBRAM Clock Enable FBCLKE 1 Crystal for secondary display controller 106 Self-Refresh Display XTAL In DCONXI 1 Display XTAL Out DCONXO 1 System Interface Pins System Reset RESET 1 EC Power On Request ECPWRRQST 1 Second Display Controller 106 Interrupt Output DCONIRQ/ 1 The second display controller 106 displays the load command Load Command Request DCONLOAD 1 Second Display Controller 106 Status Pins DCONSTAT 2 Second Display Controller 1 06 Blanking Status DCONBLNK 1 24 1344106 » *

secondary display controller 106 Register I/O SMB Clock DCONSMBCLK 1 secondary display controller 106 Register I/O SMB Data DCONSMBDATA 1 DETTL / Panel Interface Pins Panel Pixel Data 0 DOOO-DOOl 3 Panel Pixel Data 1 DO10-DO11 3 Panel Pixel Data 2 DO20-DO21 3 Source Dot Clock SCLK 1 Data Interface Polarity Control REV 1-2 2 Graphics Output Enable (Gate driver enable) GOE 1 - INV 1 - CPV 1 - STV 1 - FSTH 1 - BSTH 1 - TP 1 LCD Backlight Enable BACKLIGHT 1 Display Backlight Control (PWM) DBC 1 Driver Polarity Signal 1 POL1 1 LCD VDD Enable VDDEN 1 Bum-In / Test Mode AGMODE 1 Color / Monochrome Panel Bias Select COLMODE 1 Total User I/Os 94 而ECPWRRQST啟動的最小循環時間約小於]00 nS。上述本發明所提出之實施例係針對一顯示系統，其包 25 含顯示裝置、處理器、笸— 書面综徐μ β不控制器、第二顯示控制器、 Μ控制器與第二顯示控制器所包含的才义、.$ ’此外’第二顯示㈣ϋ設有複數個端子。Secondary display controller 106 Register I/O SMB Clock DCONSMBCLK 1 secondary display controller 106 Register I/O SMB Data DCONSMBDATA 1 DETTL / Panel Interface Pins Panel Pixel Data 0 DOOO-DOOl 3 Panel Pixel Data 1 DO10-DO11 3 Panel Pixel Data 2 DO20 -DO21 3 Source Dot Clock SCLK 1 Data Interface Polarity Control REV 1-2 2 Graphics Output Enable (Gate driver enable) GOE 1 - INV 1 - CPV 1 - STV 1 - FSTH 1 - BSTH 1 - TP 1 LCD Backlight Enable BACKLIGHT 1 Display Backlight Control (PWM) DBC 1 Driver Polarity Signal 1 POL1 1 LCD VDD Enable VDDEN 1 Bum-In / Test Mode AGMODE 1 Color / Monochrome Panel Bias Select COLMODE 1 Total User I/Os 94 and the minimum cycle time for ECPWRRQST startup is less than approximately ]00 nS. The embodiment of the present invention described above is directed to a display system, and the package 25 includes a display device, a processor, a 笸-writing system, a second display controller, a Μ controller, and a second display controller. The included meaning, .$ 'in addition' the second display (four) ϋ has a plurality of terminals.

马待私述本&月所提出之實施例係提出—方法達成無失真 :制：顯不’畫面會在該第一顯示控制器與第二顯： ==調變之後由該顯示裝置所輸出，此調變是緊跟The embodiment proposed by the horse is described in the method of the present invention. The method achieves no distortion: the system: the display is displayed by the display device after the first display controller and the second display: == modulation Output, this modulation is followed by

者^同步脈衝的後緣進行，也就是垂直敍期間订以確保無失真的輸出。退土第二顯示控制器可單獨的刷新該顯示裝置，而不需要顯不控制器或處理器，因此該顯示器不需要處理态做連續性的運算。第-及第二顯示控制器以及該顯示裝置在一延長的閒置下可被Μ ’因此本系統可節省大量的能源。上述本發明所提出之實施例提出不需要昂貴且複雜之硬體而更適用於價格導向或能源消耗導向之各種應用。The trailing edge of the sync pulse is performed, that is, the vertical period is set to ensure a distortion-free output. The second display controller can refresh the display device separately without the need to display a controller or a processor, so the display does not require a processing state for continuous operation. The first and second display controllers and the display device can be smashed under an extended period of time. Therefore, the system can save a lot of energy. The above-described embodiments of the present invention propose various applications that do not require expensive and complicated hardware and are more suitable for price-oriented or energy-consuming guidance.

_准，以上所述，僅為本發明最佳之一的具體實施例之詳細5兄明與圖式，惟本發明之特徵並不祕於此，並非用以限制本發明’本發明之所有範圍應以下述之中請專利範圍為準，凡合於本發明申請專利範圍之精神與其類似變化 ^實施例’皆應包含於本發明之㈣中，任何熟悉該項技 2者在本發明之領域内，可輕易思及之變化或修飾皆可涵盖在以下本案之專利範圍。 26 1344106 【圖式簡單說明】 =一圖係本發明實施例之全系統之示意圖；第二圖係本發明實施例之顯示系統之示意圖；第三圖係本發明實施例顯示㈣之驅動顯程圖；衣置之"丨匕 :四A及四B圖係本發明實施例顯示系統之切換顯示裝置控制權之流程圖；The above description is only a detailed description of the specific embodiments of the present invention, but the features of the present invention are not intended to limit the present invention. The scope of the patent application is subject to the following patents, and the spirit of the scope of the patent application of the present invention and its similar variations are to be included in the fourth aspect of the present invention, and any one skilled in the art is in the present invention. Changes or modifications that can be easily considered in the field can be covered in the scope of the patents in this case below. 26 1344106 [Simplified description of the drawings] = a schematic diagram of the whole system of the embodiment of the invention; the second diagram is a schematic diagram of the display system of the embodiment of the invention; the third diagram shows the driving display of the embodiment of the invention (4) Figure of the present invention, a fourth embodiment of the present invention, a flowchart of the control of the switching display device of the display system;

第五圖係本發明實施例顯示系統之⑽顯示裝置控制權之流程圖；弟六圖係本發明實施例顯示系統之啟動第The fifth figure is a flowchart of the control function of the display device of the display system of the embodiment of the present invention; the sixth figure is the startup of the display system of the embodiment of the present invention.

器之流程圖； J 第七圖係為本發明貫施例顯示系統之切換顯示裝置控制權對應時間變化之關係圖；第八圖係為本發明實施例顯示系統之切換顯示裝置控制權對應時間變化之關係圖；以及The seventh diagram is a relationship diagram of the control time corresponding to the control of the switching display device of the display system of the present invention; the eighth figure is the control time corresponding to the control of the switching display device of the display system according to the embodiment of the present invention Diagram of change; and

第^圖係為本發明實施觸示系統之啟動第二顯示控制益對應時間變化之關係圖。 27 1344106 【主要元件符號說明】 100—全系統 102 —處理器 104—第一顯示控制器 106—第二顯示控制器 - 108—顯示裝置 200 -顯示系統 202-畫面緩衝器 • 204—晝面緩衝器 206—時脈產生器 208—時脈產生器 210—第一端子 212—第二端子 214—第三端子 216—第四端子 218 —第五端子 28The figure is a relationship diagram of the second display control control corresponding time change of the activation of the touch system of the present invention. 27 1344106 [Description of main component symbols] 100 - full system 102 - processor 104 - first display controller 106 - second display controller - 108 - display device 200 - display system 202 - picture buffer • 204 - face buffer 206 - clock generator 208 - clock generator 210 - first terminal 212 - second terminal 214 - third terminal 216 - fourth terminal 218 - fifth terminal 28

Claims

、申請專利範圍·· 99年】2月3曰修正替換頁 @種具有雙顯不控制器之顯示系統的驅動方法，其中該 :::系統包括一顯示裝置、一處理器、一第一顯示控制态一第二顯示控制器，該驅動方法包括：。亥第一顯示控制器自該處理器接收-顯示資料；換销不裝置之控制權於該第—顯示控制器及該第二 2控制器之間’且該切換是緊接著在垂直同步脈衝的後緣執行；以及 =第二顯示控卿刷新該顯示裝置，而不需依賴該第— 顯示控制器及該處理器。請專利範圍第1項所述之具有雙顯示控制器之顯示 :先的驅動方法’其中在該⑽該顯示裝置之控制權之二驟1括田/又有一新的顯不畫面伽㈣被寫入該第 —顯示控制器之-畫面緩衝器，則將該第二顯示控制器之—第一端子設定為一低階狀態之步驟。範圍第2項所述之具有雙顯示控制器之顯示系統的驅動方法’其中在將該第二顯示控制器之該第— 為-低階狀態之步驟，包括一執行一顯示循環 (jlay1〇adcycle)之步驟’且該執行一顯示循環之步驟匕括將-顯示畫面（frame)寫入該第二顯示控制器之—全面緩衝器之步驟，該寫入步驟是接著垂二 (V-Sync pulse)的後緣進行。乂氏衝 4 如申請專利範圍第i項所述之具有雙顯示㈣器之如 29 1344106 ， 99年12月3日修正替換頁系統的驅動方法，其中該切換該顯示裝置之控制權之步 ^ 驟’包括一當主少一新的顯示畫面（frame)被寫入該第一顯示控制器之一畫面緩衝器，則將該第二顯示控制器之一第一端子設定為一中間型之高階狀態 (intermediatehigh state)之步驟，其中該中間型之高階狀 ' 態為一中間型高耗能寫入狀態。 5、如申請專利範圍第1項所述之具有雙顯示控制器之顯示系統的驅動方法，其中έ亥切換該顯示裝置之控制權之步鲁驟，包括一將泫第一顯示控制器之至少一個影像時序 (video timing)與6玄第一顯示控制器之至少一個影像時序 (video timing)之間的調變步驟。 6、如申請專利範圍第5項所述之具有雙顯示控制器之顯示系統的驅動方法，其中該調變步驟，包括一同時將該第顯示控制器與έ玄第一顯示控制器之至少一個影像時序 (video timmg)再觸發（re-initia]izing)之步驟，且該等影像時序疋在一遮沒期間（blanking interval)同時被再觸發。攀7、如申請專利範圍第5項所述之具有雙顯示控制器之顯示，系統的驅動方法，其中該切換該顯示裝置之控制權之步驟進一步包括一將該第二顯示控制器之畫面暫存器由寫入(write)模式切換到讀取(read)模式之步驟。 8、如申請專利範圍第5項所述之具有雙顯示控制器之顯示系統的驅動方法’其中該切換賴示裝置之控制權之步驟進一步包括一將該第二顯示控制器之影像時序連接到該處理器之步驟，該步驟包括： 30 1344106 . 99年丨2月3日修正替換頁歧該第二顯示控制器之_第二端子為—低階狀態在一 ' 垂直同步脈衝(v_sync Pulse)之前之一預定時間點；以及設定該第二端子為一高階狀態在一遮沒期間(Manking interval)，其中該遮沒期間為一垂直同步脈衝（V-sync pulse)的後緣與一新開始之掃瞄線之間的時間區段。 ’’ 9、如申請專利範圍第5項所述之具有雙顯示控制器之顯示系統的驅動方法’其中該切換賴示裝置之控制權之步 ’驟it步包括-提供至少一種類型掃猫線中斷之步驟，其中每-類型的掃猫線中斷設有一對應於預定掃目苗線之時序二而每一類型的掃瞄線中斷由該第二顯示控制器之 -第三端子所提供，且該等掃瞒線中斷之種類則由該第二顯示控制器之至少一第四端子所指示。 10、如申請專利範圍第9項所述之具有雙顯示控制器之顯示糸統的驅動方法，其中該提供至少一種類型掃目运線中斷之步驟進一步包括-禁能dbling)該第一顯示控制器 # 之步驟’且該禁能步驟是基於該等掃猫線中斷的種類: .、如申請專利範圍第9項所述之具有雙顯示控制器之顯示，系、統的驅動方法’其中該提供至少-種類型掃吗線中斷之步驟進-步包括一通知(alerting)該處理器進行同再觸發該第-顯示控制H之至少—個影像時序與該^一顯讀制器之至少一個影像時序(vide〇 Um㈣之步 12再觸發步驟是基於該等掃㈣巾斷的種類而執行。 /申凊專利範圍第5項所述之具有雙顯示控制器_ 糸統的驅動方法，其中該切換該顯示裝置之控制權之步 31 99年12月3日修正替換頁、冑進一步包括一驅動該第二顯示控制器至-閒置模式之步驟，且戎步驟疋根據該第二顯示控制器之至少一暫存器之值（value)而執行。 .13、如申請專利範圍第】項所述之具有雙顯示控制器之顯示，糸統的驅動方法’其中該刷新顯示裝置之步驟進一步包括-啟動處於間置模式之該第二顯示控制器之步驟，且該第二顯示控制器會在該處理器接收到一由至少一個輸人裝置所輸人之輸人訊號的情況下被該處理器啟動。 14、如申請專利範圍第！項所述之具有雙顯示控制器之顯示糸統的驅動方法，其中該刷新顯示裝置之步驟進一括以下步驟：將》亥第一顯不控制器之一第五端子由一低階狀態調整為一高階狀態，當該處理器接收到—由至少—個輸入裝置所輸入之輸入訊號的情況下；以及啟動處於閒置模式之該第二顯示控制器。籲I5l申請專利範圍第1項所述之具有雙顯示控制器之顯示 • 糸統的驅動方法’其中該刷新顯示裝置之步驟包括命令，⑽manding)該第—顯示控制器啟動至少—影像輸出， V ί斤的顯不畫面被寫八該第一顯示控制器之畫面每衡器。 — 專利範圍第1項所述之具有雙顯示控制器之顯示、一、驅動方法’其中該刷新顯示裝置之步驟包括由該 f ^控制态獨立地（autonomously)驅動該顯示裝，虽沒有新的顯示畫面被寫入該第一顯示控制器之畫 32 1344106 _99年12月3曰修正替換頁面緩衝器。 17 種具有雙顯示控制器之顯示系統，係包括：一處理器； -第-顯示控制器’其與該處理器電性連接且接收該理器所輸出之訊號；以及一第二顯示控制器，其與該處理器電性連接，且與該第一顯示控制器切換該顯示裝置之控制權，且在二直同步脈衝的後緣；、任^ 其中當該顯示裝置之控制權切換至該第二顯示控制器 =，該第二顯示控制器刷新該顯示裝置，而不需依賴該第一顯示控制器及該處理器。 18 19 '如申請專利範㈣17項所述之具有雙顯示控制器之顯不系統’其中該第一顯示控制器與該第二顯示控制器分別包含至少-個影像時脈(vide〇 timing)，且該等影像時脈會在該顯示裝置之控龍⑽時同步被初始化。、如申：專利範圍第17項所述之具有雙顯示控制器之顯 :系統：其中該第二顯示控制器包括：第端子，其用以控制該顯示裝置的輸入端，且依據至少-個新的顯示晝面被寫入該第一顯示控制器之一書 ⑽衝進行設㈣第—端子之狀態(敝）；-端子’其用以控制該第二顯示控制器之顯示畫面時序，的及其用以提供至少一種掃謝斷(inte—〇 33 1344106 99年12月3日修正替換頁第四端子，其用以指示該第二顯示控制器所提供的掃猫線中斷（interrupt)之類型。 20、如申4專利乾圍g 19項所述之具有雙顯示控制器之顯不系統，該第二顯示控制器進一步包括一第五端子，其用以將該第二顯示控制器由閒置模式(inactive mode)轉成啟動模式（active mode)，當該處理器自至少一輸入裝置接收至少一輸入訊號。、 2卜如申請專利範圍第17項所述之具有雙顯示控制器之邊不系統’其中該第二顯示控制器包括—晝面緩衝器，言晝面緩衝器會在該第二顯示控制器之第一端子被設定4 一低階狀態（I°WState)的情況下，由寫入(write)模式切右到讀取(read)模式。 23 料鄉㈣17項所狀具錢顯邱制器之羅不系統’其中遠第二顯示控制器包括至少—個暫存塞 (egister) 4等暫存器與該第—顯示控制器之至少一値 2存器會在該顯示裝置的控制權由該第一顯示控制器^ 換到該第二顯示㈣器的情況下，时被初始化。 :種具有雙顯示控制器之顯示系統，其中該顯示系統包 =二員示裝置、一第一顯示控制器、一第二顯示控制器及一處理器，該系統包括：手段(meanS)’其用以將該第—顯示控制器的顯示為料傳輸到該第二顯示控制器； =奐手段(means)’其用以將該顯示裝置的控制權於該 ””頁不控制H與該第二顯示控制器之間切換’且該切 34 1344106 99年12月3曰修正替換頁換動作緊跟在-垂直同步脈衝(v_Syncpu㈣的後緣；以及一刷新手段(means)’其用以刷新該顯示裝置，且該顯示裝置由该第二顯示控制器所驅動而不需依賴該第一顯示控制器及該處理器。 24、二種具有雙顯示控制器之顯示系統的驅動方法，其包括機器可讀（machine-readable)儲存媒體，其包括至少一機态可執行（machine_executable)的指令程式以控制一顯示系統的一處理器，其中該顯示系統包括一顯示裝 f、-第-顯示控制器、一第二顯示控制器以及一處理器，該方法包括：接收顯示資料’其中該顯示資料係由該第—顯示控制器接收自該處理器；切換該顯示裝置之控制權於該第一顯示控制器及該第二顯示控制器之間，且該切換是緊接著在垂直同步脈衝 (V-Sync pulse)的後緣執行；以及刷新該顯示裝置’其中該顯示裝置由該第二顯示控制器所驅動’而不需依賴該第一顯示控制器及該處理器。 35Patent application scope · 99 years] February 3 曰 correction replacement page @ a display method with a display system with dual display controllers, wherein the ::: system includes a display device, a processor, a first display Control state - a second display controller, the driving method comprises: The first display controller receives the display data from the processor; the control of the replacement of the device is between the first display controller and the second controller 2 and the switching is followed by the vertical synchronization pulse The trailing edge executes; and = the second display controller refreshes the display device without relying on the first display controller and the processor. Please display the display with dual display controller as described in the first item of the patent scope: the first driving method 'where the control right of the display device in the (10) is one of the first steps / another new display picture gamma (four) is written Entering the first-display controller-picture buffer, the first terminal of the second display controller is set to a low-order state. The driving method of the display system with the dual display controller described in the second item, wherein the step of the second display controller is the first-lower state, including performing a display cycle (jlay1〇adcycle) And the step of executing a display loop includes the step of writing a - frame to the second display controller - a full buffer, the writing step is followed by a V-Sync pulse The trailing edge of the ).乂氏冲4 As described in the patent scope of item i, the double display (four) device, such as 29 1344106, the method of modifying the replacement page system on December 3, 1999, wherein the control of the display device is controlled ^ The step 'includes when a new frame of the main frame is written to the picture buffer of the first display controller, and sets the first terminal of one of the second display controllers to an intermediate type. The step of the intermediate high state, wherein the high-order state of the intermediate type is an intermediate high-energy write state. 5. The driving method of the display system with dual display controllers as claimed in claim 1, wherein the switching control of the display device is performed, including at least one of the first display controllers A modulation step between a video timing and at least one video timing of the 6th first display controller. 6. The driving method of a display system having a dual display controller according to claim 5, wherein the modulating step comprises at least one of simultaneously displaying the first display controller and the first display controller Video timmg re-initia immersing steps, and the image timings are re-triggered simultaneously during a blanking interval. The method of driving a system, wherein the step of controlling the control of the display device further comprises: temporarily The memory is switched from a write mode to a read mode. 8. The driving method of a display system having a dual display controller according to claim 5, wherein the step of controlling the control device further comprises connecting the image timing of the second display controller to The step of the processor, the step includes: 30 1344106. The correction of the replacement page is performed on the third page of the second display controller. The second terminal is a low-order state in a 'vertical sync pulse (v_sync Pulse). One of the previous predetermined time points; and setting the second terminal to a high-order state during a blanking interval, wherein the blanking period is a trailing edge of a vertical sync pulse (V-sync pulse) and a new start The time period between the scan lines. 9. The driving method of the display system with dual display controllers as described in claim 5, wherein the step of controlling the switching device comprises: providing at least one type of sweeping cat line a step of interrupting, wherein each type of sweeping cat line interrupt is provided with a timing 2 corresponding to a predetermined sweeping line and each type of scanning line interruption is provided by a third terminal of the second display controller, and The type of the broom line interruption is indicated by at least one fourth terminal of the second display controller. 10. The driving method of a display system having a dual display controller according to claim 9, wherein the step of providing at least one type of scanning line interruption further comprises: disabling dbling) the first display control The step of 'the step' and the disabling step is based on the type of the interrupting of the cat line: ., the display with the dual display controller as described in claim 9 of the patent application, the driving method of the system Providing at least one type of scan line interrupt step further comprises: aerating the processor to perform at least one image sequence with the re-triggering of the first display control H and at least one of the read and display controllers The image timing (vide〇Um(4) step 12 re-triggering step is performed based on the type of the sweeping (four) towel. / The driving method of the dual display controller _ 所述 system described in claim 5, wherein Step of switching control of the display device 31. The replacement page is modified on December 3, 1999, and further includes a step of driving the second display controller to the idle mode, and the step 疋 is based on the second display control Executing at least one value of the register. .13. The display having the dual display controller as described in the scope of the patent application, the driving method of the system, wherein the step of refreshing the display device further comprises - a step of initiating the second display controller in the inter-mode, and the second display controller is processed by the processor if the processor receives an input signal input by at least one of the input devices 14. The driving method of the display system with dual display controllers as described in the scope of claim 2, wherein the step of refreshing the display device further comprises the following steps: A fifth terminal is adjusted from a low-order state to a high-order state, when the processor receives an input signal input by at least one input device; and activates the second display controller in an idle mode. The method for driving a display with a dual display controller according to item 1 of the patent application of the first aspect of the invention, wherein the step of refreshing the display device includes the command ⑽manding) of the - display controller activating at least - a video output, V ί pounds was written eight picture is not the first picture of the display controller for each instrument. - The display having a dual display controller according to the first aspect of the patent, the driving method of the present invention, wherein the step of refreshing the display device comprises autonomously driving the display device by the f^ control state, although there is no new one The display screen is written to the first display controller's picture 32 1344106 _99 December 3 曰 corrected replacement page buffer. 17 display systems having dual display controllers, comprising: a processor; a first display controller that is electrically coupled to the processor and receives signals output by the processor; and a second display controller Connected to the processor, and switch control of the display device with the first display controller, and at the trailing edge of the two-way sync pulse; wherein, when the control of the display device is switched to the The second display controller=, the second display controller refreshes the display device without relying on the first display controller and the processor. 18 19 'A display system having a dual display controller as described in claim 17 (4), wherein the first display controller and the second display controller respectively include at least one video clock (vide〇timing), And the image clocks are synchronized in the control of the display device (10). The invention has the dual display controller as described in claim 17: the system: wherein the second display controller comprises: a terminal for controlling an input end of the display device, and according to at least one The new display surface is written into one of the first display controllers (10), and the fourth terminal is in a state (敝); the terminal is used to control the display timing of the second display controller. And for providing at least one type of sweeping fault (inte-〇33 1344106, December 3, 1999, the replacement page fourth terminal for indicating the interrupt of the sweeping cat line provided by the second display controller 20. A display system having a dual display controller as described in claim 4, wherein the second display controller further includes a fifth terminal for using the second display controller The inactive mode is changed to an active mode, and the processor receives at least one input signal from at least one input device. 2, as described in claim 17 of the patent having the dual display controller Not systematic The second display controller includes a buffer, and the buffer is written by the first buffer of the second display controller when the first terminal is set to a low-order state (I°WState). (write) mode cut right to read (read) mode. 23 material township (four) 17 items with the money show Qiuqiu system is not system 'the second remote display controller includes at least one temporary plug (egister) 4 At least one of the register and the first display controller may be initialized when the control of the display device is changed by the first display controller to the second display (four). A display system having a dual display controller, wherein the display system package includes a two-person display device, a first display controller, a second display controller, and a processor, the system comprising: means (meanS) Transmitting the display of the first display controller to the second display controller; = means "the means for controlling the display device to the "" page does not control H and the first Two display controllers switch between 'and the cut 34 1344106 99 December 3曰Correcting the replacement page changing action to follow the vertical sync pulse (the trailing edge of v_Syncpu (4); and a refreshing means for refreshing the display device, and the display device is driven by the second display controller without Relying on the first display controller and the processor. 24. A driving method for two display systems having dual display controllers, comprising a machine-readable storage medium comprising at least one state executable ( a processor_executable) program for controlling a processor of a display system, wherein the display system includes a display device, a display controller, a second display controller, and a processor, the method comprising: receiving display data ' wherein the display data is received by the first display controller from the processor; switching control of the display device between the first display controller and the second display controller, and the switching is followed by Performing a trailing edge of a vertical sync pulse (V-Sync pulse); and refreshing the display device 'where the display device is driven by the second display controller 'Without dependence of the first display controller and the processor. 35