1249197 九、發明說明： 【發明所屬之技術領域】 本發明係提供一種切割道結構，尤指一種利用虛設金 屬結構連接製程監測圖案並包含於複數層介電層之切割道 結構。 【先前技術】 積體電路的生產主要可區分為三個階段：1)晶片的製 造，2)積體電路的製作，以及3)積體電路的切割、電性測 試、篩選與封裝。當在晶片上製作積體電路時，整個晶片 係被均勻劃分為許多重複的晶粒（die)，相鄰的晶粒之間 則以切割道作為區隔。切割積體電路的步驟即是利用切割 機（cutter)沿著切割道將晶片切割為各別的晶粒。 近年來，伴隨高積集度半導體製程的進步，銅雙鑲嵌 (dual damascene )技術搭酉己低介電常數材料戶斤構成的金 屬間介電（inter metal dielectric)層已成為目前最 受矚目的金屬内連線技術。這是由於銅具有低電阻值，而 低介電常數材料則可幫助降低多層金屬導線中的RC延遲 (RC delay)效應。然而，為了達到低介電性質，低介電 常數材料多為組織鬆散，機械強度不理想之結構，所以具 有容易脆裂（fragile)的特性。因此，在使用刀具進行晶 1249197 粒切割時，外力將容易跨越材料之降伏強度，往往由於切 割側向應力產生晶片裂痕（chip cracking)。這種晶片 裂痕使得在後續的電性測試過程中，產生許多早夭產品 (infant mortality)，而降4氏良率。此夕卜，濕氣亦可能 在可靠度測試過程中沿著晶片裂痕進入積體電路中，造成 金屬導線的腐蝕，並導致電路故障。所以雷射切割技術廣 泛的被工業界所提出，所謂雷射切割是一種新的雷射加工 方式，主要是針對脆性薄片材料，利用雷射能量集中於切 割前緣，在局部區域產生極大的熱應力。由於切割前緣可 視為是裂痕的尖端，此熱應力將使切割前緣向前擴展，切 割件自動分開。它可以改善前述晶粒切割時，所造成晶片 裂痕現象。 請參考第1圖，第1圖為習知一切割道結構之上視圖， 切割道區域10之上下兩側為保護層12，用來保護切割道 區域10兩側的元件區域，而為了避免浪費晶圓上的有效利 用面積，至少一製程監控圖案14係位於切割道區域10 中，例如設置於低介常數之介電層16中。 請參考第2圖，第2圖為沿著第1圖所示切線n-rT 獲得之切割道結構剖視圖。如第2圖所示，晶圓切割道之 結構中，包含有一基底18，基底18上方有複數層低介電 常數的介電層 16a、16b、16c、16d、16e、16f’ 一製 1249197 程監測圖案！4設置於介電層心與咖之中。其中製程 監測圖案14可以是電性測試結構（test key)、特徵^ 寸（feature dimensi〇n)之量測元件以及元件對準標 記（山卯邮此啦叫等，且製程監測圖案Μ通常為^ 屬材料所構成。此外，最上方之介電層l6f表面上設有保 護層12覆蓋於切割道區域1〇兩侧。 由於金屬材料所構成的製程監測圖案相較於低介電常 數的複數層介電層材料更容易吸收雷射光束的能量，因此 當能量快速地累積於切割道中的金屬結構後，金屬結構可 能產生相變，㈣體轉換缝體或氣體，所以造成能量的 釋放過程不僅是由下而上，並從㈣***，亦造成晶片裂 痕，嚴重影響產品良率。 【發明内容】 本發明的主要目的在於提供一種切割道結構，以避免 於利用雷射切割技術來切割晶圓時產生晶片裂痕等問題。 根據本發明之目的，該切割道結構包含有一基底，複 數層介電層形成於基底表面，至少一製程監測圖案設於上 述介電層表面之一切割道區域中，以及一虛設金屬結構形 成於基底表面。製程監測圖案係為一複數層金屬結構，此 製程監測圖案與包含複數個虛設金屬層、複數個虛設通道 1249197 的虛設金屬結構相連接，且虛設金屬結構係暴露於切割道 區域中。 由於本發明係利用虛設金屬結構暴露於切割道區域 中’當使用雷射光束進行晶粒切割時’雷射光束的能量會 均勻的被此虛設金屬結構吸收，並有良好的散熱與能量釋 放系統’如此避免了因側向***產生晶片裂痕的、現^里r 提局積體電路晶片產能。 請參考第3圖’第3圖為本發明之第—實施例中的兮 割道結構剖視圖。如第3圖所示，此切割道纟士構底部為 基底33，基底33表面形成複數層介電層34、35 ' 3 7、38,介電層3P38中係部份為介電常數小於或等 之低介電常數介電層，部分由其他介電材料形成 電層34-38亦可以全部為低介電常數介電層。在最 介電層34表面上另設有一保護層31，且保護層= 有一開口，以用來定義一切割道區域3 〇。 保護層31係用來覆蓋切割道區域3〇兩側的元件區 域，且切割道區域30中包含有至少一由金屬材料所構成2 製程監測圖案32設置於介電層36與介電層37中。 監蜊圖案32可以是電性測試結構、特徵尺寸之量测元件& 1249197 元件對準標記或其他各種監測圖案等，且製程監測圖案3 2 之上方連接一虛設金屬結構4 1，此虛設金屬結構4 1可視 需要由不同尺寸與數目之虛設金屬層39與虛設金屬通道 4〇組成，且暴露於切割道區域30中。在本發明之較佳實 施例中，虛設金屬通道係串聯各虛設金屬層39以形成 一散熱結構，可使切割過程中或是其他熱製程中所產生之 熱量及能量有效的從切割道區域30表面被釋放，以保護晶 片上之半導體元件。然而在本發明之其他實施例中，虛設 金屬通道40亦可以直接貫穿介電層34、35並連接至製程 監測圖案32，省略虛設金屬層39的製作。此外，在本發 明之其他實施例中，虛設金屬結構41亦不限定僅能設置於 製程監測圖案32的上方，當切割道區域30内包含有兩個 或兩個以上的製程監測圖案32時，虛設金屬結構41亦可 以連接於這些製程監測圖案32之間，且最上方的虛設金屬 結構4 1應暴露於切割道區域3〇中。 請參考第4圖，第4圖為本發明之第二實施例中的切 割道結構剖視圖。本發明之第二實施例與上述第一實施例 不同的是，在本發明的第一實施例中，虛設金屬結構係形 成於製程監測圖案上方且暴露於切割道區域中，使熱量及 月匕里能有效的從切割道區域表面被釋放；而本發明之第二 實&例中的虛設金屬結構則係貫穿介電層直至基底表面， 連接製程監測圖案並暴露於切割道區域中，如此在進行晶 1249197 粒切割的製程中，更能均勻的吸收雷射光束的能量，且有 效的向上以及向下釋放切割過程中或是其他熱製程中所產 生的熱量及能量，以保護晶片上之半導體元件，以避免切 割時產生之侧向***造成晶片裂痕。 如第4圖所示，此切割道結構底部為一基底53，基底 53表面形成複數層介電層54、55、56、57、58、59， 介電層54-5 9中係部份為介電常數小於或等於3之低介電 常數介電層，部分由其他介電材料形成，或者介電層54-59 亦可以全部為低介電常數介電層。在最上方之介電層54 表面上另設有一保護層61，且保護層61包含有一開口， 以用來定義一切割道區域60。 保護層61係用來覆蓋切割道區域60兩侧的元件區 域，且切割道區域60中包含有至少一由金屬材料所構成之 製程監測圖案52設置於介電層56與介電層57中。製程 監測圖案52係與一虛設金屬結構62相連接形成一散熱與 釋放能量的通道，虛設金屬結構62可視需要由不同尺寸與 數目之虛設金屬層50與虛設金屬通道51組成，且形成於 基底53的表面並暴露於切割道區域60中，使切割過程中 或是其他熱製程中所產生之熱量及能量有效的從切割道區 域60表面或是基底53表面被釋放，以保護晶片上之半導 體元件。然而在本發明之其他實施例中，虛設金屬通道51 1249197 亦可以直接貫穿介電層54、55、57、58、59，並連接至 製程監測圖案52，省略虛設金屬層50的製作。 相較於習知技術，本發明之切割道結構係具有一虛設金 屬結構，在進行晶粒切割時，能有效的將能量與熱量從切 割道區域表面釋放，以避免切割時產生之側向***造成晶 片裂痕，進而改善產品的良率，並提高積體電路晶片產能。 以上所述僅本發明之較佳實施例，凡依本發明申請專利 範圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋範 圍。 【圖式簡單說明】 第1圖為習知一切割道結構之上視圖。 第2圖為沿著第1圖所示切線n-r/獲得之切割道結構剖視 圖。 第3圖為本發明之第一實施例中的切割道結構剖視圖。 第4圖為本發明之第二實施例中的切割道結構剖視圖。 【主要元件符號說明】 1〇、3〇、6〇切割道區域 12、31、61保護層 14、32、52製程監測圖案 11 1249197 16、16a- 16f、34-38、54-59 介電層 18、33、53 基底 39、50 虛設金屬層 4〇、51 虛設金屬通道 41 ^ 62 虛設金屬結構（散熱結構）1249197 IX. Description of the Invention: [Technical Field] The present invention provides a dicing structure, and more particularly to a dicing structure in which a process monitoring pattern is connected by a dummy metal structure and included in a plurality of dielectric layers. [Prior Art] The production of the integrated circuit can be mainly divided into three stages: 1) fabrication of the wafer, 2) fabrication of the integrated circuit, and 3) cutting, electrical testing, screening, and packaging of the integrated circuit. When an integrated circuit is fabricated on a wafer, the entire wafer is evenly divided into a plurality of repeating dies, and adjacent dies are separated by dicing streets. The step of cutting the integrated circuit is to cut the wafer into individual dies along the scribe line using a cutter. In recent years, with the advancement of high-accumulation semiconductor processes, the dual damascene technology has become the most eye-catching intermetal dielectric layer composed of low dielectric constant materials. Metal interconnect technology. This is because copper has a low resistance value, while low dielectric constant materials can help reduce the RC delay effect in multilayer metal wires. However, in order to achieve low dielectric properties, low dielectric constant materials are mostly loose in structure and unsatisfactory in mechanical strength, so they are easily fragile. Therefore, when using a tool for grain 1249197 grain cutting, the external force will easily cross the material's lodging strength, often resulting in chip cracking due to the cutting lateral stress. This wafer cracking resulted in many early mortality and a 4 percent yield during subsequent electrical testing. Furthermore, moisture may also enter the integrated circuit along the wafer crack during the reliability test, causing corrosion of the metal wires and causing circuit failure. Therefore, laser cutting technology has been widely proposed by the industry. The so-called laser cutting is a new laser processing method, mainly for brittle sheet materials, using laser energy concentrated on the cutting front, generating great heat in local areas. stress. Since the cutting leading edge can be considered as the tip of the crack, this thermal stress will cause the cutting leading edge to expand forward and the cutting members will automatically separate. It can improve the cracking of the wafer caused by the aforementioned grain cutting. Please refer to FIG. 1 , which is a top view of a conventional dicing structure. The upper and lower sides of the dicing area 10 are protective layers 12 for protecting the component areas on both sides of the dicing area 10, in order to avoid waste. The effective use area on the wafer, at least one process monitor pattern 14 is located in the scribe line region 10, such as in the low dielectric constant dielectric layer 16. Please refer to Fig. 2, which is a cross-sectional view of the dicing structure obtained along the tangent line n-rT shown in Fig. 1. As shown in FIG. 2, the structure of the wafer dicing street includes a substrate 18 having a plurality of dielectric layers 16a, 16b, 16c, 16d, 16e, 16f' having a low dielectric constant above the substrate 18. Monitor the pattern! 4 set in the dielectric layer and the coffee. The process monitoring pattern 14 may be an electrical test structure (test key), a feature dimensi〇n measurement component, and a component alignment mark (the mountain is called this, and the process monitoring pattern is usually ^ The material of the genus is composed of a material. Further, a protective layer 12 is provided on the surface of the uppermost dielectric layer l6f to cover both sides of the scribe line region. The process monitoring pattern formed by the metal material is compared with the plural of the low dielectric constant. The layer dielectric material absorbs the energy of the laser beam more easily, so when the energy rapidly accumulates in the metal structure in the scribe line, the metal structure may produce a phase change, and (4) the body converts the seam or gas, so the energy release process is not only It is bottom-up and explodes from (4), which also causes wafer cracks, which seriously affect product yield. SUMMARY OF THE INVENTION The main object of the present invention is to provide a dicing structure to avoid cutting wafers by laser cutting technology. When a problem such as a wafer crack occurs, the scribe line structure includes a substrate, and a plurality of dielectric layers are formed on the surface of the substrate to A process monitoring pattern is disposed in a scribe line region of the surface of the dielectric layer, and a dummy metal structure is formed on the surface of the substrate. The process monitoring pattern is a plurality of metal structures, and the process monitoring pattern includes a plurality of dummy metal layers a dummy metal structure of a plurality of dummy channels 1249197 is connected, and the dummy metal structure is exposed in the scribe line region. Since the present invention utilizes a dummy metal structure to be exposed in the scribe line region 'When using a laser beam for grain cutting 'The energy of the laser beam is uniformly absorbed by this dummy metal structure, and there is a good heat dissipation and energy release system'. This avoids the wafer chip cracking caused by the lateral explosion. Please refer to FIG. 3 'Fig. 3 is a cross-sectional view showing the structure of the cutting channel in the first embodiment of the present invention. As shown in Fig. 3, the base of the cutting channel is a base 33, and a plurality of layers are formed on the surface of the base 33. The electrical layer 34, 35' 37, 38, the dielectric layer 3P38 is a low dielectric constant dielectric layer having a dielectric constant less than or equal to that of the dielectric layer 3P38, and is partially composed of other dielectric layers. The material forming electrical layers 34-38 may also all be low dielectric constant dielectric layers. A protective layer 31 is additionally disposed on the surface of the most dielectric layer 34, and the protective layer = an opening for defining a dicing area 3 The protective layer 31 is used to cover the component regions on both sides of the dicing region 3, and the dicing region 30 includes at least one metal material. The process monitoring pattern 32 is disposed on the dielectric layer 36 and the dielectric layer. 37. The monitoring pattern 32 may be an electrical test structure, a feature size measuring component & 1249197 component alignment mark or other various monitoring patterns, and the like, and a dummy metal structure 4 1 is connected above the process monitoring pattern 3 2 . The dummy metal structure 4 1 may be composed of different sizes and numbers of dummy metal layers 39 and dummy metal channels 4 , and exposed to the scribe line region 30 . In a preferred embodiment of the present invention, the dummy metal vias are connected in series with each of the dummy metal layers 39 to form a heat dissipating structure, which can effectively generate heat and energy generated during the cutting process or other thermal processes from the scribe line region 30. The surface is released to protect the semiconductor components on the wafer. However, in other embodiments of the present invention, the dummy metal vias 40 may also directly penetrate the dielectric layers 34, 35 and be connected to the process monitor pattern 32, omitting the fabrication of the dummy metal layer 39. In addition, in other embodiments of the present invention, the dummy metal structure 41 is not limited to being disposed only above the process monitoring pattern 32. When the scribe line region 30 includes two or more process monitoring patterns 32, The dummy metal structure 41 may also be connected between the process monitoring patterns 32, and the uppermost dummy metal structure 41 should be exposed in the scribe line region 3A. Please refer to Fig. 4, which is a cross-sectional view showing the structure of the cutting path in the second embodiment of the present invention. The second embodiment of the present invention is different from the first embodiment described above in that, in the first embodiment of the present invention, the dummy metal structure is formed over the process monitoring pattern and exposed to the scribe line region to allow heat and the moon Effectively released from the surface of the scribe line region; and the dummy metal structure in the second embodiment of the present invention penetrates the dielectric layer up to the surface of the substrate, connecting the process monitoring pattern and exposing it to the scribe line region, In the process of crystal 1249197 grain cutting, the energy of the laser beam is more uniformly absorbed, and the heat and energy generated during the cutting process or other thermal processes are effectively released upward and downward to protect the wafer. Semiconductor components to avoid wafer cracks caused by lateral explosions during cutting. As shown in FIG. 4, the bottom of the dicing circuit structure is a substrate 53, and a plurality of dielectric layers 54, 55, 56, 57, 58, 59 are formed on the surface of the substrate 53, and the middle portion of the dielectric layer 54-5 9 is The low dielectric constant dielectric layer having a dielectric constant of less than or equal to 3 is partially formed of other dielectric materials, or the dielectric layers 54-59 may all be low dielectric constant dielectric layers. A protective layer 61 is further disposed on the surface of the uppermost dielectric layer 54, and the protective layer 61 includes an opening for defining a scribe line region 60. The protective layer 61 is used to cover the component regions on both sides of the dicing street region 60, and the dicing track region 60 includes at least one process monitoring pattern 52 made of a metal material disposed in the dielectric layer 56 and the dielectric layer 57. The process monitoring pattern 52 is connected to a dummy metal structure 62 to form a channel for dissipating heat and releasing energy. The dummy metal structure 62 may be composed of different sizes and numbers of dummy metal layers 50 and dummy metal channels 51, and formed on the substrate 53 as needed. The surface is exposed to the scribe line region 60, so that the heat and energy generated during the cutting process or other thermal processes are effectively released from the surface of the scribe line region 60 or the surface of the substrate 53 to protect the semiconductor components on the wafer. . However, in other embodiments of the present invention, the dummy metal vias 51 1249197 may also directly penetrate the dielectric layers 54, 55, 57, 58, 59 and be connected to the process monitor pattern 52, omitting the fabrication of the dummy metal layer 50. Compared with the prior art, the scribe line structure of the present invention has a dummy metal structure, and can effectively release energy and heat from the surface of the scribe line region during grain cutting to avoid lateral explosion during cutting. Causes wafer cracks, which in turn improves product yield and increases integrated circuit chip throughput. The above-mentioned preferred embodiments of the present invention are intended to be equivalent to variations and modifications of the scope of the present invention. [Simple Description of the Drawing] Fig. 1 is a top view of a conventional cutting path structure. Fig. 2 is a cross-sectional view showing the structure of the scribe line obtained along the tangent line n-r/ shown in Fig. 1. Figure 3 is a cross-sectional view showing the structure of a dicing street in the first embodiment of the present invention. Figure 4 is a cross-sectional view showing the structure of a dicing street in a second embodiment of the present invention. [Main component symbol description] 1〇, 3〇, 6〇 cutting path area 12, 31, 61 protective layer 14, 32, 52 process monitoring pattern 11 1249197 16, 16a-16f, 34-38, 54-59 dielectric layer 18, 33, 53 Substrate 39, 50 dummy metal layer 4〇, 51 dummy metal channel 41 ^ 62 dummy metal structure (heat dissipation structure)
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