TW202320079A - Semiconductor device including an electronic fuse control circuit and a method for fabricating the same - Google Patents

Semiconductor device including an electronic fuse control circuit and a method for fabricating the same Download PDF

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TW202320079A
TW202320079A TW111102419A TW111102419A TW202320079A TW 202320079 A TW202320079 A TW 202320079A TW 111102419 A TW111102419 A TW 111102419A TW 111102419 A TW111102419 A TW 111102419A TW 202320079 A TW202320079 A TW 202320079A
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terminal
voltage
fuse element
latch
coupled
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TW111102419A
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TWI817328B (en
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楊吳德
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南亞科技股份有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
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Abstract

The present application discloses an electronic fuse control circuit, a semiconductor device and a method for forming a semiconductor device including an electronic fuse control circuit. The electronic fuse control circuit includes a program voltage pad, a fuse element, a latch, an operation switch unit, resistor selection pads, and bonding option units. The fuse element includes a first terminal coupled to the program voltage pad, and a second terminal. The operation switch unit forms an electrical connection between the second terminal of the fuse element and a ground terminal during a program operation, and forms an electrical connection between the second terminal of the fuse element and an input terminal of the latch during a read operation. Each of the bonding option units includes a resistor and a selection switch coupled in series between the input terminal of the latch and a resistor selection pad.

Description

具有電子熔線控制電路的半導體元件及其製備方法Semiconductor element with electronic fuse control circuit and manufacturing method thereof

本申請案主張美國第17/517,525號及第17/517,794號專利申請案之優先權（即優先權日為「2021年11月2日」及「2021年11月3日」），其內容以全文引用之方式併入本文中。This application claims priority to U.S. Patent Application Nos. 17/517,525 and 17/517,794 (i.e., priority dates are "November 2, 2021" and "November 3, 2021"), the content of which is It is incorporated herein by reference in its entirety.

本揭露提供一種電子熔線控制電路及其製備方法，特別是關於一種提供不同接合選項的電子熔線控制電路及其製備方法。The disclosure provides an electronic fuse control circuit and a manufacturing method thereof, in particular, an electronic fuse control circuit providing different bonding options and a manufacturing method thereof.

反熔線器(antifuse)是電子熔線器元件(eFuse)的一種類型，並且已在一次性可編程(one-time programmable，OTP)非揮發性記憶體中獲得採用。圖1例示反熔線器AF1的結構。如圖1所示，反熔線器AF1的結構類似於電晶體的結構；反熔線器AF1包括閘極G1和主動區A1。在此情況下，由於閘極G1包括閘極氧化物，因此閘極G1和主動區A1之間具有相當高的電阻。然而，當編程電壓VH被施加到閘極G1上，而接地電壓被施加到主動區A1上時，施加到反熔線器元件AF1上的高電壓會破壞閘極G1的閘極氧化物，因而在閘極G1和主動區A1之間產生低電阻器路徑。因此，反熔線器元件AF1可被編程(programmed)。An antifuse is a type of electronic fuse element (eFuse) and has been adopted in one-time programmable (OTP) non-volatile memory. FIG. 1 illustrates the structure of the antifuse AF1. As shown in FIG. 1 , the structure of the antifuse AF1 is similar to that of a transistor; the antifuse AF1 includes a gate G1 and an active region A1 . In this case, since the gate G1 includes a gate oxide, there is a relatively high resistance between the gate G1 and the active region A1. However, when the programming voltage VH is applied to the gate G1 and the ground voltage is applied to the active area A1, the high voltage applied to the antifuse element AF1 destroys the gate oxide of the gate G1, thus A low resistance path is created between gate G1 and active area A1. Therefore, the antifuse element AF1 can be programmed.

由於在對反熔線器AF1執行編程操作時，反熔線器AF1的電阻值會發生很大的變化，因此系統可以藉由檢測反熔線器AF1的電阻值來識別反熔線器AF1是否已經被編程。例如，可以利用參考電阻器來與反熔線器AF1進行分壓，從而藉由產生的分配電壓來識別反熔線器AF1的狀態。然而，由於反熔線器在製備過程中的變異，不同反熔線的電阻值可能彼此不同。例如，在一般情況下，在對反熔線器執行編程操作之前，反熔線器的電阻值可能大於5000千歐姆(kΩ)，而在對反熔線執行編程操作之後，其電阻值可能小於400千歐姆。然而，在對反熔線執行編程操作之前，一些反熔線的電阻值可能小於1500千歐姆，而其他一些反熔線的電阻值甚至在對反熔線執行編程操作之後仍可能大於800千歐姆。在此情況下，為一個反熔線器所選定的參考電阻器就可能無法正確識別另一個反熔線器的狀態。在此情況下，就可能需要額外的製程來更換參考電阻器，因而造成成本增加，並使製備效率降低。Since the resistance value of the antifuse AF1 will change greatly when the programming operation is performed on the antifuse AF1, the system can identify whether the antifuse AF1 is has been programmed. For example, a reference resistor can be used to divide the voltage with the anti-fuse AF1 , so that the state of the anti-fuse AF1 can be identified through the generated divided voltage. However, due to variations in the fabrication process of antifuses, the resistance values of different antifuses may differ from each other. For example, in typical cases, an antifuse may have a resistance greater than 5000 kilo-ohms (kΩ) before programming and less than 5000 kΩ after programming. 400 kohms. However, some antifuses may have a resistance value less than 1500 kohms before the antifuse is programmed, while others may have a resistance greater than 800 kohms even after the antifuse is programmed . In this case, the reference resistor selected for one anti-fuse may not correctly identify the state of the other anti-fuse. In this case, an additional process may be required to replace the reference resistor, resulting in increased cost and reduced manufacturing efficiency.

上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不設置本揭露之先前技術，且上文之「先前技術」之任何說明均不應做為本案之任一部分。The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, does not set the prior art of this disclosure, and any description of the above "prior technology" shall not form any part of this case.

本揭露的一實施例提供一種電子熔線控制電路，包括：一編程電壓墊、一熔線器元件、一鎖存器、一操作開關單元、複數個電阻器選擇墊和複數個接合選項單元。該編程電壓墊經配置以接收該編程電壓。該熔線器元件包括與該編程電壓墊耦合的一第一端，和一第二端。該鎖存器包括一輸入端和一輸出端。該操作開關單元經配置以在一編程操作期間在該熔線器元件的該第二端和一接地端之間形成一電性連接，並經配置以在一讀取操作期間在該熔線器元件的該第二端和該鎖存器的該輸入端之間形成一電性連接。該複數個接合選項單元中的每一個都包括一電阻器和一選擇開關，串聯在該鎖存器的該輸入端和該複數個電阻器選擇墊中的一相應電阻器選擇墊之間。An embodiment of the present disclosure provides an electronic fuse control circuit, including: a programming voltage pad, a fuse element, a latch, an operation switch unit, a plurality of resistor selection pads and a plurality of bonding option units. The programming voltage pad is configured to receive the programming voltage. The fuse element includes a first terminal coupled to the programming voltage pad, and a second terminal. The latch includes an input terminal and an output terminal. The operation switch unit is configured to form an electrical connection between the second terminal of the fuse element and a ground terminal during a programming operation, and to establish an electrical connection between the fuse element during a read operation. An electrical connection is formed between the second end of the element and the input end of the latch. Each of the plurality of engagement option cells includes a resistor and a selection switch connected in series between the input terminal of the latch and a corresponding resistor selection pad of the plurality of resistor selection pads.

在一些實施例中，該熔線器元件是一反熔線器(antifuse)。In some embodiments, the fuse element is an antifuse.

在一些實施例中，該複數個接合選項單元的電阻器具有不同的電阻器。In some embodiments, the plurality of resistors engaging the option unit have different resistors.

在一些實施例中，該電子熔線控制電路更包括一讀取開關，該讀取開關包括與該熔線器元件的該第一端耦合的一第一端、與該接地端耦合的一第二端和經配置以接收一讀取控制訊號的一控制端。In some embodiments, the electronic fuse control circuit further includes a read switch, the read switch includes a first terminal coupled to the first terminal of the fuse element, a first terminal coupled to the ground terminal Two terminals and a control terminal configured to receive a read control signal.

在一些實施例中，該操作開關單元包括一第一開關、一第二開關和一第三開關。該第一開關包括與該熔線器元件的該第二端耦合的一第一端、第二端以及經配置以接收一讀取和編程控制訊號的一控制端。該第二開關包括與該第一開關的該第二端耦合的一第一端，與該接地端耦合的一第二端，以及經配置以接收一編程控制訊號的一控制端。該第三開關包括與該第一開關的該第二端耦合的一第一端，與該鎖存器的該輸入端耦合的一第二端，以及經配置以接收一讀取控制訊號的一控制端。In some embodiments, the operation switch unit includes a first switch, a second switch and a third switch. The first switch includes a first terminal coupled to the second terminal of the fuse element, a second terminal, and a control terminal configured to receive a read and program control signal. The second switch includes a first terminal coupled with the second terminal of the first switch, a second terminal coupled with the ground terminal, and a control terminal configured to receive a programming control signal. The third switch includes a first terminal coupled to the second terminal of the first switch, a second terminal coupled to the input terminal of the latch, and a configured to receive a read control signal Control terminal.

在一些實施例中，該鎖存器更包括一第一反相器和一第二反相器。該第一反相器包括與該鎖存器的該輸入端耦合的一輸入端，以及與該鎖存器的該輸出端耦合的一輸出端。該第二反相器包括與該鎖存器的該輸出端耦合的一輸入端，以及與該鎖存器的該輸入端耦合的一輸出端。In some embodiments, the latch further includes a first inverter and a second inverter. The first inverter includes an input coupled to the input of the latch, and an output coupled to the output of the latch. The second inverter includes an input coupled to the output of the latch, and an output coupled to the input of the latch.

在一些實施例中，該複數個電阻器選擇墊中的至少一個在該讀取操作期間接收一讀取電壓，其中該讀取電壓小於該編程電壓。In some embodiments, at least one of the plurality of resistor select pads receives a read voltage during the read operation, wherein the read voltage is less than the programming voltage.

本揭露的另一實施例提供一種半導體元件，包括：一晶片和一基底。該晶片包括一電子熔線控制電路，該電子熔線控制電路包括一編程電壓墊、一熔線器元件、一鎖存器、一操作開關單元、複數個電阻器選擇墊以及複數個接合選項單元。該編程電壓墊經配置以接收一編程電壓。該熔線器元件包括與該編程電壓墊耦合的一第一端，和一第二端。該鎖存器包括一輸入端和一輸出端。該操作開關單元經配置以在一編程操作期間在該熔線器元件的該第二端和一接地端之間形成一電性連接，並經配置以在一讀取操作期間在該熔線器元件的該第二端和該鎖存器的該輸入端之間形成一電性連接。該複數個接合選項單元中的每一個都包括一電阻器和一選擇開關，串聯在該鎖存器的該輸入端和該複數個電阻器選擇墊中的一相應電阻器選擇墊之間。該基底包括一第一電壓接合墊和複數個第二電壓接合墊。該第一電壓接合墊被接合到該編程電壓墊，該複數個第二電壓接合墊中的至少一個被接合到該複數個電阻器選擇墊中的至少一個。Another embodiment of the present disclosure provides a semiconductor device, including: a wafer and a substrate. The chip includes an electronic fuse control circuit including a programming voltage pad, a fuse element, a latch, an operation switch unit, a plurality of resistor selection pads, and a plurality of bonding option units . The programming voltage pad is configured to receive a programming voltage. The fuse element includes a first terminal coupled to the programming voltage pad, and a second terminal. The latch includes an input terminal and an output terminal. The operation switch unit is configured to form an electrical connection between the second terminal of the fuse element and a ground terminal during a programming operation, and to establish an electrical connection between the fuse element during a read operation. An electrical connection is formed between the second end of the element and the input end of the latch. Each of the plurality of engagement option cells includes a resistor and a selection switch connected in series between the input terminal of the latch and a corresponding resistor selection pad of the plurality of resistor selection pads. The substrate includes a first voltage bonding pad and a plurality of second voltage bonding pads. The first voltage bonding pad is bonded to the programming voltage pad, and at least one of the plurality of second voltage bonding pads is bonded to at least one of the plurality of resistor selection pads.

在一些實施例中，該熔線器元件是一種反熔線器。In some embodiments, the fuse element is an anti-fuse.

在一些實施例中，該複數個接合選項單元的電阻器具有不同的電阻器。In some embodiments, the plurality of resistors engaging the option unit have different resistors.

在一些實施例中，該電子熔線控制電路更包括一讀取開關，該讀取開關包括與該熔線器元件的該第一端耦合的一第一端、與該接地端耦合的一第二端以及經配置以接收一讀取控制訊號的一控制端。In some embodiments, the electronic fuse control circuit further includes a read switch, the read switch includes a first terminal coupled to the first terminal of the fuse element, a first terminal coupled to the ground terminal Two terminals and a control terminal configured to receive a read control signal.

在一些實施例中，該操作開關單元包括一第一開關、一第二開關以及一第三開關。該第一開關包括與該熔線器元件的該第二端耦合的一第一端、一第二端以及經配置以接收一讀取和編程控制訊號的一控制端。該第二開關包括與該第一開關的該第二端耦合的一第一端，與該接地端耦合的一第二端，以及經配置以接收一編程控制訊號的一控制端。該第三開關包括與該第一開關的該第二端耦合的一第一端，與該鎖存器的該輸入端耦合的一第二端，以及經配置以接收一讀取控制訊號的一控制端。In some embodiments, the operation switch unit includes a first switch, a second switch and a third switch. The first switch includes a first terminal coupled to the second terminal of the fuse element, a second terminal, and a control terminal configured to receive a read and program control signal. The second switch includes a first terminal coupled with the second terminal of the first switch, a second terminal coupled with the ground terminal, and a control terminal configured to receive a programming control signal. The third switch includes a first terminal coupled to the second terminal of the first switch, a second terminal coupled to the input terminal of the latch, and a configured to receive a read control signal Control terminal.

在一些實施例中，該鎖存器更包括一第一反相器以及一第二反相器。該第一反相器包括與該鎖存器的該輸入端耦合的一輸入端，以及與該鎖存器的該輸出端耦合的一輸出端。該第二反相器包括與該鎖存器的一輸出端耦合的一輸入端，以及與該鎖存器的該輸入端耦合的一輸出端。In some embodiments, the latch further includes a first inverter and a second inverter. The first inverter includes an input coupled to the input of the latch, and an output coupled to the output of the latch. The second inverter includes an input coupled to an output of the latch, and an output coupled to the input of the latch.

在一些實施例中，被接合到該複數個第二電壓接合墊中的一第二電壓接合墊的一電阻器選擇墊經配置以在該讀取操作期間接收一讀取電壓，其中該讀取電壓小於該編程電壓。In some embodiments, a resistor select pad bonded to a second voltage bond pad of the plurality of second voltage bond pads is configured to receive a read voltage during the read operation, wherein the read voltage is less than the programming voltage.

本揭露的另一實施例提供一種半導體元件的製備方法，包括：提供包括一電子熔線控制電路的一晶片，其中該電子熔線控制電路包括一編程電壓墊、一熔線器元件、一鎖存器、複數個電阻器選擇墊以及複數個接合選項單元。該編程電壓墊與該熔線器元件的一第一端耦合，而該複數個接合選項單元中的每一都都包括一電阻器和一選擇開關，串聯在該鎖存器的該輸入端和該複數個電阻器選擇墊中的一相應電阻器選擇墊之間。該製備方法更包括提供包括一第一電壓接合墊和複數個第二電壓接合墊的一基底，將該晶片設置在該基底上，將該第一電壓接合墊與該編程電壓墊接合，以及將該複數個第二電壓接合墊中的至少一個與該複數個電阻器選擇墊中的至少一個接合。Another embodiment of the present disclosure provides a method of fabricating a semiconductor device, including: providing a chip including an electronic fuse control circuit, wherein the electronic fuse control circuit includes a programming voltage pad, a fuse element, a lock registers, resistor selection pads, and bonding option cells. The programming voltage pad is coupled to a first end of the fuse element, and each of the plurality of bonding option cells includes a resistor and a selection switch connected in series between the input end of the latch and between a corresponding one of the plurality of resistor selection pads. The manufacturing method further includes providing a substrate including a first voltage bonding pad and a plurality of second voltage bonding pads, disposing the wafer on the substrate, bonding the first voltage bonding pad to the programming voltage pad, and At least one of the plurality of second voltage bonding pads is bonded to at least one of the plurality of resistor selection pads.

在一些實施例中，該製備方法更包括根據該熔線器元件的狀態來執行一測試操作，以決定將該複數個電阻器選擇墊中的該至少一個接合到該複數個第二電壓接合墊中的該至少一個。In some embodiments, the manufacturing method further includes performing a test operation according to the state of the fuse element to determine to bond the at least one of the plurality of resistor selection pads to the plurality of second voltage bonding pads at least one of the .

在一些實施例中，根據該熔線器元件的該狀態執行該測試操作，以決定將該複數個電阻器選擇墊中的該至少一個接合到該複數個第二電壓接合墊中的該至少一個，包括：用該複數個接合選項單元中的一第一接合選項單元讀取該熔線器元件，以產生一第一讀取結果，以及當該第一讀取結果被確定為負向時，用該複數個接合選項單元中的一第二接合選項單元對該熔線器元件執行一讀取操作，以產生一第二讀取結果。In some embodiments, the test operation is performed based on the state of the fuse element to determine to bond the at least one of the plurality of resistor selection pads to the at least one of the plurality of second voltage bond pads , comprising: reading the fuse element with a first bond option cell of the plurality of bond option cells to generate a first read result, and when the first read result is determined to be negative, A read operation is performed on the fuse element with a second bond option unit of the plurality of bond option cells to generate a second read result.

在一些實施例中，當該第二讀取結果確定為正向時，執行該測試操作更包括決定將與該第二接合選項單元耦合的一電阻器選擇墊耦合至該複數個第二電壓接合墊中的該至少一個接合。In some embodiments, when the second read result is determined to be positive, performing the test operation further includes determining to couple a resistor selection pad coupled to the second junction option unit to the plurality of second voltage junctions The at least one of the pads is engaged.

在一些實施例中，用該複數個接合選項單元中的該第一接合選項單元讀取該熔線器元件，以產生第一讀取結果，包括：將一讀取電壓施加到與該第一接合選項單元耦合的一電阻器選擇墊上，導通該第一接合選項單元的一選擇開關，將一接地電壓施加到該熔線器元件的該第一端，以及將該熔線器元件的一第二端與該鎖存器的該輸入端耦合。In some embodiments, reading the fuse element with the first bond option cell of the plurality of bond option cells to generate a first read result includes: applying a read voltage to the first a resistor select pad coupled to the bond option cell, turning on a select switch of the first bond option cell, applying a ground voltage to the first terminal of the fuse element, and a first terminal of the fuse element Two terminals are coupled with the input terminal of the latch.

在一些實施例中，在對該熔線器元件執行該讀取操作之前，藉由向該編程電壓墊施加一編程電壓並向該熔線器元件的該第二端施加一接地電壓，來對該熔線器元件執行一編程操作。In some embodiments, the read operation is performed on the fuse element by applying a programming voltage to the programming voltage pad and applying a ground voltage to the second terminal of the fuse element before performing the read operation on the fuse element. The fuse element performs a programming operation.

本揭露實施例提供的電子熔線控制電路、半導體元件和半導體元件的製備方法允許使用者在晶圓探測製程中選擇適當的接合選項單元，並且更允許使用者隨後在封裝製程中將選擇的接合選項單元連接到基底的接合墊。因此，即使在製備晶片之前無法預測熔線器元件的電阻，製造商也可以在製備晶片之後選擇具有適當電阻的適當接合選項單元，以確保讀取操作的準確性，並避免現有技術中改變參考電阻器所需的額外製程。The electronic fuse control circuit, the semiconductor element, and the method for manufacturing the semiconductor element provided by the embodiments of the present disclosure allow the user to select an appropriate bonding option unit in the wafer probing process, and further allow the user to subsequently select the bonding option unit in the packaging process. The option unit is connected to the bonding pads of the substrate. Thus, even if the resistance of the fuse element cannot be predicted before wafer fabrication, the manufacturer can select the appropriate bonding option cell with the appropriate resistance after wafer fabrication to ensure accuracy of read operations and avoid changing references as in the prior art Additional process required for resistors.

上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。設置本揭露之揭露專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可以相當容易地利用下文揭示之概念與特定實施例可以做為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之揭露專利範圍所定義之本揭露的精神和範圍。The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages of setting the disclosed patent scope of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure as defined by the appended patent disclosures.

以下揭露內容提供做為實作本揭露的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列形式的具體實施例或實例以簡化本揭露內容。當然，該些僅為實例且不旨在執行限制。舉例而言，元件的尺寸並非僅限於所揭露範圍或值，而是可以相依於製程條件及/或元件的所期望性質。此外，以下說明中將第一特徵形成於第二特徵「上方」或第二特徵「上」可以包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可以包括其中第一特徵與第二特徵之間可以形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。為簡潔及清晰起見，可以按不同比例任意繪製一些特徵。在附圖中，為簡化起見，可以省略一些層/特徵。The following disclosure provides a number of different embodiments or examples for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or the desired properties of the elements. In addition, in the following description, the first feature is formed "over" the second feature or "on" the second feature may include the embodiment in which the first feature and the second feature are formed in direct contact, and may also include the embodiment in which the first feature Embodiments in which an additional feature may be formed between a feature and a second feature such that the first feature may not be in direct contact with the second feature. For simplicity and clarity, some features may be arbitrarily drawn at different scales. In the drawings, some layers/features may be omitted for simplicity.

此外，為易於說明，本文中可能使用例如「之下(beneath)」、「下方(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述元件可以具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可以同樣相應地執行直譯。Additionally, for ease of description, spaces such as "beneath", "below", "lower", "above", "upper" may be used herein Relative relationship terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The described elements may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may also be translated accordingly.

應當理解，當元件或層被稱為“連接到”或“耦合到”另一個元件或層時，它可以直接連接到或耦合到另一個元件或層，或其間間元件或層可能存在。It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer, or intervening elements or layers may be present.

應當理解，儘管可以用術語第一、第二等來描述各種元素，但這些元素不應受到術語的限制。除非另有說明，術語僅用於區分一個元素和另一個元素。因此，例如，下面討論的第一要素、第一元件或第一部分可以被稱為第二要素、第二元件或第二部分，而不偏離本揭露內容的教導。It will be understood that, although the terms first, second, etc. may be used to describe various elements, these elements should not be limited by the terms. Unless stated otherwise, terms are only used to distinguish one element from another. Thus, for example, a first element, a first element or a first section discussed below could be termed a second element, a second element or a second section without departing from the teachings of the disclosure.

除非上下文另有說明，本文在提到方向、佈局、位置、形狀、大小、數量或其他措施時，使用的術語如"相同"、"相等"、"平面”或”共面"，不一定是指完全相同的方向、佈局、位置、形狀、大小、數量或其他措施，而是指在可能發生的、例如由於製造製程而發生的可接受的變化範圍內，包括幾乎相同的方向、佈局、位置、形狀、大小、數量或其他措施。術語”實質上”可以用來反映此含義。例如，被描述為”實質上相同"、"實質上相等”或”實質上平面”的項目可以是完全相同、相等或平面，也可以是在可接受的變化範圍內相同、相等或平面，例如由於製程而可能發生的變化。Unless the context dictates otherwise, terms such as "same", "equal", "planar" or "coplanar" are used herein when referring to orientation, arrangement, position, shape, size, quantity or other measures, not necessarily means identical in orientation, arrangement, position, shape, size, quantity, or other measure, but means nearly identical in orientation, arrangement, position, within acceptable variations that may occur, for example, due to manufacturing processes , shape, size, quantity or other measure. The term "substantially" may be used to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially flat" could be identical, equal, or flat, or the same, equal, or flat within acceptable variations, such as Variations may occur due to process.

在本揭露中，半導體元件一般是指能夠利用半導體特性發揮作用的元件，電光元件、發光顯示元件、半導體電路和電子元件均包括在本揭露中。半導體元件的類別。具體地，本揭露實施例的半導體元件可以是動態隨機存取記憶體元件。In the present disclosure, a semiconductor element generally refers to an element capable of utilizing semiconductor properties to function, and electro-optic elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the present disclosure. Types of semiconductor components. Specifically, the semiconductor device of the disclosed embodiment may be a dynamic random access memory device.

圖2是電路圖，例示本揭露一實施例之電子熔線控制電路100。電子熔線控制電路100包括編程電壓墊PP1、複數個電阻器選擇墊PS1至PSN、熔線器元件110、鎖存器120、操作開關單元130、和複數個接合選項單元1401至140N，其中N是大於1的正整數。FIG. 2 is a circuit diagram illustrating an electronic fuse control circuit 100 according to an embodiment of the present disclosure. The electronic fuse control circuit 100 includes a programming voltage pad PP1, a plurality of resistor selection pads PS1 to PSN, a fuse element 110, a latch 120, an operation switch unit 130, and a plurality of bonding option units 1401 to 140N, where N is a positive integer greater than 1.

熔線器元件110包括第一端和第二端，熔線器元件110的第一端與編程電壓墊PP1耦合。在本實施例中，熔線器元件110可以是反熔線器(antifuse)，並且可以具有與圖1中所示的反熔線器AF1相同的結構。在此情況下，熔線器元件110的第一端可以是反熔線器元件AF1的閘極G1，而熔線器元件110的第二端可以是反熔線器元件AF1的主動區A1。The fuse element 110 includes a first end and a second end, and the first end of the fuse element 110 is coupled to the programming voltage pad PP1. In this embodiment, the fuse element 110 may be an antifuse, and may have the same structure as the antifuse AF1 shown in FIG. 1 . In this case, the first end of the fuse element 110 may be the gate G1 of the anti-fuse element AF1 , and the second end of the fuse element 110 may be the active area A1 of the anti-fuse element AF1 .

鎖存器120包括輸入端和輸出端。操作開關單元130與熔線器元件110的第二端、鎖存器120的輸入端和接地端耦合。在本實施例中，操作開關單元130可以根據要執行的操作，在熔線器元件110的第二端和接地端之間形成電性連接，或者在熔線器元件110的第二端和鎖存器120的輸入端之間形成電性連接。The latch 120 includes an input terminal and an output terminal. The operation switch unit 130 is coupled with the second terminal of the fuse element 110, the input terminal of the latch 120 and the ground terminal. In this embodiment, the operation switch unit 130 can form an electrical connection between the second end of the fuse element 110 and the ground end, or between the second end of the fuse element 110 and the lock according to the operation to be performed. An electrical connection is formed between the input terminals of the memory 120.

此外，接合選項單元1401至140N中的每一個包括串聯在鎖存器120的輸入端和電阻器選擇墊PS1至PSN中一相應電阻器選擇墊之間的一電阻器和一選擇開關。例如，接合選項單元1401可以耦合到電阻器選擇墊PS1，而接合選項單元140N可以耦合到電阻器選擇墊PSN。此外，在本實施例中，接合選項單元1401至140N的電阻器1441至144N可以具有不同的電阻值，且選擇開關1421至142N可以分別並相應地受控於控制訊號SIG C1至控制訊號SIG CN。 In addition, each of the bonding option cells 1401 to 140N includes a resistor and a selection switch connected in series between the input terminal of the latch 120 and a corresponding one of the resistor selection pads PS1 to PSN. For example, bond option cell 1401 may be coupled to resistor select pad PS1 and bond option cell 140N may be coupled to resistor select pad PSN. In addition, in this embodiment, the resistors 1441 to 144N connecting the option units 1401 to 140N can have different resistance values, and the selection switches 1421 to 142N can be respectively and correspondingly controlled by the control signals SIG C1 to SIG CN .

鎖存器120包括第一反相器122和第二反相器124。第一反相器122包括與鎖存器120的輸入端耦合的一輸入端，以及與鎖存器120的輸出端耦合的一輸出端。第二反相器124包括與鎖存器120的輸出端耦合的一輸入端，以及與鎖存器120的輸入端耦合的一輸出端。The latch 120 includes a first inverter 122 and a second inverter 124 . The first inverter 122 includes an input terminal coupled to the input terminal of the latch 120 , and an output terminal coupled to the output terminal of the latch 120 . The second inverter 124 includes an input terminal coupled to the output terminal of the latch 120 , and an output terminal coupled to the input terminal of the latch 120 .

此外，操作開關單元130包括第一開關132、第二開關134和第三開關136。第一開關132包括與熔線器元件110的第二端耦合的一第一端、一第二端、和用於接收讀取和編程控制訊號SIG RP的一控制端。第二開關134包括與第一開關132的第二端耦合的一第一端，與接地端耦合的一第二端，以及用於接收編程控制訊號SIG P的一控制端。第三開關136包括與第一開關132的第二端耦合的一第一端，與鎖存器120的輸入端耦合的一第二端，以及用於接收讀取控制訊號SIG R的一控制端。 In addition, the operation switch unit 130 includes a first switch 132 , a second switch 134 and a third switch 136 . The first switch 132 includes a first terminal coupled to the second terminal of the fuse element 110, a second terminal, and a control terminal for receiving the read and program control signal SIG RP . The second switch 134 includes a first terminal coupled to the second terminal of the first switch 132 , a second terminal coupled to the ground terminal, and a control terminal for receiving the programming control signal SIG P. The third switch 136 includes a first terminal coupled to the second terminal of the first switch 132, a second terminal coupled to the input terminal of the latch 120, and a control terminal for receiving the read control signal SIG R .

在本實施例中，電子熔線控制電路100更可以包括讀取開關150。讀取開關150包括與熔線器元件110的第一端耦合的一第一端，與接地端耦合的一第二端，以及用於接收讀取控制訊號SIG R的一控制端。在一些實施例中，開關132、134、136和150可以是，例如但不限於，由電晶體形成。在本實施例中，開關132、134、136和150可以由N型金屬氧化物半導體(MOS)電晶體實現。 In this embodiment, the electronic fuse control circuit 100 may further include a read switch 150 . The read switch 150 includes a first terminal coupled to the first terminal of the fuse element 110 , a second terminal coupled to the ground terminal, and a control terminal for receiving the read control signal SIG R. In some embodiments, switches 132, 134, 136, and 150 may be, for example and without limitation, formed of transistors. In this embodiment, the switches 132, 134, 136 and 150 may be implemented by N-type metal oxide semiconductor (MOS) transistors.

圖3是時序圖，例示圖2之電子熔線控制電路100在編程操作和讀取操作期間接收控制訊號的時序。如圖3所示，編程操作是在T1期間執行的，讀取操作是在T2期間執行的。圖4是電路圖，例示圖2之電子熔線控制電路100的編程操作期間。FIG. 3 is a timing diagram illustrating the timing of receiving control signals by the electronic fuse control circuit 100 of FIG. 2 during a program operation and a read operation. As shown in FIG. 3, the program operation is performed during T1, and the read operation is performed during T2. FIG. 4 is a circuit diagram illustrating during a programming operation of the electronic fuse control circuit 100 of FIG. 2 .

在T1期間，編程控制訊號SIG P與讀取和編程控制訊號SIG RP處於邏輯高電壓電平，而讀取控制訊號SIG R處於邏輯低電壓電平。在此情況下，操作開關單元130的第一開關132和第二開關134導通(turn on)，而第三開關136和讀取開關150截止(turn off)。 During T1, the program control signal SIG P and the read and program control signal SIG RP are at a logic high voltage level, and the read control signal SIG R is at a logic low voltage level. In this case, the first switch 132 and the second switch 134 of the operation switch unit 130 are turned on, and the third switch 136 and the read switch 150 are turned off.

此外，如圖4所示，編程電壓墊PP1可以在編程操作期間接收編程電壓VP。由於操作開關單元130的第一開關132和第二開關134導通，熔線器元件110的第二端和接地端之間形成電性連接，以便將熔線器元件110的第二端拉低到接地電壓。在本實施例中，編程電壓VP可以是高到足以燒斷熔線器元件110的高電壓。在此情況下，熔線器元件110的閘極氧化物可以被施加在熔線器元件110上的高電壓擊穿，因此在熔線器元件110的第一端和第二端之間將形成低電阻器路徑。因此，如圖4所示，從編程電壓墊PP1到接地端形成電流路徑CP1，通過熔線器元件110、第一開關132和第二開關134。In addition, as shown in FIG. 4, the program voltage pad PP1 may receive a program voltage VP during a program operation. Since the first switch 132 and the second switch 134 of the operation switch unit 130 are turned on, an electrical connection is formed between the second terminal of the fuse element 110 and the ground terminal, so that the second terminal of the fuse element 110 is pulled down to ground voltage. In this embodiment, the programming voltage VP may be a high voltage high enough to blow the fuse element 110 . In this case, the gate oxide of the fuse element 110 can be broken down by the high voltage applied across the fuse element 110, thus forming a low resistor path. Therefore, as shown in FIG. 4 , a current path CP1 is formed from the programming voltage pad PP1 to the ground terminal, passing through the fuse element 110 , the first switch 132 and the second switch 134 .

在編程操作之後，如圖3所示，在週期T2中執行讀取操作。圖5是電路圖，例示圖2之電子熔線控制電路100的讀取操作期間。在讀取操作期間，編程控制訊號SIG P處於邏輯低電壓電平，而讀取和編程控制訊號SIG RP和讀取控制訊號SIG R處於邏輯高電壓電平。在此情況下，第二開關134截止，而第一開關132、第三開關136和讀取開關150導通。因此，熔線器元件110的第二端和鎖存器120的輸入端之間形成電性連接。 After the program operation, as shown in FIG. 3, a read operation is performed in a period T2. FIG. 5 is a circuit diagram illustrating during a read operation of the electronic fuse control circuit 100 of FIG. 2 . During a read operation, the program control signal SIG P is at a logic low voltage level, and the read and program control signal SIG RP and the read control signal SIG R are at a logic high voltage level. In this case, the second switch 134 is turned off, and the first switch 132 , the third switch 136 and the read switch 150 are turned on. Therefore, an electrical connection is formed between the second terminal of the fuse element 110 and the input terminal of the latch 120 .

此外，在圖5所示的實施例中，在讀取操作期間，接合選項單元1401至140N的選擇開關1421至142N導通。此外，由於電阻器選擇墊PS1被接合到外部接合墊並在讀取操作期間接收讀取電壓VR，因此在本實施例中是利用接合選項單元1401來執行讀取操作。在此情況下，如圖5所示，可以從電阻器選擇墊PS1到接地端形成電流路徑CP2，該電流路徑通過接合選項單元1401的電阻器1441、第三開關136、第一開關132、熔線器元件110和讀取開關150。因此，鎖存器120可以感應到熔線器元件110的第二端上的電壓VF，並且相應地輸出資料訊號SIG D。在一些實施例中，為了防止熔線器元件110被讀取電壓VR燒斷，讀取電壓VR應小於編程電壓VP。例如，編程電壓VP可以是6V，而讀取電壓VR可以是2V。應當理解，在其他一些實施例中，也可以採用其他的接合選項單元來執行讀取操作。在此情況下，與所欲採用的接合選項單元耦合的電阻器選擇墊將被接合到外部接合墊上，以便在讀取操作期間接收讀取電壓VR。 Furthermore, in the embodiment shown in FIG. 5 , during a read operation, selection switches 1421 to 142N engaging option cells 1401 to 140N are turned on. In addition, since the resistor selection pad PS1 is bonded to an external bonding pad and receives the read voltage VR during the read operation, the read operation is performed using the bond option unit 1401 in this embodiment. In this case, as shown in FIG. 5 , a current path CP2 may be formed from the resistor selection pad PS1 to the ground terminal through the resistor 1441 joining the option unit 1401, the third switch 136, the first switch 132, the fuse Sensor element 110 and read switch 150. Therefore, the latch 120 can sense the voltage VF on the second terminal of the fuse element 110 and output the data signal SIG D accordingly. In some embodiments, in order to prevent the fuse element 110 from being blown by the read voltage VR, the read voltage VR should be smaller than the programming voltage VP. For example, the program voltage VP may be 6V, and the read voltage VR may be 2V. It should be understood that in some other embodiments, other bonded option units may also be used to perform the read operation. In this case, the resistor select pad coupled to the desired bond option cell will be bonded to an external bond pad to receive the read voltage VR during a read operation.

在本實施例中，熔線器元件110的第二端的電壓VF是根據電阻器1441的電阻與熔線器元件110的電阻之比值產生的讀取電壓VR的分電。圖6是電路圖，例示圖2之電子熔線控制電路100在讀取操作期間的等效電路。如圖6所示，熔線器元件110第二端的電壓VF可以用公式(1)表示。

Figure 02_image001
公式(1) In this embodiment, the voltage VF at the second terminal of the fuse element 110 is a division of the read voltage VR generated according to the ratio of the resistance of the resistor 1441 to the resistance of the fuse element 110 . FIG. 6 is a circuit diagram illustrating an equivalent circuit of the electronic fuse control circuit 100 of FIG. 2 during a read operation. As shown in FIG. 6 , the voltage VF at the second terminal of the fuse element 110 can be expressed by formula (1).
Figure 02_image001
Formula 1)

在公式(1)中，R 110代表熔線器元件110的電阻，而R 1441代表電阻器1441的電阻。在一些實施例中，如果電壓VF大於0.6V，鎖存器120將把資料訊號SIG D鎖存到邏輯低電壓電平，如果電壓VF小於0.6V，鎖存器120將把資料訊號SIG D鎖存到邏輯高電壓電平。在此情況下，為了根據電壓VF正確識別熔線器元件110的狀態，在對熔線器元件110執行編程之前，電阻器1441的電阻R 1441應該與熔線器元件110的電阻R 110相當接近，如此一來，熔線器元件110的電阻R 110的變化就可以藉由電壓VF明顯反映出來。 In equation (1), R 110 represents the resistance of fuse element 110 , and R 1441 represents the resistance of resistor 1441 . In some embodiments, if the voltage VF is greater than 0.6V, the latch 120 will latch the data signal SIG D to a logic low voltage level, and if the voltage VF is less than 0.6V, the latch 120 will latch the data signal SIG D stored to a logic high voltage level. In this case, in order to correctly identify the state of the fuse element 110 from the voltage VF, the resistance R 1441 of the resistor 1441 should be fairly close to the resistance R 110 of the fuse element 110 before programming the fuse element 110 , so that the change of the resistance R 110 of the fuse element 110 can be clearly reflected by the voltage VF.

在本實施例中，電阻器1441的電阻R 1441可以是4兆歐姆(MΩ)，熔線器元件110的電阻R 110在熔線器元件110被編程之前可以是5兆歐姆，而熔線器元件110的電阻R 110在熔線器元件110被編程之後可以變成100千歐姆(kΩ)。在此情況下，由於熔線器元件110在前一期間T1已經被編程，電壓VF將是0.029V，鎖存器120將把資料訊號SIG D鎖存到邏輯高電壓電平。然而，如果熔線器元件110沒有被編程，則電壓VF將是0.67V，鎖存器120將把資料訊號SIG D鎖存到邏輯低電壓電平。因此，可以根據資料訊號SIG D的電壓電平來識別熔線器元件110的狀態。 In this embodiment, the resistance R 1441 of the resistor 1441 may be 4 megaohms (MΩ), the resistance R 110 of the fuse element 110 may be 5 megaohms before the fuse element 110 is programmed, and the fuse Resistance R 110 of element 110 may become 100 kilo-ohms (kΩ) after fuse element 110 is programmed. In this case, since the fuse element 110 has been programmed during the previous period T1, the voltage VF will be 0.029V, and the latch 120 will latch the data signal SIG D to a logic high voltage level. However, if fuse element 110 is not programmed, voltage VF will be 0.67V and latch 120 will latch data signal SIG D to a logic low voltage level. Therefore, the state of the fuse element 110 can be identified according to the voltage level of the data signal SIG D.

然而，在其他一些實施例中，熔線器元件110的電阻R 110在被編程之前可能小於5兆歐姆，例如5兆歐姆，而在被編程之後可能變成100千歐姆。因此，如果不對熔線器元件110執行編程，電壓VF將是0.33V，如果對熔線器元件110執行編程，電壓VF將是0.029V。由於在這兩種情況下電壓VF都小於0.6V，所以無論熔線器元件110是否被編程，鎖存器120都會將資料訊號SIG D鎖存到邏輯高電壓電平。在此情況下，接合選項單元1401的電阻器1441可能就不適合用以做為識別熔線器元件110狀態的參考電組，而可以採用其他具有較小電阻的接合選項單元。 However, in other embodiments, the resistance R 110 of the fuse element 110 may be less than 5 megohms, eg, 5 megohms, before being programmed, and may become 100 kiloohms after being programmed. Therefore, if the fuse element 110 is not programmed, the voltage VF will be 0.33V, and if the fuse element 110 is programmed, the voltage VF will be 0.029V. Since the voltage VF is less than 0.6V in both cases, the latch 120 will latch the data signal SIG D to a logic high voltage level regardless of whether the fuse element 110 is programmed or not. In this case, the resistor 1441 of the joint option unit 1401 may not be suitable as a reference electrical set for identifying the state of the fuse element 110 , and other joint option units with lower resistance may be used.

為了確保讀取操作的結果能夠反映出熔線器元件110的狀態，不同的熔線器元件110可以採用不同的接合選項單元來實現不同的電阻。在一些實施例中，可以執行一測試操作，藉由對不同的接合選項單元執行讀取操作來找到具有適當電阻的適當接合選項單元。In order to ensure that the result of the read operation reflects the state of the fuse element 110, different fuse elements 110 may use different bonding option cells to achieve different resistances. In some embodiments, a test operation may be performed by performing a read operation on different bond option cells to find a suitable bond option cell with an appropriate resistance.

此外，在本實施例中，編程電壓墊PP1和電阻器選擇墊PS1至PSN可以是探測(probe)墊，可以接收來自探測卡(probe card)的電壓，以便在晶圓探測程序中對熔線器元件110執行編程操作和讀取操作。亦即，在電子熔線控制電路100的晶片被封裝之前，可以決定並選擇適當的接合選項單元。在此情況下，在選擇適當的接合選項單元之後，在封裝製程中便可將與該選擇的接合選項單元相應耦合的電阻器選擇墊接合到封裝基底的接合墊上，而其餘的電阻器選擇墊可以在封裝製程之後不被接合。如此一來，不同的電子熔線控制電路100的晶片可有不同的接合選項，因此確保可以準確地執行讀取操作，避免現有技術中改變參考電阻所需的額外製程。In addition, in this embodiment, the programming voltage pad PP1 and the resistor selection pads PS1 to PSN can be probe pads, which can receive a voltage from a probe card, so as to detect fuses during the wafer probing process. The device element 110 performs a program operation and a read operation. That is, before the chip of the electronic fuse control circuit 100 is packaged, an appropriate bonding option unit can be determined and selected. In this case, after an appropriate bonding option unit is selected, the resistor selection pad correspondingly coupled to the selected bonding option unit can be bonded to the bonding pad of the package substrate during the packaging process, while the rest of the resistor selection pads May not be bonded after packaging process. In this way, different chips of the electronic fuse control circuit 100 can have different bonding options, thus ensuring that the reading operation can be performed accurately, and avoiding the extra process required to change the reference resistor in the prior art.

圖7是俯視圖，例示本揭露一實施例之半導體元件10。圖8是剖視圖，例示本揭露一實施例之沿圖7所示A-A'線拍攝的半導體元件10。半導體元件10包括晶片12和基底14。晶片12包括電子熔線控制電路100。在一些實施例中，晶片12更可以包括其他電路，電子熔線控制電路100的熔線器元件110可以做為其他電路的儲存體或電子識別碼(identifier)。例如，晶片12更可以包括動態隨機存取記憶體(DRAM)，而電子熔線控制電路100的熔線器元件110可以做為DRAM的識別碼。在一些實施例中，晶片12更可以包括額外的電子熔線控制電路100，用於根據系統要求儲存更多的資料位元。FIG. 7 is a top view illustrating a semiconductor device 10 according to an embodiment of the present disclosure. FIG. 8 is a cross-sectional view illustrating the semiconductor device 10 taken along line AA' shown in FIG. 7 according to an embodiment of the present disclosure. Semiconductor element 10 includes a wafer 12 and a substrate 14 . Die 12 includes electronic fuse control circuitry 100 . In some embodiments, the chip 12 may further include other circuits, and the fuse element 110 of the electronic fuse control circuit 100 may serve as a storage body or an electronic identifier for other circuits. For example, the chip 12 can further include a dynamic random access memory (DRAM), and the fuse element 110 of the electronic fuse control circuit 100 can be used as an identification code of the DRAM. In some embodiments, the chip 12 may further include an additional electronic fuse control circuit 100 for storing more data bits according to system requirements.

基底14包括第一電壓接合墊BPA1和複數個第二電壓接合墊BPB1至BPBN，而晶片12可以經設置在基底14上。在本實施例中，第一電壓接合墊BPA1、第二電壓接合墊BPB1至BPBN、編程電壓墊PP1和電阻器選擇墊PS1至PSN均朝上，因此第一電壓接合墊BPA1和第二電壓接合墊BPB1至BPBN可藉由相應的接合線(bonding wire)與編程電壓墊PP1和電阻器選擇墊PS1至PSN連接。The substrate 14 includes a first voltage bonding pad BPA1 and a plurality of second voltage bonding pads BPB1 to BPBN, and the chip 12 may be disposed on the substrate 14 . In this embodiment, the first voltage bonding pad BPA1, the second voltage bonding pads BPB1 to BPBN, the programming voltage pad PP1 and the resistor selection pads PS1 to PSN are all facing up, so the first voltage bonding pad BPA1 and the second voltage bonding pad The pads BPB1 to BPBN may be connected to the programming voltage pad PP1 and the resistor selection pads PS1 to PSN through corresponding bonding wires.

例如，如圖7所示，第一電壓接合墊BPA1藉由接合線BW1接合到編程電壓墊PP1，而第二電壓接合墊BB1可以藉由接合線BW2接合到電阻器選擇墊PS1。在此情況下，第二電壓接合墊BPB1可以在讀取操作期間接收讀取電壓VR，而與電阻器選擇墊PS1耦合的接合選項單元1401將用於執行讀取操作。此外，由於第二電壓接合墊BPB2至BPBN未與電阻器選擇墊PS2至PSN接合，因此接合選項單元1402至140N將不會在讀取操作期間被採用。For example, as shown in FIG. 7, the first voltage bonding pad BPA1 is bonded to the programming voltage pad PP1 through the bonding wire BW1, and the second voltage bonding pad BB1 may be bonded to the resistor selection pad PS1 through the bonding wire BW2. In this case, the second voltage bond pad BPB1 may receive the read voltage VR during a read operation, and the bond option unit 1401 coupled with the resistor selection pad PS1 will be used to perform the read operation. Furthermore, since the second voltage bond pads BPB2 to BPBN are not bonded to the resistor select pads PS2 to PSN, the bond option cells 1402 to 140N will not be employed during the read operation.

然而，在其他一些實施例中，如果選擇接合選項單元1402來執行讀取操作，則第二電壓接合墊BPB2將被接合到電阻器選擇墊PS2上，而第二電壓接合墊BPB1可能不會被接合到電阻器選擇墊PS1上。亦即，電子熔線控制電路100允許使用者根據晶圓探測製程的測試結果，從接合選項單元1401至140N中選擇適當的接合選項單元，該選擇的接合選項單元可以在隨後的封裝製程中藉由打線連接到基底的接合墊。因此，即使電子熔線控制電路100的熔線器元件110的電阻可能無法預測，製造商也可以在製備晶片10之後選擇具有適當電阻的適當的接合選項單元，以確保讀取操作的準確性。However, in some other embodiments, if the bonding option cell 1402 is selected to perform a read operation, the second voltage bonding pad BPB2 will be bonded to the resistor selection pad PS2, while the second voltage bonding pad BPB1 may not be bonded. Bonded to Resistor Select Pad PS1. That is, the electronic fuse control circuit 100 allows the user to select an appropriate bonding option unit from the bonding option units 1401 to 140N according to the test result of the wafer probing process, and the selected bonding option unit can be borrowed in the subsequent packaging process. Bond pads connected to the substrate by wire bonding. Therefore, even though the resistance of the fuse element 110 of the electronic fuse control circuit 100 may be unpredictable, the manufacturer can select the appropriate bonding option cell with the appropriate resistance after the wafer 10 is prepared to ensure the accuracy of the read operation.

此外，在一些實施例中，不同接合選項單元中的電阻可以並聯，並可組合用於讀取操作，因此提供更多的電阻電平選擇。圖9是俯視圖，例示本揭露另一實施例之半導體元件20。半導體元件20和半導體元件10具有類似的結構，可以根據相同的原理執行操作。然而，在半導體元件20中，第二電壓接合墊BPB1藉由接合線BW2接合到電阻器選擇墊PS1，第二電壓接合墊BPB2藉由接合線BW3接合到電阻器選擇墊PS2。在此情況下，在讀取操作期間，第二電壓接合墊BPB1和BPB2可以同時接收讀取電壓VR，並且接合選項單元1401和1402的選擇開關1421和1422可以同時導通。因此，電阻器1441和1442可以並聯，做為參考電阻器，與熔線器元件110產生分配電壓VF。亦即，接合選項單元1401至140N的電阻器可以單獨或組合採用；因此，接合選項單元1401至140N能夠提供多達(2 N-1)個不同電阻的選項。 Additionally, in some embodiments, resistors in different junction option cells can be connected in parallel and combined for read operations, thus providing more resistor level options. FIG. 9 is a top view illustrating a semiconductor device 20 according to another embodiment of the present disclosure. The semiconductor element 20 and the semiconductor element 10 have a similar structure and can perform operations based on the same principle. However, in the semiconductor device 20, the second voltage bonding pad BPB1 is bonded to the resistor selection pad PS1 by the bonding wire BW2, and the second voltage bonding pad BPB2 is bonded to the resistor selection pad PS2 by the bonding wire BW3. In this case, during the read operation, the second voltage bonding pads BPB1 and BPB2 may simultaneously receive the read voltage VR, and the selection switches 1421 and 1422 of the bonding option cells 1401 and 1402 may be simultaneously turned on. Therefore, the resistors 1441 and 1442 can be connected in parallel as reference resistors to generate the split voltage VF with the fuse element 110 . That is, the resistors of the bonded option units 1401 to 140N can be used alone or in combination; thus, the bonded option units 1401 to 140N can provide up to (2 N −1) different resistance options.

圖10是流程圖，例示本揭露一實施例之半導體元件10的製備方法200。製備方法200包括步驟S210至步驟S260。在步驟S210中，提供包括電子熔線控制電路100的晶片12，並在步驟S220中對電子熔線控制電路100的熔線器元件110執行測試操作。在本實施例中，根據熔線器元件110的狀態執行測試操作，以決定要與第二電壓接合墊接合的電阻器選擇墊。在決定將與第二電壓接合墊接合的電阻器選擇墊之後，在步驟S230中提供基底14，並在步驟S240中將晶片12設置在基底14上。此外，在步驟S250中，第一電壓接合墊BPA1被接合到編程電壓墊PP1，並且在步驟S260中，第二電壓接合墊BPB1至BPBN中的至少一個被接合到步驟S220中決定和選擇的電阻器選擇墊。FIG. 10 is a flowchart illustrating a manufacturing method 200 of the semiconductor device 10 according to an embodiment of the present disclosure. The preparation method 200 includes step S210 to step S260. In step S210, the wafer 12 including the electronic fuse control circuit 100 is provided, and a test operation is performed on the fuse element 110 of the electronic fuse control circuit 100 in step S220. In this embodiment, a test operation is performed according to the state of the fuse element 110 to determine the resistor selection pad to be bonded to the second voltage bonding pad. After determining the resistor selection pad to be bonded to the second voltage bonding pad, the substrate 14 is provided in step S230 and the die 12 is disposed on the substrate 14 in step S240. In addition, in step S250, the first voltage bonding pad BPA1 is bonded to the programming voltage pad PP1, and in step S260, at least one of the second voltage bonding pads BPB1 to BPBN is bonded to the resistor determined and selected in step S220. selector pad.

圖11是流程圖，例示本揭露一實施例之測試操作的執行步驟S220的子步驟。如圖11所示，步驟S220包括步驟S221至步驟S225。在步驟S221中，藉由將編程電壓VP施加到編程電壓墊PP1並將接地電壓施加到熔線器元件110的第二端，來對熔線器元件110執行編程操作。然而，在一些實施例中，根據要儲存的資料，熔線器元件110可能傾向不編程。在此情況下，步驟S221可以被省略，熔線器元件110將保持未編程狀態。接下來，在步驟S222中，用從接合選項單元1401至140N中選擇的至少一個接合選項單元對熔線器元件110執行讀取操作，以產生讀取結果。FIG. 11 is a flowchart illustrating the sub-steps of the execution step S220 of the test operation according to an embodiment of the present disclosure. As shown in FIG. 11, step S220 includes step S221 to step S225. In step S221 , a program operation is performed on the fuse element 110 by applying the program voltage VP to the program voltage pad PP1 and applying the ground voltage to the second terminal of the fuse element 110 . However, in some embodiments, depending on the data to be stored, fuse element 110 may be prone to non-programming. In this case, step S221 can be omitted, and the fuse element 110 will remain in an unprogrammed state. Next, in step S222 , a read operation is performed on the fuse element 110 with at least one bond option cell selected from the bond option cells 1401 to 140N to generate a read result.

圖12是流程圖，例示本揭露一實施例之讀取操作的執行步驟。如圖12所示，該讀取操作可以包括步驟S2221至步驟S2224。在步驟S2221中，讀取電壓VR被施加到一電阻器選擇墊上，該電阻器選擇墊與該讀取操作採用的一接合選項單元耦合。在步驟S2222中，採用的該接合選項單元的選擇開關導通。在步驟S2223中，熔線器元件110的第一端被耦合到接地電壓。在步驟S2224中，熔線器元件110的第二端被耦合到鎖存器120的輸入端。在一些實施例中，步驟S2222至步驟S2224可以藉由控制讀取開關150和操作開關單元130的開關來執行。因此，讀取電壓VR的分配電壓VF可以根據所採用的接合選擇單元的電阻與熔線器元件110的電阻之比值來產生，並且鎖存器120可以根據分配電壓VF來鎖存資料訊號SIG D。 FIG. 12 is a flowchart illustrating the execution steps of a read operation according to an embodiment of the present disclosure. As shown in FIG. 12 , the read operation may include steps S2221 to S2224. In step S2221, the read voltage VR is applied to a resistor select pad coupled to a bond option cell used in the read operation. In step S2222, the selection switch of the used joint option unit is turned on. In step S2223, the first end of the fuse element 110 is coupled to a ground voltage. In step S2224 , the second terminal of the fuse element 110 is coupled to the input terminal of the latch 120 . In some embodiments, step S2222 to step S2224 may be performed by controlling the read switch 150 and operating a switch of the switch unit 130 . Therefore, the distribution voltage VF of the read voltage VR can be generated according to the ratio of the resistance of the junction selection unit to the resistance of the fuse element 110, and the latch 120 can latch the data signal SIG D according to the distribution voltage VF. .

在本實施例中，由於在執行測試操作之前已知熔線器元件110的狀態，因此也可以得到預期的讀取結果。例如，如果熔線器元件110已經被編程，可以預期具有邏輯高電壓電平的訊號資料SIG D。但是，如果熔線器元件110沒有被編程，則將不會預期有邏輯高電壓電平的訊號資料SIG D。 In this embodiment, since the state of the fuse element 110 is known before the test operation is performed, an expected reading result can also be obtained. For example, if fuse element 110 has been programmed, a signal data SIGD having a logic high voltage level may be expected. However, if the fuse element 110 is not programmed, a logic high voltage level signal data SIGD would not be expected.

在步驟S223中，可以將讀取結果與預期結果執行比較，以決定當前選擇的接合選項單元是否適當。如果讀取結果被決定為負向，即讀取結果與熔線器元件110的預期狀態不匹配，此讀取結果可能暗示在步驟S221中選擇的接合選項單元不是適當的選擇。在此情況下，在步驟S224中可選擇另一接合選項單元，並以新選擇的接合選項單元再次執行步驟S222。然而，如果讀取結果被確定為是正向的，則當前用於讀取操作的接合選項單元即可被決定為適當的選擇並被選用。在此情況下，在步驟S225中，與選擇的接合選項單元耦合的電阻器選擇墊被確定將接合到相應的第二電壓接合墊上，並且在步驟S260中，藉由測試操作決定或選擇的電阻器選擇墊被接合到相應的第二電壓接合墊。In step S223, the read result may be compared with the expected result to determine whether the currently selected joining option unit is appropriate. If the read result is determined to be negative, ie the read result does not match the expected state of the fuse element 110, this read result may suggest that the bond option cell selected in step S221 is not an appropriate choice. In this case, another joint option unit may be selected in step S224, and step S222 may be performed again with the newly selected joint option unit. However, if the read result is determined to be positive, then the splice option cell currently being used for the read operation can be determined to be an appropriate choice and selected. In this case, in step S225, the resistor selection pad coupled with the selected bonding option unit is determined to be bonded to the corresponding second voltage bonding pad, and in step S260, the resistor selected or determined by the test operation The selector pads are bonded to corresponding second voltage bond pads.

在本實施例中，測試操作可以在晶片12被封裝之前藉由晶圓探測來執行；因此，在選擇適當的接合選項單元之後，電阻器選擇墊和第二電壓接合墊可以在封裝製程的後期被接合，因此確保讀取操作可以被準確執行，並避免現有技術中改變參考電阻器所需的額外製程。In this embodiment, the test operation can be performed by wafer probing before the die 12 is packaged; thus, after selecting the appropriate bonding option cells, the resistor selection pads and the second voltage bonding pads can be processed at a later stage in the packaging process. is bonded, thus ensuring that the read operation can be performed accurately, and avoiding the extra process required to change the reference resistor in the prior art.

綜上所述，本揭露的實施例所提供的電子熔線控制電路、半導體元件以及半導體元件的製備方法允許使用者在晶圓探測製程中選擇適當的接合選項單元，並且使用者隨後可以在封裝製程中將選擇的接合選項單元連接到基底的接合墊上。因此，即使在製造晶片之前無法預測熔線器元件的電阻，製造商也能夠在製造晶片之後選擇具有適當電阻的適當接合選項單元，以確保讀取操作的準確性，並避免現有技術中改變參考電阻所需的額外製程。To sum up, the electronic fuse control circuit, the semiconductor element, and the manufacturing method of the semiconductor element provided by the embodiments of the present disclosure allow the user to select an appropriate bonding option unit in the wafer probing process, and the user can then package The process connects the selected bonding option cells to bonding pads of the substrate. Therefore, even if the resistance of the fuse element cannot be predicted before the wafer is manufactured, the manufacturer is able to select the appropriate bonding option cell with the appropriate resistance after the wafer is manufactured to ensure the accuracy of the read operation and avoid changing the reference Additional process required for resistors.

雖然已詳述本揭露及其優點，然而應理解可以執行一些變化、取代與替代而不脫離揭露專利範圍所定義之本揭露的精神與範圍。例如，可以用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made without departing from the spirit and scope of the disclosure as defined by the patent claims disclosed. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

再者，本揭露案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可以自本揭露的揭示內容理解可以根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包括於本揭露案之揭露專利範圍內。Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future development processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.

10:半導體元件 12:晶片 14:基底 100:電子熔線控制電路 110:熔線器元件 120:鎖存器 122:第一反相器 124:第二反相器 130:操作開關單元 132:第一開關 134:第二開關 136:第三開關 150:讀取開關 200:製備方法 1401~140N:接合選項單元 1421~142N:選擇開關 1441~144N:電阻器 A1:主動區 AF1:反熔線器 BPA1:第一電壓接合墊 BPB1~BPBN:第二電壓接合墊 BW1:接合線 BW2:接合線 BW3:接合線 CP1:電流路徑 CP2:電流路徑 G1:閘極 PP1:編程電壓墊 PS1~PSN:電阻器選擇墊 S210:步驟 S220:步驟 S221:步驟 S222:步驟 S223:步驟 S224:步驟 S225:步驟 S230:步驟 S240:步驟 S250:步驟 S260:步驟 S2221:步驟 S2222:步驟 S2223:步驟 S2224:步驟 SIG C1~SIG CN:控制訊號 SIG D:資料訊號 SIG P:編程控制訊號 SIG R:讀取控制訊號 SIG RP:讀取和編程控制訊號 T1:期間 T2:期間 VF:電壓 VH:編程電壓 VP:編程電壓 VR:讀取電壓 10: semiconductor element 12: wafer 14: substrate 100: electronic fuse control circuit 110: fuse element 120: latch 122: first inverter 124: second inverter 130: operation switch unit 132: second inverter One switch 134: Second switch 136: Third switch 150: Read switch 200: Preparation method 1401~140N: Engagement option unit 1421~142N: Selection switch 1441~144N: Resistor A1: Active area AF1: Antifuse BPA1: first voltage bonding pad BPB1~BPBN: second voltage bonding pad BW1: bonding wire BW2: bonding wire BW3: bonding wire CP1: current path CP2: current path G1: gate PP1: programming voltage pad PS1~PSN: resistor Selector pad S210: Step S220: Step S221: Step S222: Step S223: Step S224: Step S225: Step S230: Step S240: Step S250: Step S260: Step S2221: Step S2222: Step S2223: Step S2224: Step SIG C1 ~SIG CN : Control signal SIG D : Data signal SIG P : Program control signal SIG R : Read control signal SIG RP : Read and program control signal T1: Period T2: Period VF: Voltage VH: Program voltage VP: Program voltage VR: read voltage

參閱實施方式與揭露專利範圍合併考量圖式時，可以得以更全面了解本揭露案之揭示內容，圖式中相同的元件符號係指相同的元件。 圖1是示意圖，例示反熔線器的結構。 圖2是電路圖，例示本揭露一實施例之電子熔線控制電路。 圖3是時序圖，例示圖2之電子熔線控制電路在編程操作和讀取操作期間接收控制訊號的時序。 圖4是電路圖，例示圖2之電子熔線控制電路的編程操作期間。 圖5是電路圖，例示圖2之電子熔線控制電路的讀取操作期間。 圖6是電路圖，例示圖2之電子熔線控制電路在讀取操作期間的等效電路。 圖7是俯視圖，例示本揭露一實施例之半導體元件。 圖8是剖視圖，例示本揭露一實施例之圖7所示半導體元件。 圖9是俯視圖，例示本揭露另一實施例之半導體元件。 圖10是流程圖，例示本揭露一實施例之半導體元件的製備方法。 圖11是流程圖，例示本揭露一實施例之測試操作的執行步驟。 圖12是流程圖，例示本揭露一實施例之讀取操作的執行步驟。 When referring to the embodiments and the patent scope of the disclosure and considering the drawings together, the disclosure content of the disclosure can be understood more comprehensively, and the same reference numerals in the drawings refer to the same components. FIG. 1 is a schematic diagram illustrating the structure of an antifuse. FIG. 2 is a circuit diagram illustrating an electronic fuse control circuit according to an embodiment of the present disclosure. FIG. 3 is a timing diagram illustrating the timing of receiving control signals by the electronic fuse control circuit of FIG. 2 during a program operation and a read operation. FIG. 4 is a circuit diagram illustrating during a programming operation of the electronic fuse control circuit of FIG. 2 . FIG. 5 is a circuit diagram illustrating during a read operation of the electronic fuse control circuit of FIG. 2 . FIG. 6 is a circuit diagram illustrating an equivalent circuit of the electronic fuse control circuit of FIG. 2 during a read operation. FIG. 7 is a top view illustrating a semiconductor device according to an embodiment of the present disclosure. FIG. 8 is a cross-sectional view illustrating the semiconductor device shown in FIG. 7 according to an embodiment of the present disclosure. FIG. 9 is a top view illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 10 is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure. FIG. 11 is a flowchart illustrating the execution steps of a test operation according to an embodiment of the present disclosure. FIG. 12 is a flowchart illustrating the execution steps of a read operation according to an embodiment of the present disclosure.

100:電子熔線控制電路 100: electronic fuse control circuit

110:熔線器元件 110: fuse element

120:鎖存器 120:Latch

122:第一反相器 122: The first inverter

124:第二反相器 124: Second inverter

130:操作開關單元 130: Operation switch unit

132:第一開關 132: first switch

134:第二開關 134: second switch

136:第三開關 136: The third switch

150:讀取開關 150: read switch

1401~140N:接合選項單元 1401~140N: Joint option unit

1421~142N:選擇開關 1421~142N: selection switch

1441~144N:電阻器 1441~144N: Resistor

PP1:編程電壓墊 PP1: Programming Voltage Pad

PS1~PSN:電阻器選擇墊 PS1~PSN: Resistor selection pads

SIGC1~SIGCN:控制訊號 SIG C1 ~SIG CN : Control signal

SIGD:資料訊號 SIG D : Data signal

SIGP:編程控制訊號 SIG P : programming control signal

SIGR:讀取控制訊號 SIG R : read control signal

SIGRP:讀取和編程控制訊號 SIG RP : read and program control signals

Claims (20)

一種電子熔線控制電路，包括： 一編程電壓墊，經配置以接收一編程電壓； 一熔線器元件，包括與該編程電壓墊耦合的一第一端，和一第二端； 一鎖存器，包括一輸入端和一輸出端； 一操作開關單元，經配置以在一編程操作期間在該熔線器元件的該第二端和一接地端之間形成一電性連接，並經配置以在一讀取操作期間在該熔線器元件的該第二端和該鎖存器的該輸入端之間形成一電性連接； 複數個電阻器選擇墊；以及 複數個接合選項單元，其中該複數個接合選項單元中的每一個都包括一電阻器和一選擇開關，串聯在該鎖存器的該輸入端和該複數個電阻器選擇墊中的一相應電阻器選擇墊之間。 An electronic fuse control circuit, comprising: a programming voltage pad configured to receive a programming voltage; a fuse element including a first terminal coupled to the programming voltage pad, and a second terminal; A latch, including an input terminal and an output terminal; an operational switch unit configured to form an electrical connection between the second terminal of the fuse element and a ground terminal during a programming operation, and configured to connect the fuse element during a read operation forming an electrical connection between the second end of the device element and the input end of the latch; a plurality of resistor selection pads; and a plurality of engagement option cells, wherein each of the plurality of engagement option cells includes a resistor and a selection switch connected in series between the input of the latch and a corresponding resistor in the plurality of resistor selection pads to select between pads. 如請求項1所述的電子熔線控制電路，其中該熔線器元件是一反熔線器(antifuse)。The electronic fuse control circuit as claimed in claim 1, wherein the fuse element is an antifuse. 如請求項1所述的電子熔線控制電路，其中該複數個接合選項單元的電阻器具有不同的電阻值。The electronic fuse control circuit as claimed in claim 1, wherein the resistors of the plurality of bonding option units have different resistance values. 如請求項1所述的電子熔線控制電路，更包括一讀取開關，包括： 一第一端，與該熔線器元件的該第一端耦合； 一第二端，與該接地端耦合；以及 一控制端，經配置以接收一讀取控制訊號。 The electronic fuse control circuit as described in claim 1 further includes a read switch, including: a first end coupled to the first end of the fuse element; a second terminal coupled to the ground terminal; and A control terminal is configured to receive a read control signal. 如請求項1所述的電子熔線控制電路，其中該操作開關單元包括： 一第一開關，包括： 一第一端，與該熔線器元件的該第二端耦合； 一第二端；以及 一控制端，經配置以接收一讀取和編程控制訊號； 一第二開關，包括： 一第一端，與該第一開關的該第二端耦合； 一第二端，與該接地端耦合；以及 一控制端，經配置以接收一編程控制訊號；以及 一第三開關，包括： 一第一端，與該第一開關的該第二端耦合； 一第二端，與該鎖存器的該輸入端耦合；以及 一控制端，經配置以接收一讀取控制訊號。 The electronic fuse control circuit according to claim 1, wherein the operation switch unit includes: a first switch, comprising: a first end coupled to the second end of the fuse element; a second end; and a control terminal configured to receive a read and program control signal; a second switch, comprising: a first terminal coupled to the second terminal of the first switch; a second terminal coupled to the ground terminal; and a control terminal configured to receive a programming control signal; and a third switch, comprising: a first terminal coupled to the second terminal of the first switch; a second terminal coupled to the input terminal of the latch; and A control terminal is configured to receive a read control signal. 如請求項1所述的電子熔線控制電路，其中該鎖存器更包括： 一第一反相器，包括： 一輸入端，與該鎖存器的該輸入端耦合；以及 一輸出端，與該鎖存器的該輸出端耦合；以及 一第二反相器，包括： 一輸入端，與該鎖存器的該輸出端耦合；以及 一輸出端，與該鎖存器的該輸入端耦合。 The electronic fuse control circuit as claimed in item 1, wherein the latch further includes: a first inverter, comprising: an input coupled to the input of the latch; and an output coupled to the output of the latch; and a second inverter comprising: an input coupled to the output of the latch; and An output coupled to the input of the latch. 如請求項1所述的電子熔線控制電路，其中該複數個電阻器選擇墊中的至少一個在該讀取操作期間接收一讀取電壓，其中該讀取電壓小於該編程電壓。The electronic fuse control circuit of claim 1, wherein at least one of the plurality of resistor select pads receives a read voltage during the read operation, wherein the read voltage is less than the programming voltage. 一種半導體元件，包括： 一晶片，包括一電子熔線控制電路，該電子熔線控制電路包括： 一編程電壓墊，經配置以接收一編程電壓； 一熔線器元件，包括與該編程電壓墊耦合的一第一端，和一第二端； 一鎖存器，包括一輸入端和一輸出端； 一操作開關單元，經配置以在一編程操作期間在該熔線器元件的該第二端和一接地端之間形成一電性連接，並經配置以在一讀取操作期間在該熔線器元件的該第二端和該鎖存器的該輸入端之間形成一電性連接； 複數個電阻器選擇墊；以及 複數個接合選項單元，其中該複數個接合選項單元中的每一個都包括一電阻器和一選擇開關，串聯在該鎖存器的該輸入端和該複數個電阻器選擇墊中的一相應電阻器選擇墊之間；以及 一基底，包括： 一第一電壓接合墊，被接合到該編程電壓墊；以及 複數個第二電壓接合墊，其中該複數個第二電壓接合墊中的至少一個被接合到該複數個電阻器選擇墊中的至少一個。 A semiconductor element comprising: A chip, including an electronic fuse control circuit, the electronic fuse control circuit includes: a programming voltage pad configured to receive a programming voltage; a fuse element including a first terminal coupled to the programming voltage pad, and a second terminal; A latch, including an input terminal and an output terminal; an operational switch unit configured to form an electrical connection between the second terminal of the fuse element and a ground terminal during a programming operation, and configured to connect the fuse element during a read operation forming an electrical connection between the second end of the device element and the input end of the latch; a plurality of resistor selection pads; and a plurality of engagement option cells, wherein each of the plurality of engagement option cells includes a resistor and a selection switch connected in series between the input of the latch and a corresponding resistor in the plurality of resistor selection pads between the selector pads; and A base, including: a first voltage bonding pad bonded to the programming voltage pad; and A plurality of second voltage bond pads, wherein at least one of the plurality of second voltage bond pads is bonded to at least one of the plurality of resistor selection pads. 如請求項8所述的半導體元件，其中該熔線器元件是一反熔線器。The semiconductor device as claimed in claim 8, wherein the fuse element is an antifuse. 如請求項8所述的半導體元件，其中該複數個接合選項單元的電阻器具有不同的電阻值。The semiconductor device as claimed in claim 8, wherein the resistors of the plurality of bonding option units have different resistance values. 如請求項8所述的半導體元件，其中該電子熔線控制電路更包括一讀取開關，包括： 一第一端，與該熔線器元件的該第一端耦合； 一第二端，與該接地端耦合；以及 一控制端，經配置以接收一讀取控制訊號。 The semiconductor device as claimed in item 8, wherein the electronic fuse control circuit further includes a read switch, including: a first end coupled to the first end of the fuse element; a second terminal coupled to the ground terminal; and A control terminal is configured to receive a read control signal. 如請求項8所述的半導體元件，其中該操作開關單元包括： 一第一開關，包括： 一第一端，與該熔線器元件的該第二端耦合； 一第二端；以及 一控制端，經配置以接收一讀取和編程控制訊號； 一第二開關，包括： 一第一端，與該第一開關的該第二端耦合； 一第二端，與該接地端耦合；以及 一控制端，經配置以接收一編程控制訊號；以及 一第三開關，包括： 一第一端，與該第一開關的該第二端耦合； 一第二端，與該鎖存器的該輸入端耦合；以及 一控制端，經配置以接收一讀取控制訊號。 The semiconductor element according to claim 8, wherein the operation switch unit includes: a first switch, comprising: a first end coupled to the second end of the fuse element; a second end; and a control terminal configured to receive a read and program control signal; a second switch, comprising: a first terminal coupled to the second terminal of the first switch; a second terminal coupled to the ground terminal; and a control terminal configured to receive a programming control signal; and a third switch, comprising: a first terminal coupled to the second terminal of the first switch; a second terminal coupled to the input terminal of the latch; and A control terminal is configured to receive a read control signal. 如請求項8所述的半導體元件，其中該鎖存器包括： 一第一反相器，包括： 一輸入端，與該鎖存器的該輸入端耦合；以及 一輸出端，與該鎖存器的該輸出端耦合；以及 一第二反相器，包括： 一輸入端，與該鎖存器的該輸出端耦合；以及 一輸出端，與該鎖存器的該輸入端耦合。 The semiconductor element as claimed in claim 8, wherein the latch comprises: a first inverter, comprising: an input coupled to the input of the latch; and an output coupled to the output of the latch; and a second inverter comprising: an input coupled to the output of the latch; and An output coupled to the input of the latch. 如請求項8所述的半導體元件，其中被接合到該複數個第二電壓接合墊中的一第二電壓接合墊的一電阻器選擇墊經配置以在該讀取操作期間接收一讀取電壓，其中該讀取電壓小於該編程電壓。The semiconductor device as claimed in claim 8, wherein a resistor selection pad bonded to a second voltage bonding pad of the plurality of second voltage bonding pads is configured to receive a read voltage during the read operation , wherein the read voltage is less than the program voltage. 一種半導體元件的製備方法，包括： 提供包括一電子熔線控制電路的一晶片，其中該電子熔線控制電路包括一編程電壓墊、一熔線器元件、一鎖存器、複數個電阻器選擇墊以及複數個接合選項單元，該編程電壓墊與該熔線器元件的一第一端耦合，而該複數個接合選項單元中的每一個都包括一電阻器和一選擇開關，串聯在該鎖存器的該輸入端和該複數個電阻器選擇墊中的一相應電阻器選擇墊之間； 提供包括一第一電壓接合墊和複數個第二電壓接合墊的一基底； 將該晶片設置在該基底上； 將該第一電壓接合墊與該編程電壓墊接合；以及 將該複數個第二電壓接合墊中的至少一個與該複數個電阻器選擇墊中的至少一個接合。 A method for preparing a semiconductor element, comprising: A chip is provided that includes an electronic fuse control circuit, wherein the electronic fuse control circuit includes a programming voltage pad, a fuse element, a latch, a plurality of resistor selection pads, and a plurality of bonding option cells, the A programming voltage pad is coupled to a first end of the fuse element, and each of the plurality of bonding option cells includes a resistor and a selection switch connected in series between the input of the latch and the plurality of between a corresponding resistor selection pad in one resistor selection pad; providing a substrate including a first voltage bonding pad and a plurality of second voltage bonding pads; disposing the wafer on the substrate; bonding the first voltage bonding pad to the programming voltage pad; and At least one of the plurality of second voltage bonding pads is bonded to at least one of the plurality of resistor selection pads. 如請求項15所述的製備方法，更包括： 根據該熔線器元件的狀態來執行一測試操作，以決定將該複數個電阻器選擇墊中的該至少一個接合到該複數個第二電壓接合墊中的該至少一個。 The preparation method as described in claim item 15, further comprising: A test operation is performed according to the state of the fuse element to determine to bond the at least one of the plurality of resistor selection pads to the at least one of the plurality of second voltage bonding pads. 如請求項16所述的製備方法，其中根據該熔線器元件的狀態執行該測試操作，以決定將該複數個電阻器選擇墊中的該至少一個接合到該複數個第二電壓接合墊中的該至少一個，包括： 用該複數個接合選項單元中的一第一接合選項單元讀取該熔線器元件，以產生一第一讀取結果；以及 當該第一讀取結果確定為負向時，用該複數個接合選項單元中的一第二接合選項單元對該熔線器元件執行一讀取操作，以產生一第二讀取結果。 The manufacturing method as claimed in claim 16, wherein the test operation is performed according to the state of the fuse element to determine that at least one of the plurality of resistor selection pads is bonded to the plurality of second voltage bonding pads at least one of the following: reading the fuse element with a first bond option cell of the plurality of bond option cells to generate a first read result; and When the first read result is determined to be negative, a read operation is performed on the fuse element by using a second joint option unit of the plurality of joint option units to generate a second read result. 如請求項17所述的製備方法，其中根據該熔線器元件的狀態執行該測試操作，以決定將該複數個電阻器選擇墊中的該至少一個接合到該複數個第二電壓接合墊中的該至少一個，更包括： 當該第二讀取結果確定為正向時，決定將與該第二接合選項單元耦合的一電阻器選擇墊耦合至該複數個第二電壓接合墊中的該至少一個接合。 The manufacturing method as claimed in claim 17, wherein the test operation is performed according to the state of the fuse element to decide to bond the at least one of the plurality of resistor selection pads into the plurality of second voltage bonding pads At least one of the more included: When the second reading result is determined to be positive, it is determined to couple a resistor selection pad coupled with the second bonding option unit to the at least one bonding of the plurality of second voltage bonding pads. 如請求項17所述的製備方法，其中用該複數個接合選項單元中的該第一接合選項單元讀取該熔線器元件，以產生該第一讀取結果，包括： 將一讀取電壓施加到與該第一接合選項單元耦合的一電阻器選擇墊上； 導通該第一接合選項單元的一選擇開關； 將一接地電壓施加到該熔線器元件的該第一端；以及 將該熔線器元件的一第二端與該鎖存器的該輸入端耦合。 The manufacturing method as claimed in claim 17, wherein reading the fuse element with the first bonding option unit in the plurality of bonding option units to generate the first reading result comprises: applying a read voltage to a resistor select pad coupled to the first bond option cell; turning on a selection switch of the first joint option unit; applying a ground voltage to the first end of the fuse element; and A second terminal of the fuse element is coupled to the input terminal of the latch. 如請求項17所述的製備方法，其中執行該測試操作更包括： 在對該熔線器元件執行該讀取操作之前，藉由向該編程電壓墊施加一編程電壓並向該熔線器元件的該第二端施加一接地電壓，來對該熔線器元件執行一編程操作。 The preparation method as described in claim item 17, wherein performing the test operation further includes: performing the read operation on the fuse element by applying a programming voltage to the programming voltage pad and applying a ground voltage to the second terminal of the fuse element before performing the read operation on the fuse element a programming operation.
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