TW202042353A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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Publication number
TW202042353A
TW202042353A TW108120957A TW108120957A TW202042353A TW 202042353 A TW202042353 A TW 202042353A TW 108120957 A TW108120957 A TW 108120957A TW 108120957 A TW108120957 A TW 108120957A TW 202042353 A TW202042353 A TW 202042353A
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Taiwan
Prior art keywords
sealing body
semiconductor die
circuit layer
redistributed circuit
redistributed
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TW108120957A
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English (en)
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江家緯
方立志
范文正
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力成科技股份有限公司
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Publication of TW202042353A publication Critical patent/TW202042353A/zh

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Abstract

本發明提供一種半導體封裝及其製造方法。半導體封裝包括頂半導體晶粒、底半導體晶粒、第一密封體、第二密封體、第三密封體、第一重佈線路層以及第二重佈線路層。頂半導體晶粒堆疊在底半導體晶粒上。第三密封體橫向密封底半導體晶粒，且第三密封體被第一密封體橫向圍繞。第二密封體橫向密封頂半導體晶粒。第一重佈線路層設置在頂半導體晶粒及底半導體晶粒之間。底半導體晶粒、第一密封體及第三密封體位於第一重佈線路層及第二重佈線路層之間。

Description

半導體封裝及其製造方法
本發明是有關於一種半導體封裝及其製造方法，且特別是有關於一種具有多個半導體晶粒的半導體封裝及其製造方法。
近幾十年來，由於半導體晶粒中的電路積體密度的不斷提高，半導體工業快速成長。在大多數情況下，積體密度的提升是源於最小特徵尺寸連續減少，這允許將更多的元件集成至限定的區域中。近來，隨著對電子設備微型化的需求增加，對半導體晶粒的微型化及更有創意的封裝技術的需求不斷地提升。
本發明提供一種半導體封裝，包括頂半導體晶粒、底半導體晶粒、第一密封體、第二密封體、第三密封體、第一重佈線路層以及第二重佈線路層。頂半導體晶粒堆疊在底半導體晶粒上。第一密封體橫向圍繞底半導體晶粒。第二密封體橫向密封頂半導體晶粒。第三密封體橫向密封底半導體晶粒且被第一密封體橫向圍繞。第一重佈線路層設置在頂半導體晶粒及底半導體晶粒之間，且電性連接至頂半導體晶粒。底半導體晶粒、第一密封體及第三密封體位於第一重佈線路層及第二重佈線路層之間。第二重佈線路層電性連接至第一重佈線路層及底半導體晶粒。
在本發明的一實施例中，上述的頂半導體晶粒具有主動側與相對於主動側的背側。多個導電柱位於主動側。頂半導體晶粒的主動側面向第一重佈線路層。頂半導體晶粒的背側遠離第一重佈線路層。
在本發明的一實施例中，上述的頂半導體晶粒具有主動側與相對於主動側的背側。頂半導體晶粒的背側面向第一重佈線路層。頂半導體晶粒的主動側遠離第一重佈線路層，且藉由多條接合線電性連接至第一重佈線路層。
在本發明的一實施例中，上述的底半導體晶粒具有主動側與相對於主動側的一背側。多個導電柱位於主動側。底半導體晶粒的主動側面向第二重佈線路層。底半導體晶粒的背側遠離第一重佈線路層。
在本發明的一實施例中，上述的半導體封裝更包括晶粒黏著膜。晶粒黏著膜設置於底半導體晶粒的背側及第一重佈線路層之間。
在本發明的一實施例中，介面存在於第一密封體及第三密封體之間。
在本發明的一實施例中，上述的第三密封體的導熱率大於第一密封體的導熱率和第二密封體的導熱率。
在本發明的一實施例中，上述的第三密封體的楊氏模數大於第一密封體的楊氏模數和該第二密封體的楊氏模數。
在本發明的一實施例中，上述的第三密封體的整個側壁實質上被第一密封體覆蓋。
在本發明的一實施例中，上述的第一重佈線路層和第二重佈線路層透過貫穿第一密封體的密封體貫孔來彼此電性連接。
在本發明的一實施例中，上述的半導體封裝更包括多個電性連接件。電性連接件設置在第二重佈線路層遠離第一重佈線路層的表面。
本發明提供一種半導體封裝的製造方法，包括以下步驟。形成犧牲圖案在第一載板上。以第一密封體橫向密封犧牲圖案。形成第一重佈線路層在犧牲圖案及第一密封體上。貼附第一半導體晶粒在第一重佈線路層上。以第二密封體橫向密封第一半導體晶粒。貼附第二載板至第二密封體。從犧牲圖案及第一密封體分離第一載板。移除犧牲圖案以暴露出第一重佈線路層的一部分。貼附第二半導體晶粒至第一重佈線路層的暴露部分。以第三密封體橫向密封第二半導體晶粒。形成第二重佈線路層在第一密封體及第三密封體上。分離第二載板。
在本發明的一實施例中，上述的第一半導體晶粒藉由覆晶製程貼附在第一重佈線路層上。
在本發明的一實施例中，上述的第一半導體晶粒藉由打線接合製程貼附在第一重佈線路層上。
在本發明的一實施例中，上述的第二半導體晶粒藉由晶粒黏著膜貼附至第一重佈線路層。
在本發明的一實施例中，上述的半導體封裝的製造方法，更包括形成貫穿第一密封體的密封體貫孔。
在本發明的一實施例中，上述的形成密封體貫孔的步驟是在分離第一載板的步驟之後，以及在移除犧牲圖案的步驟之前。
在本發明的一實施例中，上述的形成密封體貫孔的步驟是在形成第一重佈線路層的步驟之前。
在本發明的一實施例中，上述的半導體封裝的製造方法，更包括形成多個電性連接件在第二重佈線路層遠離第一重佈線路層的一側。
在本發明的一實施例中，上述的犧牲圖案包括光敏性材料。
基於上述，本發明的實施例的半導體封裝是三維封裝結構。半導體封裝包括底半導體晶粒（即，第二半導體晶粒）和堆疊在底半導體晶粒上的頂半導體晶粒（即，第一半導體晶粒）。頂半導體晶粒和底半導體晶粒分別由密封體（即，第二密封體和第三密封體）密封，並且密封底半導體晶粒（即，第三密封體）的密封體被另一密封體（即，第一密封體）橫向圍繞。此外，半導體封裝包括至少一重佈線路層（即，第一重佈線路層和第二重佈線路層），用於對頂半導體晶粒和底半導體晶粒進行外部佈線以及實現頂半導體晶粒和底半導體晶粒之間的通信。在半導體封裝的製造期間，底半導體晶粒的貼附區限制在曾被犧牲圖案佔據且被第一密封體圍繞的空間中。因此可減少在底半導體晶粒貼附期間的底半導體晶粒的錯位，以及在後續製程中因必然的熱導致的底半導體晶粒的偏移。如此一來，可提升半導體封裝製程的產量。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1是本發明一些實施例的半導體封裝的製造方法的流程圖。圖2A至圖2K是圖1的半導體封裝的製造方法的各階段結構的剖面示意圖。
請參照圖1與圖2A，執行步驟S100，形成犧牲圖案100在第一載板CA1上。第一載板CA1例如是玻璃基板。在一些實施例中，預先形成黏著層102在第一載板CA1的表面上，隨後於其上形成犧牲圖案100。黏著層102例如是光熱轉換（light-to-heat conversion；LTHC）層或熱釋放層（thermal release layer）。僅管在圖2A中僅繪示單個犧牲圖案100，實際上可以在第一載板CA1上形成多個犧牲圖案100。犧牲圖案100彼此橫向分離。每個犧牲圖案100的面積可以大於半導體晶粒的面積（如圖2H所示的第二半導體晶粒SD2），如此以使半導體晶粒可以容置在曾被犧牲圖案100佔據的空間中（如圖2H所示的腔體CV）。舉例來說，每個犧牲圖案100的面積可以在50 mm2 至225 mm2 的範圍內。形成犧牲圖案100的方法可以包括形成覆蓋材料層（未繪示）在第一載板CA1上，接著圖案化覆蓋材料層以形成犧牲圖案100。在一些實施例中，用於形成犧牲圖案100的覆蓋材料層的材料是光敏性材料，例如正光阻（positive type photoresist）或負光阻（negative type photoresist）。在這些實施例中，在覆蓋材料層上執行的圖案化製程可以是光刻製程（photolithography process）。
請參照圖1與圖2B，執行步驟S102，以第一密封體104橫向密封犧牲圖案100。在一些實施例中，犧牲圖案100可先由密封材料包覆，接著在密封材料上執行平坦化製程，暴露出犧牲圖案100且形成第一密封體104。第一密封體104的材料例如可包括環氧樹脂（epoxy resin）、聚酰亞胺（polyimide）、二氧化矽（silica）等或其組合。再者，平坦化製程可以包括化學機械拋光（chemical mechanical polishing；CMP）製程、蝕刻製程（etching process）、研磨製程（grinding process）或其組合。在一些實施例中，如圖2B所示，第一密封體104遠離第一載板CA1的表面實質上與犧牲圖案100的暴露表面共平面。
請參照圖1與圖2C，執行步驟S104，形成第一重佈線路層在犧牲圖案及第一密封體上。在一些實施例中，第一重佈線路層106包括絕緣層108的堆疊，以及在絕緣層108的堆疊中形成重佈線路元件110。重佈線路元件110實質上分佈於絕緣層108的整個範圍，並且與犧牲圖案100和第一密封體104交疊。重佈線路元件110可以分別為導電線（conductive trace）、導電通孔（conductive via）或其組合。導電線實質上沿著平行於絕緣層108延伸方向的一個或多個方向延伸，而導電通孔貫穿至少一絕緣層108且電性連接至一導電線。在一些實施例中，絕緣層108的材料包括聚合材料，重佈線路元件110的材料包括金屬或金屬合金。舉例來說，聚合材料可包括聚酰亞胺、聚苯並噁唑（polybenzoxazole；PBO）、苯並環丁烯（benzocyclobutene；BCB）等或其組合，而金屬/金屬合金包括銅、鎳、鈦等或其組合。在替代實施例中，絕緣層108是無機絕緣層，且由例如是氧化矽、氮化矽等製成。
請參照圖1與圖2D，執行步驟S106，貼附第一半導體晶粒在第一重佈線路層上。如圖2D所示，儘管在圖2中僅繪示了單個第一半導體晶粒SD1，實際上可以貼附多個第一半導體晶粒SD1至第一重佈線路層106上。貼附的第一半導體晶粒SD1橫向分離，並分別與犧牲圖案100交疊。在某些實施例中，第一半導體晶粒SD1可以分別位在下方犧牲圖案100的範圍內。然而，本領域技術人員可以修改犧牲圖案100和第一半導體晶粒SD1的配置，本發明不限於此。在一些實施例中，第一半導體晶粒SD1可以分別是邏輯積體電路（Logic integrated circuit；Logic IC）晶粒、記憶體積體電路（Memory IC）晶粒、類比邏輯積體電路（Analog IC）晶粒或特殊應用積體電路（Application specific IC；ASIC）晶粒等。每個第一半導體晶粒SD1具有主動側AS1，多個導電柱CP1位於主動側AS1，且具有相對於主動側AS1的背側BS1。在一些實施例中，第一半導體晶粒SD1藉由覆晶製程貼附在第一重佈線路層106上。在這些實施例中，導電柱CP1接觸並電性連接至第一重佈線路層106中最頂部的重佈線路元件110。換句話說，第一半導體晶粒SD1的主動側AS1面向第一重佈線路層106，而第一半導體晶粒SD1的背側BS1遠離第一重佈線路層106。在替代實施例中，第一半導體晶粒SD1可以藉由打線接合製程貼附在第一重佈線路層上106上。在這些替代實施例中，第一半導體晶粒SD1的主動側AS1遠離第一重佈線路層106，且藉由多條接合線（未繪示）電性連接至第一重佈線路層106，而第一半導體晶粒SD1的背側BS1面向第一重佈線路層106。此外，在這些替代實施例中，每個第一半導體晶粒SD1可由半導體晶粒的堆疊（未繪示）取代。
接著，執行步驟S108，以第二密封體112橫向密封第一半導體晶粒SD1。在一些實施例中，第一半導體晶粒SD1被第二密封體112包覆，且埋入第二密封體112中。第二密封體112的材料可包括環氧樹脂、聚酰亞胺、二氧化矽等或其組合。至此，目前的封裝結構包括兩個密封體（即，第一密封體104和第二密封體112）的堆疊，其經由第一重佈線路層106彼此垂直分離。
請參照圖1、圖2D與圖2E，執行步驟S110，貼附第二載板CA2至第二密封體112，以及從目前的封裝結構分離第一載板CA1。第二載板CA2貼附至第二密封體112遠離第一重佈線路層106的表面上。在一些實施例中，預先形成黏著層114在第二載板CA2貼附第二密封體112的表面上。黏著層114例如是光熱轉換（light-to-heat conversion；LTHC）層或熱釋放層（thermal release layer）。另一方面，在第一載板CA1上形成的黏著層102是光熱轉換層或熱釋放層的那些實施例中，當黏著層102暴露在光或熱而失去黏著性，使第一載板CA1從目前的封裝結構分離。在分離第一載板CA1之後，現暴露出第一密封體104和犧牲圖案100遠離第一重佈線路層106的表面。
請參照圖1、圖2E與圖2F，執行步驟S112，倒轉目前圖2E所示的結構，且形成密封體貫孔116在第一密封體104中。密封體貫孔116貫穿第一密封體104，並且電性連接至第一重佈線路層106中的重佈線路元件110。在一些實施例中，用於形成密封體貫孔116的方法包括藉由例如機械鑽孔製程或雷射鑽孔製程，移除第一密封體104的一部分以在第一密封體104中形成通孔。隨後，將導電材料填入至第一密封體104的通孔中以形成密封體貫孔116。導電材料例如可包括銅、鈦、鋁、鎳等或其組合。在一些實施例中，導電材料可以先延伸至第一密封體104和犧牲圖案100的暴露表面上，接著可在導電材料上執行平坦化製程，移除在第一密封體104和犧牲圖案100的暴露表面上的導電材料的部分，以形成密封體貫孔116。舉例來說，平坦化製程可以包括化學機械拋光製程、蝕刻製程、研磨製程或其組合。在一些實施例中，密封體貫孔116的暴露表面實質上與第一密封體104和犧牲圖案100的暴露表面共平面。
根據前述實施例，形成密封體貫孔116的步驟在形成第一重佈線路層106和貼附第一半導體晶粒SD1的步驟之後執行。然而，在替代實施例中，形成密封體貫孔116的步驟可以在形成第一重佈線路層106和貼附第一半導體晶粒SD1的步驟之前執行。在這些替代實施例中，形成密封體貫孔116的步驟可以在藉由第一密封體104橫向密封犧牲圖案100的步驟之後（如圖2B所示），以及在形成第一重佈線路層106的步驟之前執行（如圖2C所示）。
請參照圖1、圖2F與圖2G，執行步驟S114，移除犧牲圖案100。在一些實施例中，藉由剝離製程（stripping process）或蝕刻製程以移除犧牲圖案100。一旦移除犧牲圖案100以形成腔體CV在第一密封體104中，且藉由腔體CV暴露出第一重佈線路層的一部分。如圖2F和圖2G所示，腔體CV是被犧牲圖案100佔據的空間。同犧牲圖案100，腔體CV分別與第一半導體晶粒SD1交疊。另外，在某些實施例中，每個第一半導體晶粒SD1是位在交疊腔體CV的範圍中。
請參照圖1、圖2G與圖2H，執行步驟S116，貼附第二半導體晶粒SD2在第一重佈線路層106的暴露部分上。貼附的第二半導體晶粒SD2分別位於腔體CV中，並且與第一半導體晶粒SD1交疊。在一些實施例中，每個腔體CV的邊界與對應的第二半導體晶粒SD2之間的間隔SP可以在25μm至30μm的範圍內。此外，位於第一密封體104的腔體CV中的第二半導體晶粒SD2和埋入第二密封體112中的第一半導體晶粒SD1可以是相同類型的半導體晶粒，或者可以是不同類型的半導體晶粒。在一些實施例中，第二半導體晶粒SD2分別是邏輯積體電路晶粒、記憶體積體電路晶粒、類比邏輯積體電路晶粒或特殊應用積體電路晶粒等。每個第二半導體晶粒SD2具有主動側AS2，多個導電柱CP2位於主動側AS2，以及具有相對於主動側AS2的背側BS2。第二半導體晶粒SD2的背側BS2面向第一重佈線路層106，而第二半導體晶粒SD2的主動側AS2遠離第一重佈線路層106。在一些實施例中，每個第二半導體晶粒SD2的背側BS2可以藉由晶粒黏著膜（die attach film；DAF）118貼附至第一重佈線路層106。在這些實施例中，在第二半導體晶粒SD2貼附至第一重佈線路層層106上之前，可以預先形成晶粒黏著膜118在第二半導體晶粒SD2的背側BS。或者，在第二半導體晶粒SD2貼附至第一重佈線路層106上之前，可以預先形成晶粒黏著膜118在第一重佈線路層106的暴露部分。
請參照圖1與圖2I，執行步驟S118，以第三密封體120橫向密封第二半導體晶粒SD2。每個第三密封體120可以認為被第一密封體104圍繞，以及第一密封體104與第三密封體120經由第一重佈線路層106與下方第二密封體112垂直分離。在一些實施例中，每個第三密封體120的整個側壁實質上被第一密封體104覆蓋。用於形成第三密封體120的方法可以包括將密封材料填入至第一密封體104的腔體CV（如圖2H所示）中。密封材料可以填充腔體CV，並且延伸至第一密封體104和密封體貫孔116的表面上。隨後，可以對密封材料執行平坦化製程，移除在第一密封體104和密封體貫孔116的表面上的封裝材料的部分，以形成第三密封體120。舉例來說，平坦化製程可以包括平坦化製程可以包括化學機械拋光製程、蝕刻製程、研磨製程或其組合。在一些實施例中，第三密封體120的暴露表面實質上與第一密封體104、密封體貫孔116以及第二半導體晶粒SD2的導電柱CP2的暴露表面共平面。
在一些實施例中，第三密封體120的材料不同於第一密封體104和第二密封體112的材料。在這些實施例中，第三密封體120的導熱率可以大於第一密封體104的導熱率和第二密封體112的導熱率，且可以改善埋入第三密封體120中的第二半導體晶粒SD2的散熱。例如，第三密封體120的導熱率可高達3W / mK，而第一密封體104的導熱率和第二密封體112的導熱率可分別高達0.7W / mK。此外，在這些實施例中，第三密封體120的楊氏模數可以大於第一密封體104的楊氏模數和第二密封體112的楊氏模數，且可以改善埋入第三密封體120中的第二半導體晶粒SD2的機械性保護。例如，第三密封體120的楊氏模數可高達30GPa，而第一密封體104的楊氏模數和第二密封體112的楊氏模數可分別高達15GPa。
在替代實施例中，第三密封體120的材料與第一密封體104的材料和/或第二密封體112的材料相同。應注意的是，即使第一密封體104和第三密封體120由相同的材料製成，因為第一密封體104和第三密封體120在不同的步驟形成，所以仍然可以觀察到第一密封體104和第三密封體120之間的界面IF。
請參照圖1、圖2I與圖2J，執行步驟S120，形成第二重佈線路層122在第一密封體104及第三密封體120上。在一些實施例中，第二重佈線路層122整體地形成在圖2I所示的封裝結構上。如此，第一密封體104、密封體貫孔116、第三密封體120以及第二半導體晶粒SD2的導電柱CP2的表面是被第二重佈線路層122覆蓋。第二重佈線路層122電性連接至密封體貫孔116和第二半導體晶粒SD2的導電柱CP2。如此，第一半導體晶粒SD1和第二半導體晶粒SD2的外部佈線可以藉由第一重佈線路層106、密封體貫孔116和第二重佈線路層122實現第一半導體晶粒SD1和第二半導體晶粒SD2之間的通信。在一些實施例中，第二重佈線路層122包括絕緣層124的堆疊和形成在絕緣層124的堆疊中的多個重佈線路元件126。重佈線路元件126電性連接至密封體貫孔116和第二半導體晶粒SD2的導電柱CP2，且密封體貫孔116和導電柱CP2實質上扇出至絕緣層124的整個區域。在一些實施例中，重佈線路元件126分別為導電線、導電通孔或其組合。導電線實質上沿著平行於絕緣層124延伸方向的一個或多個方向延伸，而導電通孔貫穿至少一絕緣層124且電性連接至一導電線。在一些實施例中，絕緣層124的材料包括聚合材料，重佈線路元件126的材料包括金屬或金屬合金。例如，聚合材料可包括聚酰亞胺、聚苯並噁唑、苯並環丁烯等或其組合，而金屬/金屬合金包括銅、鎳、鈦等或其組合。在替代實施例中，絕緣層124是無機絕緣層，且由例如是氧化矽或氮化矽等製成。
接著，執行步驟S122，形成多個電性連接件128。電性連接件128形成在目前的封裝結構上，且可以延伸至第二重佈線路層122中最頂部的絕緣層124，以電性連接至第二重佈線路層122中的重佈線路元件126。用於形成電性連接件128的方法可以包括移除最頂部的絕緣層124的一些部分以形成開口，並暴露出重佈線路元件126的一部分。隨後，電性連接件128分別設置在重佈線路元件126的暴露部分上。在一些實施例中，在設置電性連接件128之前，底部金屬層（under ball metallization layer；UBM layer）130分別形成在最頂部的絕緣層124的開口中。如此，在設置電性連接件128之後分別位於電性連接件128和第二重佈線路層122之間。在一些實施例中，底部金屬層130更延伸到上述開口外最頂部的絕緣層124的表面上。電性連接件128可包括微凸塊（micro-bump）、覆晶互連技術（controlled collapse chip connection；C4）凸塊、球柵陣列封裝（Ball Grid Array；GBA）球或焊球（solder ball）等。此外，底部金屬層130的材料可包括Cr、Cu、Ti、W、Ni、Al等或其組合。
請參照圖1、圖2J與圖2K，執行步驟S124，從第二密封體112分離第二載板CA2。在第二載板CA2上形成的黏著層114是光熱轉換層或熱釋放層的那些實施例中，當黏著層114暴露在光或熱而失去黏著性時，使第二載板CA2從目前的封裝結構分離。在分離第二載板CA2之後，現暴露出第二密封體112遠離第一重佈線路層106的表面。此外，如圖2K所示，倒轉目前的封裝結構。在一些實施例中，對目前的封裝結構進行單體化製程（singulation process），例如切割製程（dicing process）、鋸切製程（sawing process）或雷射燒蝕製程（laser ablation process）。在單體化製程中，封裝結構可以貼附至膠帶（tape）或另一載板（未繪示）上，並且在單體化步驟之後移除這種膠帶或載板。圖2K所示的單個封裝結構即為半導體封裝10。半導體封裝10包括半導體晶粒（即，第一半導體晶粒SD1和第二半導體晶粒SD2）的堆疊，每個半導體晶粒至少由密封體（即，第一密封體104，第二密封體112和第三密封體120）密封。且至少包括重佈線路層（例如，第一重佈線路層106和第二重佈線路層122），其用於對半導體晶粒進行外部佈線，以及實現半導體晶粒之間的通信。因此，半導體封裝10可以被視為三維封裝結構，例如扇出封裝（fan-out package-on-package；PoP）結構。在一些實施例中，單體化製程的結果，第一密封體104的側壁實質上與第二密封體112的側壁共平面。
在上述實施例中，形成電性連接件128的步驟、分離第二載板CA2的步驟和單體化的步驟是依序地執行。本發明對執行這些步驟的順序並不加以限制。
如上所述，本發明的一些實施例的半導體封裝10是三維封裝結構。半導體封裝10包括底半導體晶粒（即，第二半導體晶粒SD2）和堆疊在底半導體晶粒上的頂半導體晶粒（即，第一半導體晶粒SD1）。頂半導體晶粒和底半導體晶粒分別由密封體（即，第二密封體112和第三密封體120）密封，且密封底半導體晶粒的密封體（即，第三密封體120）由另一密封體橫向圍繞（即，第一密封體104）。此外，半導體封裝10包括至少一個重佈線路層（例如，第一重佈線路層106和第二重佈線路層122），用於對頂半導體晶粒和底半導體晶粒進行外部佈線，以及實現頂半導體晶粒和底半導體晶粒之間的通信。在半導體封裝10的製造期間，底半導體晶粒的貼附區被限制在由圍繞的第一密封劑104所限定的腔體（即，圖2H所示的腔體CV）。因此，可減少在底半導體晶粒貼附期間的底半導體晶粒的錯位，以及在後續製程中因必然的熱所導致的底半導體晶粒的偏移。如此一來，可提升半導體封裝製程的產量。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
S100、S102、S104、S106、S108、S110、S112、S114、S116、S118、S120、S122、S124:步驟 10:半導體封裝 100:犧牲圖案 102、114:黏著層 104:第一密封體 106:第一重佈線路層 108、124:絕緣層 110、126:重佈線路元件 112:第二密封體 116:密封體貫孔 118:晶粒黏著膜 120:第三密封體 122:第二重佈線路層 128:電性連接件 130:底部金屬層 AS1、AS2:主動側 BS1、BS2:背側 CA1:第一載板 CA2:第二載板 CP1、CP2:導電柱 CV:腔體 IF:界面 SD1:第一半導體晶粒 SD2:第二半導體晶粒 SP:間隔
包括附圖以提供對本發明的進一步理解，並且附圖併入本說明書中並構成本說明書的一部分。附圖示出了本發明的示例性實施例，並且與說明書一起用於解釋本發明的原理。 圖1是本發明一些實施例的半導體封裝的製造方法的流程圖。 圖2A至圖2K是圖1的半導體封裝的製造方法的各階段結構的剖面示意圖。
10:半導體封裝
104:第一密封體
106:第一重佈線路層
112:第二密封體
116:密封體貫孔
118:晶粒黏著膜
120:第三密封體
122:第二重佈線路層
128:電性連接件
130:底部金屬層
CP1、CP2:導電柱
IF:界面
SD1:第一半導體晶粒
SD2:第二半導體晶粒

Claims (10)

  1. 一半導體封裝，包括： 一頂半導體晶粒及一底半導體晶粒，其中該頂半導體晶粒堆疊在該底半導體晶粒上； 一第一密封體，橫向圍繞該底半導體晶粒； 一第二密封體，橫向密封該頂半導體晶粒； 一第三密封體，橫向密封該底半導體晶粒且被該第一密封體橫向圍繞； 一第一重佈線路層，設置在該頂半導體晶粒及該底半導體晶粒之間，且電性連接至該頂半導體晶粒；以及 一第二重佈線路層，其中該底半導體晶粒、該第一密封體及該第三密封體位於該第一重佈線路層及該第二重佈線路層之間，且其中該第二重佈線路層電性連接至該第一重佈線路層及該底半導體晶粒。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該頂半導體晶粒具有一主動側與相對於該主動側的一背側，多個導電柱位於該主動側，該頂半導體晶粒的該主動側面向該第一重佈線路層，且該頂半導體晶粒的該背側遠離該第一重佈線路層。
  3. 如申請專利範圍第1項所述的半導體封裝，其中該頂半導體晶粒具有一主動側與相對於該主動側的一背側，該頂半導體晶粒的該背側面向該第一重佈線路層，以及該頂半導體晶粒的該主動側遠離該第一重佈線路層，且藉由多條接合線電性連接至該第一重佈線路層。
  4. 如申請專利範圍第1項所述的半導體封裝，其中該底半導體晶粒具有一主動側與相對於該主動側的一背側，多個導電柱位於該主動側，該底半導體晶粒的該主動側面向該第二重佈線路層，且該底半導體晶粒的該背側遠離該第一重佈線路層。
  5. 如申請專利範圍第1項所述的半導體封裝，其中該第三密封體的導熱率大於該第一密封體的導熱率和該第二密封體的導熱率，且該第三密封體的楊氏模數大於該第一密封體的楊氏模數和該第二密封體的楊氏模數。
  6. 如申請專利範圍第1項所述的半導體封裝，其中該第三密封體的整個側壁實質上被該第一密封體覆蓋。
  7. 如申請專利範圍第1項所述的半導體封裝，其中該第一重佈線路層和該第二重佈線路層透過貫穿該第一密封體的一密封體貫孔來彼此電性連接。
  8. 一種半導體封裝的製造方法，包括： 形成一犧牲圖案在一第一載板上； 以一第一密封體橫向密封該犧牲圖案； 形成一第一重佈線路層在該犧牲圖案及該第一密封體上； 貼附一第一半導體晶粒在該第一重佈線路層上； 以一第二密封體橫向密封該第一半導體晶粒； 貼附一第二載板至該第二密封體； 從該犧牲圖案及該第一密封體分離該第一載板； 移除該犧牲圖案以暴露出該第一重佈線路層的一部分; 貼附一第二半導體晶粒至該第一重佈線路層的該部分； 以一第三密封體橫向密封該第二半導體晶粒； 形成一第二重佈線路層在該第一密封體及該第三密封體上；以及 分離該第二載板。
  9. 如申請專利範圍第8項所述的半導體封裝的製造方法，更包括形成貫穿該第一密封體的一密封體貫孔，其中形成該密封體貫孔的步驟是在分離該第一載板的步驟之後，以及在移除該犧牲圖案的步驟之前。
  10. 如申請專利範圍第8項所述的半導體封裝的製造方法，更包括形成貫穿該第一密封體的一密封體貫孔，其中形成該密封體貫孔的步驟是在形成該第一重佈線路層的步驟之前。
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