TW201633052A - External power supply and system connection detection unit applied thereto - Google Patents
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Description
本發明有關於一種電源供應器,且特別是一種外部電源供應器以及應用於外部電源供應器之系統連接偵測單元。 The invention relates to a power supply, and in particular to an external power supply and a system connection detecting unit applied to an external power supply.
近年來環保意識的提升,與全球暖化問題,迫使節約能源成為世界各國重要政策之一。美國能源局(Department of Energy)對於各項資訊電子設備也相對制定更低能耗的規範以去達到節能的目的,如在外部電源供應器上有Energy efficiency level VI需求(Eff.>88%,Pin<0.21W @ no load),歐盟亦研擬導入實施外部電源供應器之進一步節能規範CoC tier I(Eff.>89%,Pin<0.25W at no load)& tier II(Eff.>89%,Pin<0.15W at no load),所以降低外部電源轉換器之功耗是所屬技術領域之人員目前必須克服的課題。而在能耗要求持續提升下,為達極低之轉換器功耗,採突發模式(burst-mode)控制方式已不足以達到要求,因而採用深度睡眠模式(deep sleeping mode)之外部電源開始被廣泛使用。 In recent years, the promotion of environmental awareness and global warming have forced energy conservation to become one of the important policies of all countries in the world. The US Department of Energy also sets a lower energy consumption specification for various information electronic devices to achieve energy saving purposes, such as energy efficiency level VI requirements on external power supplies (Eff.>88%, Pin <0.21W @ no load), the EU is also planning to introduce further energy-saving specifications for implementing external power supplies, CoC tier I (Eff.>89%, Pin<0.25W at no load)& tier II (Eff.>89%, Pin<0.15W at no load), so reducing the power consumption of the external power converter is a problem that must be overcome by those skilled in the art. With the continuous improvement of energy consumption requirements, the burst-mode control method is not enough to meet the requirements for the extremely low converter power consumption. Therefore, the external power supply with deep sleeping mode is used. being widely used.
如圖1所示,深度睡眠模式因其於無載時利用電源供應器(Power Supply Unit,PSU)以極長之休眠時間歇式工作,進而達到極低之輸入功耗。狀態SA是睡眠時電壓下降,直到電壓低於某一程度時進入狀態SB以進行功率開關切換藉此提升電壓。然而,因其間歇工作之間隔過長,導致輸出電壓會做極大幅度之上升與下 降,而無法穩定於一般系統工作時所需之直流電壓。當系統啟動運作時(例如電腦開機)即系統負載產生時(時間點T1),通常利用電流偵測方式使電源供應器在偵測到系統抽載電流後才啟動正常工作模式。因輸出電壓不穩定緣故,若於無電池之電腦系統使用此工作方式,則系統抽載時因電源供應器不及恢復正常工作模式而造成電壓過低,如圖1所示在時間點T1之後的壓降幅度相當大。如此可能導致系統工作異常,故傳統上此模式一般僅應用(或適用)於配備電池之電腦系統(如筆記型電腦)。 As shown in Figure 1, the deep sleep mode uses a Power Supply Unit (PSU) for intermittent operation during extremely long sleep periods, resulting in extremely low input power consumption. The state SA is a voltage drop during sleep until the voltage is below a certain level and enters the state SB for power switching to thereby boost the voltage. However, due to the long interval between intermittent operations, the output voltage will rise to a very large extent. It is not stable enough to stabilize the DC voltage required for normal system operation. When the system starts up (for example, when the computer is turned on), that is, when the system load is generated (time point T1), the current detection mode is usually used to enable the power supply to start the normal operation mode after detecting the system load current. Due to the unstable output voltage, if this working mode is used in a batteryless computer system, the voltage is too low due to the power supply being unable to return to the normal working mode when the system is pumping, as shown in Figure 1 after time T1. The pressure drop is quite large. This may cause the system to work abnormally, so this mode has traditionally only applied (or applied) to computer systems equipped with batteries (such as notebook computers).
本發明實施例提供一種外部電源供應器以及應用於外部電源供應器之偵測單元,以對先前技術的問題進行改良,加入系統連接偵測單元並以電壓偵測方式偵測系統的輸入信號(電壓偵測信號),以電路調整電源供應器之工作模式。於無系統連接/無負載時進入深度睡眠模式,以達極低之輸入功耗以符合國際能源法規。於連接系統時電源供應器即恢復正常工作模式,使輸出穩定於直流,以解決因電壓過低系統工作異常之問題,且使外部電源供應器可應用於無電池之電腦系統(例如桌上型電腦)、顯示器或電視等。 An embodiment of the present invention provides an external power supply and a detection unit applied to an external power supply to improve the prior art problem by adding a system connection detection unit and detecting an input signal of the system by voltage detection ( Voltage detection signal), the circuit adjusts the working mode of the power supply. Enter deep sleep mode when there is no system connection/no load to achieve extremely low input power consumption to comply with international energy regulations. When the system is connected, the power supply returns to the normal working mode, the output is stabilized to DC, to solve the problem of abnormal operation of the system due to low voltage, and the external power supply can be applied to the batteryless computer system (such as desktop type). Computer), monitor or TV.
本發明實施例提供一種外部電源供應器,所述外部電源供應器具有正常工作模式與深度睡眠模式,外部電源供應器用以分別透過正輸出端與負輸出端可分離地連接至一系統之正輸入端與負輸入端,藉此提供電力至所述系統。當所述正輸出端與負輸出端未連接至所述系統之正輸入端與負輸入端時,所述外部電源供應器操作於深度睡眠模式。所述外部電源供應器包括電力供應單元以及系統連接偵測單元。電力供應單元電性連接至正輸出端與負輸出端,電力供應單元將外部電源轉換為直流電力。當正輸出端與負輸出端分別連接至所述系統之正輸入端與負輸入端時,電力供應單元將直流電力傳送至所述系統。系統連接偵測單元電性連 接電力供應單元,並用於偵測外部電源供應器與系統的連接狀態,系統連接偵測單元具有系統偵測端。當正輸出端與負輸出端分別連接至所述系統之正輸入端與負輸入端時,系統偵測端用以連接至所述系統之系統連接端,其中系統連接端透過至少一第一電阻性元件電性連接至所述系統之正輸入端與負輸入端的其中之一。系統連接偵測單元偵測所述系統偵測端之電壓並據此產生連接狀態信號,當正輸出端與負輸出端分別連接至所述系統之正輸入端與負輸入端時,系統連接偵測單元產生之連接狀態信號使所述外部電源供應器的操作由深度睡眠模式切換為正常工作模式。 An embodiment of the present invention provides an external power supply device having a normal working mode and a deep sleep mode, wherein an external power supply is detachably connected to a positive input of a system through a positive output terminal and a negative output terminal, respectively. End and negative inputs, thereby providing power to the system. The external power supply operates in a deep sleep mode when the positive and negative outputs are not connected to the positive and negative inputs of the system. The external power supply includes a power supply unit and a system connection detection unit. The power supply unit is electrically connected to the positive output terminal and the negative output terminal, and the power supply unit converts the external power source into DC power. When the positive output terminal and the negative output terminal are respectively connected to the positive input terminal and the negative input terminal of the system, the power supply unit transmits DC power to the system. System connection detection unit electrical connection The power supply unit is connected and used to detect the connection status between the external power supply and the system, and the system connection detection unit has a system detection end. When the positive output terminal and the negative output terminal are respectively connected to the positive input terminal and the negative input terminal of the system, the system detecting end is connected to the system connection end of the system, wherein the system connection end transmits at least one first resistor The sexual element is electrically coupled to one of a positive input and a negative input of the system. The system connection detecting unit detects the voltage of the detecting end of the system and generates a connection state signal according to the same. When the positive output terminal and the negative output terminal are respectively connected to the positive input terminal and the negative input terminal of the system, the system connection detection The connection status signal generated by the measurement unit causes the operation of the external power supply to be switched from the deep sleep mode to the normal operation mode.
本發明實施例提供一種應用於外部電源供應器之系統連接偵測單元,所述外部電源供應器具有正常工作模式與深度睡眠模式,所述外部電源供應器用以分別透過正輸出端與負輸出端可分離地連接至一系統之正輸入端與負輸入端,藉此提供電力至所述系統。當正輸出端與負輸出端未連接至所述系統之正輸入端與負輸入端時,所述外部電源供應器操作於深度睡眠模式。所述系統連接偵測單元用於偵測外部電源供應器與系統的連接狀態,所述系統連接偵測單元包括系統偵測端、電源阻抗匹配電路以及邏輯電路。當正輸出端與負輸出端分別連接至所述系統之正輸入端與負輸入端時,所述系統偵測端用以連接至所述系統之系統連接端,其中所述系統連接端透過至少一第一電阻性元件電性連接至所述系統之正輸入端與負輸入端的其中之一。電源阻抗匹配電路電性連接所述系統偵測端,依據所述系統偵測端之電壓產生電壓偵測信號。邏輯電路將電壓偵測信號與參考信號做比較而產生連接狀態信號,其中參考信號的電壓介於正輸出端與負輸出端之間的電壓。當正輸出端與負輸出端分別連接至所述系統之正輸入端與負輸入端時,所述系統連接偵測單元產生之連接狀態信號使所述外部電源供應器的操作由深度睡眠模式切換為正常工作模式。 An embodiment of the present invention provides a system connection detecting unit applied to an external power supply, wherein the external power supply has a normal working mode and a deep sleep mode, and the external power supply is configured to respectively pass through the positive output terminal and the negative output terminal. The positive input and the negative input are detachably coupled to a system, thereby providing power to the system. The external power supply operates in a deep sleep mode when the positive and negative outputs are not connected to the positive and negative inputs of the system. The system connection detecting unit is configured to detect a connection state between the external power supply and the system, and the system connection detecting unit includes a system detecting end, a power source impedance matching circuit, and a logic circuit. When the positive output terminal and the negative output terminal are respectively connected to the positive input terminal and the negative input terminal of the system, the system detecting end is connected to the system connection end of the system, wherein the system connection end transmits at least A first resistive element is electrically coupled to one of a positive input and a negative input of the system. The power impedance matching circuit is electrically connected to the detecting end of the system, and generates a voltage detecting signal according to the voltage of the detecting end of the system. The logic circuit compares the voltage detection signal with the reference signal to generate a connection state signal, wherein the voltage of the reference signal is between the positive output terminal and the negative output terminal. When the positive output terminal and the negative output terminal are respectively connected to the positive input terminal and the negative input terminal of the system, the connection state signal generated by the system connection detecting unit causes the operation of the external power supply device to be switched by the deep sleep mode For normal working mode.
綜上所述,本發明實施例提供一種外部電源供應器以及應用 於外部電源供應器之系統連接偵測單元,所述電源供應器利用系統連接端連接系統時的阻抗匹配得到來自系統的電壓偵測信號,並利用此電壓偵測信號透過電路回授機制判斷電源是否連接至系統/負載以控制電源操作於深度睡眠模式和正常工作模式之應用。 In summary, the embodiments of the present invention provide an external power supply and an application thereof. The system of the external power supply is connected to the detecting unit, and the power supply uses the impedance matching when the system is connected to the system to obtain the voltage detecting signal from the system, and uses the voltage detecting signal to judge the power through the circuit feedback mechanism. Whether to connect to the system/load to control the application of the power supply operating in deep sleep mode and normal operating mode.
為使能更進一步瞭解本發明之特徵及技術內容,請參閱以下有關本發明之詳細說明與附圖,但是此等說明與所附圖式僅係用來說明本發明,而非對本發明的權利範圍作任何的限制。 The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.
1、1a、1b‧‧‧外部電源供應器 1, 1a, 1b‧‧‧ external power supply
2‧‧‧系統 2‧‧‧System
T1、T2‧‧‧時間點 T1, T2‧‧‧ time points
V1‧‧‧正常輸出電壓 V1‧‧‧ normal output voltage
20‧‧‧系統模組 20‧‧‧System Module
SA、SB、SC‧‧‧狀態 SA, SB, SC‧‧‧ Status
11‧‧‧電力供應單元 11‧‧‧Power supply unit
Vout‧‧‧輸出電壓 Vout‧‧‧ output voltage
GND‧‧‧接地 GND‧‧‧ Grounding
L、N‧‧‧交流端點 L, N‧‧‧ exchange endpoint
FG‧‧‧大地端 FG‧‧‧ Earth Terminal
Ta‧‧‧正輸出端 Ta‧‧‧ positive output
Tb‧‧‧負輸出端 Tb‧‧‧negative output
Tc‧‧‧正輸入端 Tc‧‧‧ positive input
Td‧‧‧負輸入端 Td‧‧‧negative input
V+、V-‧‧‧電壓 V+, V-‧‧‧ voltage
DETa‧‧‧系統偵測端 DETa‧‧‧ system detection end
DETb‧‧‧系統連接端 DETb‧‧‧ system connection
Rs‧‧‧第一電阻性元件 Rs‧‧‧First resistive element
111‧‧‧輸入濾波/整流電路 111‧‧‧Input Filter/Rectifier Circuit
112、32、42‧‧‧直流/直流轉換器 112, 32, 42‧‧‧ DC/DC converters
113‧‧‧控制積體電路 113‧‧‧Control integrated circuit
114‧‧‧回授誤差放大器 114‧‧‧Return error amplifier
12、12a、12b‧‧‧系統連接偵測單元 12, 12a, 12b‧‧‧ system connection detection unit
121、121a、121b、33、43‧‧‧電源阻抗匹配電路 121, 121a, 121b, 33, 43‧‧‧ power impedance matching circuit
122、122a、122b‧‧‧邏輯電路 122, 122a, 122b‧‧‧ logic circuits
VDET‧‧‧電壓偵測信號 V DET ‧‧‧voltage detection signal
Vref‧‧‧參考信號 Vref‧‧‧ reference signal
CS‧‧‧連接狀態信號 CS‧‧‧Connection status signal
CS’‧‧‧驅動信號 CS’‧‧‧ drive signal
CMP‧‧‧比較器 CMP‧‧‧ comparator
DRV‧‧‧驅動電路 DRV‧‧‧ drive circuit
Rd‧‧‧第二電阻性元件 Rd‧‧‧second resistive element
31、41‧‧‧控制器 31, 41‧‧‧ controller
34a、34b、34c、44a、44b、44c‧‧‧邏輯方塊 34a, 34b, 34c, 44a, 44b, 44c‧‧‧ logical squares
圖1是傳統的電源供應器的輸出電壓的波形圖。 Fig. 1 is a waveform diagram of an output voltage of a conventional power supply.
圖2是本發明實施例提供的外部電源供應器的輸出電壓的波形圖。 2 is a waveform diagram of an output voltage of an external power supply provided by an embodiment of the present invention.
圖3是本發明實施例提供的外部電源供應器與所連接的系統的電路方塊圖。 3 is a circuit block diagram of an external power supply and a connected system according to an embodiment of the present invention.
圖4是本發明實施例提供的外部電源供應器與所連接的系統的電路方塊圖。 4 is a circuit block diagram of an external power supply and a connected system according to an embodiment of the present invention.
圖5是圖4的電路方塊所對應的功能方塊圖。 FIG. 5 is a functional block diagram corresponding to the circuit block of FIG. 4.
圖6是本發明另一實例提供的外部電源供應器與所連接的系統的電路方塊圖。 6 is a circuit block diagram of an external power supply and a connected system provided by another example of the present invention.
圖7是圖5的電路方塊所對應的功能方塊圖。 FIG. 7 is a functional block diagram corresponding to the circuit block of FIG. 5.
本實施例的外部電源供應器具有正常工作模式(normal operation mode)與深度睡眠模式(deep sleeping mode)。外部電源供應器操作在深度睡眠模式所消耗的電力少於操作在正常工作模式所消耗的電力。請參照圖2,圖2是本發明實施例提供的外部電源 供應器的輸出電壓的波形圖。在此先說明本實施例的外部電源供應器所達到的目的,而外部電源供應器以及系統連接偵測單元的電路將於後續進一步說明。本實施例的外部電源供應器於無系統連接/無負載時進入深度睡眠模式,以達極低之輸入功耗以符合國際能源法規,如圖2所示外部電源供應器的運作是在狀態SA(睡眠)與狀態SB(切換)之間切換。於判斷連接系統時(在時間點T2),外部電源供應器即由深度睡眠模式恢復為正常工作模式(即改變為狀態SC持續切換功率開關),使輸出穩定於直流電壓(正常輸出電壓V1),藉此解決如圖1所示的因輸出電壓過低所造成的系統工作異常之問題。換句話說,在圖2中的系統負載開始後(時間點T1之後),由於外部電源供應器已工作在正常工作模式,使得輸出電壓並不會因負載而大幅降低。 The external power supply of this embodiment has a normal operation mode and a deep sleeping mode. The external power supply operates to consume less power in the deep sleep mode than is consumed in the normal operating mode. Please refer to FIG. 2. FIG. 2 is an external power supply according to an embodiment of the present invention. Waveform of the output voltage of the supplier. The purpose achieved by the external power supply of the present embodiment will be described first, and the circuits of the external power supply and the system connection detecting unit will be further described later. The external power supply of this embodiment enters deep sleep mode when there is no system connection/no load, so as to achieve extremely low input power consumption in accordance with international energy regulations, as shown in FIG. 2, the operation of the external power supply is in the state SA. Switch between (sleep) and status SB (handover). When judging the connection system (at time point T2), the external power supply is restored from the deep sleep mode to the normal operation mode (ie, changing to the state SC to continuously switch the power switch), so that the output is stabilized at the DC voltage (normal output voltage V1) Therefore, the problem of abnormal operation of the system caused by the output voltage being too low as shown in FIG. 1 is solved. In other words, after the system load in Fig. 2 starts (after time point T1), since the external power supply has been operating in the normal operation mode, the output voltage is not greatly reduced by the load.
如先前技術所說明的,利用現有技術,傳統的深度睡眠模式不適用於無配備電池之系統(當系統是電腦系統,則例如是桌上型電腦系統),參照圖1。因此,外部電源供應器僅能以突波模式(burst-mode)達到空載輸入能耗0.17~0.18W。相對的,當使用本發明實施例的技術,則可有效將空載輸入能耗減少約65%,以降低至0.06~0.07W並能進一步符合CoC tier II(Eff.>89%,Pin<0.15W at no load)規範。 As explained in the prior art, with the prior art, the conventional deep sleep mode is not suitable for a system without a battery (when the system is a computer system, for example, a desktop computer system), refer to FIG. Therefore, the external power supply can only achieve a no-load input energy consumption of 0.17~0.18W in burst mode. In contrast, when the technique of the embodiment of the present invention is used, the energy consumption of the no-load input can be effectively reduced by about 65% to be reduced to 0.06 to 0.07 W and can further conform to CoC tier II (Eff.>89%, Pin<0.15). W at no load) specification.
請參照圖3,圖3是本發明實施例提供的外部電源供應器與所連接的系統的電路方塊圖。外部電源供應器1用以分別透過正輸出端Ta與負輸出端Tb可分離地連接至系統2之正輸入端Tc與負輸入端Td,藉此提供電力至所述系統2。 Please refer to FIG. 3. FIG. 3 is a circuit block diagram of an external power supply and a connected system according to an embodiment of the present invention. The external power supply 1 is detachably connected to the positive input terminal Tc and the negative input terminal Td of the system 2 through the positive output terminal Ta and the negative output terminal Tb, respectively, thereby supplying power to the system 2.
當正輸出端Ta與負輸出端Tb未連接至系統2之正輸入端Tc與負輸入端Td時,外部電源供應器1操作於深度睡眠模式。例如:以圖2所示的輸出電壓波形為例,在時間點T2之前,外部電源供應器1的正輸出端Ta與負輸出端Tb未連接至系統2之正輸入端Tc與負輸入端Td,使得外部電源供應器1操作在深度睡眠模 式,而外部電源供應器1的輸出電壓Vout的狀態是在狀態SA與狀態SB之間切換。 When the positive output terminal Ta and the negative output terminal Tb are not connected to the positive input terminal Tc and the negative input terminal Td of the system 2, the external power supply 1 operates in the deep sleep mode. For example, taking the output voltage waveform shown in FIG. 2 as an example, before the time point T2, the positive output terminal Ta and the negative output terminal Tb of the external power supply 1 are not connected to the positive input terminal Tc and the negative input terminal Td of the system 2. So that the external power supply 1 operates in the deep sleep mode The state of the output voltage Vout of the external power supply 1 is switched between the state SA and the state SB.
外部電源供應器1包括電力供應單元11以及系統連接偵測單元12。電力供應單元11電性連接至正輸出端Ta與負輸出端Tb,電力供應單元11將外部電源轉換為直流電力。一般而言,所述外部電源可以是交流電源,但本發明並不因此限定。以外部電源例是交流電源(AC power)為例,電力供應單元11通常可以包括輸入濾波/整流電路111、直流/直流轉換器112、控制積體電路113與回授誤差放大器114。所屬技術領域具有通常知識者應容易了解電力供應單元11的實現方式,不再贅述。 The external power supply 1 includes a power supply unit 11 and a system connection detecting unit 12. The power supply unit 11 is electrically connected to the positive output terminal Ta and the negative output terminal Tb, and the power supply unit 11 converts the external power source into DC power. In general, the external power source may be an AC power source, but the invention is not so limited. Taking the external power source as an example of an AC power source, the power supply unit 11 may generally include an input filter/rectifier circuit 111, a DC/DC converter 112, a control integrated circuit 113, and a feedback error amplifier 114. Those skilled in the art should readily understand the implementation of the power supply unit 11, and will not be described again.
在圖3中,外部的交流電源透過火線L、中性線N與大地FG(Frame Ground)傳送至電力供應單元11的輸入濾波/整流電路111,但本發明也不限定電力供應單元11與外部電源的連接方式。輸入濾波/整流電路111將交流電源轉換為直流電,通常包括濾波以及整流的元件。直流/直流轉換器112將來自輸入濾波/整流電路111的電力傳送至正輸出端Ta與負輸出端Tb。控制積體電路113利用回授誤差放大器114的回授信號控制直流/直流轉換器112所輸出的輸出電壓Vout。 In FIG. 3, the external AC power source is transmitted to the input filter/rectifier circuit 111 of the power supply unit 11 through the live line L, the neutral line N, and the ground FG (Frame Ground), but the present invention is not limited to the power supply unit 11 and the outside. How to connect the power supply. The input filter/rectifier circuit 111 converts the AC power to DC power, typically including filtered and rectified components. The DC/DC converter 112 transmits power from the input filter/rectifier circuit 111 to the positive output terminal Ta and the negative output terminal Tb. The control integrated circuit 113 controls the output voltage Vout output from the DC/DC converter 112 by the feedback signal of the feedback error amplifier 114.
當正輸出端Ta與負輸出端Tb分別連接至系統2之正輸入端Tc與負輸入端Td時,電力供應單元11用以將直流電力(以輸出電壓Vout表示)傳送至系統2。以圖2的輸出電壓波形圖為例,時間點T2表示正輸出端Ta與負輸出端Tb分別連接至系統2之正輸入端Tc與負輸入端Td,而且在時間點T2時系統負載尚未存在(系統2尚未啟動)。在時間點T2之後的時間點T1則代表系統負載產生(系統2被啟動),此時電力供應單元11可以將直流電力傳送至系統2。 When the positive output terminal Ta and the negative output terminal Tb are respectively connected to the positive input terminal Tc and the negative input terminal Td of the system 2, the power supply unit 11 is configured to transmit DC power (indicated by the output voltage Vout) to the system 2. Taking the output voltage waveform diagram of FIG. 2 as an example, the time point T2 indicates that the positive output terminal Ta and the negative output terminal Tb are respectively connected to the positive input terminal Tc and the negative input terminal Td of the system 2, and the system load does not exist at the time point T2. (System 2 has not been started yet). The time point T1 after the time point T2 represents the system load generation (the system 2 is started), at which time the power supply unit 11 can transmit the direct current power to the system 2.
系統連接偵測單元12電性連接電力供應單元11,用於偵測外部電源供應器1與系統2的連接狀態。系統連接偵測單元11具有 系統偵測端DETa。系統2具有系統連接端DETb。本發明並不限定系統2的種類,在圖3中,系統2包括連接正輸入端Tc、負輸入端Td與系統連接端DETb的系統模組20,而針對系統2的應用類型(電腦、電視或機上盒等),系統2會有不同的功能電路,在圖3中被省略。 The system connection detecting unit 12 is electrically connected to the power supply unit 11 for detecting the connection state of the external power supply 1 and the system 2. The system connection detecting unit 11 has The system detects the terminal DETa. System 2 has a system connection DETb. The invention does not limit the type of the system 2. In FIG. 3, the system 2 includes a system module 20 that connects the positive input terminal Tc, the negative input terminal Td, and the system connection terminal DETb, and the application type for the system 2 (computer, television) Or the set-top box, etc.), system 2 will have different functional circuits, which are omitted in Figure 3.
外部電源供應器1與系統2的連接與否可以由使用者操作來決定。例如:外部電源供應器1的正輸出端Ta、負輸出端Tb與系統偵測端DETa可設置於一個連接器上(例如是具有三個電性接點的插座),而系統2的正輸入端Tc、負輸入端Td與系統連接端DETb也設置於一個連接器上(例如是具有三個電性接點的插頭)。使用者可以將系統2的連接器接上外部電源供應器1的連接器(例如將系統2的插頭接至外部電源供應器1的插座),以實現對於系統2的供電迴路。 The connection of the external power supply 1 to the system 2 can be determined by user operation. For example, the positive output terminal Ta, the negative output terminal Tb and the system detection terminal DETa of the external power supply 1 can be disposed on one connector (for example, a socket having three electrical contacts), and the positive input of the system 2 The terminal Tc, the negative input terminal Td and the system connection terminal DETb are also disposed on a connector (for example, a plug having three electrical contacts). The user can connect the connector of the system 2 to the connector of the external power supply 1 (for example, connect the plug of the system 2 to the socket of the external power supply 1) to implement a power supply loop for the system 2.
在另一實施例中,外部電源供應器1與系統2的連接與否可以用開關電路或切換器來決定。外部電源供應器1與系統2的連接可以利用切換器進行控制,當切換器被打開(turn on)時,所述切換器將正輸出端Ta、負輸出端Tb與系統偵測端DETa分別連接正輸入端Tc、負輸入端Td與系統連接端DETb。當切換器被關閉(turn off)時,所述切換器分別將正輸出端Ta與正輸入端Tc的連接斷開,將負輸出端Tb與負輸入端Td的連接斷開,且將系統偵測端DETa與系統連接端DETb的連接斷開。 In another embodiment, the connection of the external power supply 1 to the system 2 can be determined by a switching circuit or a switch. The connection between the external power supply 1 and the system 2 can be controlled by a switcher. When the switch is turned on, the switch connects the positive output terminal Ta and the negative output terminal Tb to the system detection terminal DETa. The positive input terminal Tc, the negative input terminal Td and the system connection terminal DETb. When the switch is turned off, the switch disconnects the connection between the positive output terminal Ta and the positive input terminal Tc, disconnects the connection between the negative output terminal Tb and the negative input terminal Td, and the system detects The connection between the measuring terminal DETa and the system connection terminal DETb is broken.
接著,繼續說明外部電源供應器1與系統2連接之後的電路狀態。當正輸出端Ta與負輸出端Tb分別連接至系統2之正輸入端Tc與負輸入端Td時,系統偵測端DETa用以連接至系統2之系統連接端DETb,其中系統連接端DETb透過至少一第一電阻性元件電性連接至系統2之正輸入端Ta與負輸入端Tb的其中之一。在圖3的實施例中,第一電阻性元件是Rs,且第一電阻性元件Rs連接至系統2之負輸入端Td,而系統連接端DETb與正輸入端Tc 不連接。另外,在後續的另一實施例中,系統連接端DETb透過第一電阻性元件Rs連接至系統2之正輸入端Tc。但本發明並不限定系統2之系統連接端DETb與正輸入端Tc或負輸入端Td的連接方式。系統2之系統連接端DETb可以利用不只一個電阻性元件所組成的電阻電路而與正輸入端Tc與負輸入端Td的其中之一連接。也就是說,系統2之系統連接端DETb透過電阻性元件與正輸入端Tc與負輸入端Td的其中之一連接,使得在當系統連接端DETb與系統偵測端DETa連接時,系統連接端DETb的電壓變化可被系統偵測端DETa所測得。換句話說,系統2之系統連接端DETb是用以在外部電源供應器1與系統2連接時回饋系統2所獲得的輸入電壓的狀態給外部電源供應器1,以致使外部電源供應器1離開深度睡眠模式。 Next, the state of the circuit after the external power supply 1 is connected to the system 2 will be described. When the positive output terminal Ta and the negative output terminal Tb are respectively connected to the positive input terminal Tc and the negative input terminal Td of the system 2, the system detecting terminal DETa is connected to the system connection terminal DETb of the system 2, wherein the system connection terminal DETb transmits At least one first resistive element is electrically connected to one of the positive input terminal Ta and the negative input terminal Tb of the system 2. In the embodiment of FIG. 3, the first resistive element is Rs, and the first resistive element Rs is connected to the negative input terminal Td of the system 2, and the system connection terminal DETb and the positive input terminal Tc Not connected. In addition, in a further embodiment, the system connection terminal DETb is connected to the positive input terminal Tc of the system 2 via the first resistive element Rs. However, the present invention does not limit the manner in which the system connection terminal DETb of the system 2 is connected to the positive input terminal Tc or the negative input terminal Td. The system connection terminal DETb of the system 2 can be connected to one of the positive input terminal Tc and the negative input terminal Td by a resistor circuit composed of more than one resistive component. That is to say, the system connection terminal DETb of the system 2 is connected through one of the positive input terminal Tc and the negative input terminal Td through the resistive component, so that when the system connection terminal DETb is connected with the system detection terminal DETa, the system connection end The voltage change of DETb can be measured by the system detection terminal DETa. In other words, the system connection terminal DETb of the system 2 is used to return the state of the input voltage obtained by the system 2 to the external power supply 1 when the external power supply 1 is connected to the system 2, so that the external power supply 1 is left. Deep sleep mode.
系統連接偵測單元12偵測系統偵測端DETa之電壓並據此產生連接狀態信號CS,當正輸出端Ta與負輸出端Tb分別連接至系統2之正輸入端Tc與負輸入端Td時(此時系統連接端DETb也與系統偵測端DETa連接),系統連接偵測單元12產生之連接狀態信號CS被傳送至電力供應單元11,以使電力供應單元11改變操作狀態。如此,外部電源供應器1的操作可由深度睡眠模式切換為正常工作模式。 The system connection detecting unit 12 detects the voltage of the system detecting terminal DETa and generates a connection state signal CS according to the same. When the positive output terminal Ta and the negative output terminal Tb are respectively connected to the positive input terminal Tc and the negative input terminal Td of the system 2, (At this time, the system connection terminal DETb is also connected to the system detection terminal DETa), and the connection state signal CS generated by the system connection detecting unit 12 is transmitted to the power supply unit 11 to cause the power supply unit 11 to change the operation state. As such, the operation of the external power supply 1 can be switched from the deep sleep mode to the normal operating mode.
系統連接偵測單元12包括電源阻抗匹配電路121以及邏輯電路122。電源阻抗匹配電路121電性連接系統偵測端DETa,依據系統偵測端DETa之電壓產生電壓偵測信號VDET。邏輯電路122電性連接至電源阻抗匹配電路121,邏輯電路122將電壓偵測信號VDET與參考信號Vref做比較而產生連接狀態信號CS,其中參考信號Vref的電壓介於正輸出端Ta與負輸出端Tb之間的電壓。依據實際需要,參考信號Vref是可設定的。在本實施例中,參考信號Vref是用以區別系統連接端DETb與系統偵測端DETa連接與否的電壓偵測信號VDET的差異。 The system connection detecting unit 12 includes a power source impedance matching circuit 121 and a logic circuit 122. The power impedance matching circuit 121 is electrically connected to the system detection terminal DETa, and generates a voltage detection signal V DET according to the voltage of the system detection terminal DETa. The logic circuit 122 is electrically connected to the power source impedance matching circuit 121. The logic circuit 122 compares the voltage detection signal V DET with the reference signal Vref to generate a connection state signal CS, wherein the voltage of the reference signal Vref is between the positive output terminal Ta and the negative The voltage between the output terminals Tb. The reference signal Vref is configurable according to actual needs. In this embodiment, the reference signal Vref is used to distinguish the difference between the voltage detection signal V DET of whether the system connection terminal DETb is connected to the system detection terminal DETa.
電源阻抗匹配電路121是用於在系統連接端DETb與系統偵測端DETa連接時的阻抗匹配。電源阻抗匹配電路121至少具有一個第二電阻性元件。邏輯電路是對來自電源阻抗匹配電路121的電壓偵測信號VDET作邏輯判斷,以判定系統2是否有與外部電源供應器1連接。電源阻抗匹配電路121與邏輯電路122的實施方式將於後續進一步說明。 The power impedance matching circuit 121 is used for impedance matching when the system connection terminal DETb is connected to the system detection terminal DETa. The power source impedance matching circuit 121 has at least one second resistive element. The logic circuit logically judges the voltage detection signal V DET from the power source impedance matching circuit 121 to determine whether the system 2 is connected to the external power supply 1 . Embodiments of the power supply impedance matching circuit 121 and the logic circuit 122 will be further described later.
請參照圖4,圖4是本發明實施例提供的外部電源供應器與所連接的系統的電路方塊圖。圖4的外部電源供應器1a的電力供應單元11與圖3的外部電源供應器1的電力供應單元11相同。圖4進一步揭示了系統連接偵測單元的其中一個實現方式。系統連接偵測單元12a包括電源阻抗匹配電路121a以及邏輯電路122a。 Please refer to FIG. 4. FIG. 4 is a circuit block diagram of an external power supply and a connected system according to an embodiment of the present invention. The power supply unit 11 of the external power supply 1a of FIG. 4 is the same as the power supply unit 11 of the external power supply 1 of FIG. Figure 4 further discloses one implementation of the system connection detection unit. The system connection detecting unit 12a includes a power source impedance matching circuit 121a and a logic circuit 122a.
如圖4所示,電源阻抗匹配電路121a包括第二電阻性元件Rd。第二電阻性元件Rd連接於系統偵測端DETa與正輸出端Ta之間,也就是系統偵測端DETa透過第二電阻性元件Rd電性連接正輸出端Ta。而系統連接端DETb透過第一電阻性元件Rs電性連接至系統2之負輸入端Td。 As shown in FIG. 4, the power source impedance matching circuit 121a includes a second resistive element Rd. The second resistive element Rd is connected between the system detecting end DETa and the positive output end Ta, that is, the system detecting end DETa is electrically connected to the positive output end Ta through the second resistive element Rd. The system connection terminal DETb is electrically connected to the negative input terminal Td of the system 2 through the first resistive element Rs.
然而,本發明並不限定電源阻抗匹配電路121a需要連接至正輸出端Ta或負輸出端Tb。在本實施例中,在系統連接端DETb與系統偵測端DETa未連接時(也就是外部電源供應器1a與系統尚未連接時),電源阻抗匹配電路121a利用第二電阻性元件Rd維持一個電壓狀態(V+)。使得當外部電源供應器1未連接至系統2時,電壓偵測信號VDET會隨著輸出電壓Vout(在圖4中即為電壓V+)作一周期性的變化,如圖2的時間點T2以前之電壓情況。在系統連接端DETb與系統偵測端DETa連接時,電壓偵測信號VDET則被改變且可被邏輯電路122a所區別出來。 However, the present invention does not limit the need for the power source impedance matching circuit 121a to be connected to the positive output terminal Ta or the negative output terminal Tb. In this embodiment, when the system connection terminal DETb is not connected to the system detection terminal DETa (that is, when the external power supply 1a is not connected to the system), the power supply impedance matching circuit 121a maintains a voltage by using the second resistive element Rd. Status (V+). When the external power supply 1 is not connected to the system 2, the voltage detection signal V DET changes periodically with the output voltage Vout (the voltage V+ in FIG. 4), as shown in the time point T2 of FIG. The previous voltage situation. When the system connection terminal DETb is connected to the system detection terminal DETa, the voltage detection signal V DET is changed and can be distinguished by the logic circuit 122a.
在實際應用時,電源阻抗匹配電路121a也可不連接至正輸出端Ta或負輸出端Tb(例如連接至一個不同於輸出電壓Vout的固定電壓),只要電源阻抗匹配電路121a產生的電壓偵測信號VDET可 以讓邏輯電路122a得知系統連接端DETb與系統偵測端DETa尚未連接的狀態,且使邏輯電路122a可以區別系統連接端DETb與系統偵測端DETa連接與否的電壓差異即可。在另一實施例中,電源阻抗匹配電路121a也可以包括多個第二電阻性元件所組成的電阻電路或分壓電路。 In practical applications, the power source impedance matching circuit 121a may not be connected to the positive output terminal Ta or the negative output terminal Tb (for example, connected to a fixed voltage different from the output voltage Vout) as long as the power source impedance matching circuit 121a generates a voltage detection signal. The V DET can make the logic circuit 122a know that the system connection terminal DETb is not connected to the system detection terminal DETa, and the logic circuit 122a can distinguish the voltage difference between the system connection terminal DETb and the system detection terminal DETa. In another embodiment, the power source impedance matching circuit 121a may also include a resistor circuit or a voltage dividing circuit composed of a plurality of second resistive elements.
邏輯電路122a包括比較器CMP與驅動電路DRV。比較器CMP分別接收電壓偵測信號VDET與參考信號Vref,以產生連接狀態信號CS。在圖4中,比較器CMP的正輸入端(+)接收電壓偵測信號VDET與而比較器CMP的負輸入端(-)接收參考信號Vref,但本發明並不因此限定。比較器CMP輸入信號的方式可依據邏輯電路122a的設計而改變。 The logic circuit 122a includes a comparator CMP and a drive circuit DRV. The comparator CMP receives the voltage detection signal V DET and the reference signal Vref, respectively, to generate a connection state signal CS. In FIG. 4, the positive input terminal (+) of the comparator CMP receives the voltage detection signal V DET and the negative input terminal (-) of the comparator CMP receives the reference signal Vref, but the present invention is not limited thereto. The manner in which the comparator CMP inputs the signal can vary depending on the design of the logic circuit 122a.
驅動電路DRV耦接比較器CMP,將比較器CMP所產生之連接狀態信號CS轉換為驅動信號CS’以提供至電力供應單元11之控制晶片(例如是圖4的控制積體電路113),藉此決定是否使外部電源供應器1a由深度睡眠模式切換為正常工作模式。驅動信號CS’與連接狀態信號CS可以相同,在實際應用時驅動信號CS’可代替連接狀態信號CS作為驅動控制的信號源。在實際應用時,驅動電路DRV的驅動信號CS’可依據電路設計需要而調整。在本實施例中,驅動電路DRV可以是獨立於控制積體電路113之外的控制晶片或電路,但本發明並不因此限定。 The driving circuit DRV is coupled to the comparator CMP, and converts the connection state signal CS generated by the comparator CMP into a driving signal CS' to be supplied to the control chip of the power supply unit 11 (for example, the control integrated circuit 113 of FIG. 4). This decision determines whether the external power supply 1a is switched from the deep sleep mode to the normal operation mode. The drive signal CS' and the connection state signal CS may be the same, and in actual application, the drive signal CS' may be used as a signal source for drive control instead of the connection state signal CS. In practical applications, the drive signal CS' of the drive circuit DRV can be adjusted according to the circuit design needs. In the present embodiment, the drive circuit DRV may be a control chip or circuit independent of the control integrated circuit 113, but the present invention is not limited thereto.
在另一實施例中,驅動電路DRV可以被併入電力供應單元11的控制積體電路113中以成為單一個控制晶片。也就是說,邏輯電路122a直接將電壓偵測信號VDET與參考信號Vref做比較而產生連接狀態信號CS,並將連接狀態信號CS提供至電力供應單元11之一控制晶片(即圖4中的控制積體電路113),藉此決定是否使外部電源供應器1a的操作由深度睡眠模式切換為正常工作模式。 In another embodiment, the drive circuit DRV may be incorporated into the control integrated circuit 113 of the power supply unit 11 to become a single control wafer. That is, the logic circuit 122a directly compares the voltage detection signal V DET with the reference signal Vref to generate a connection state signal CS, and supplies the connection state signal CS to one of the power supply units 11 to control the wafer (ie, in FIG. 4 The integrated circuit 113) is controlled, thereby determining whether or not the operation of the external power supply 1a is switched from the deep sleep mode to the normal operation mode.
接著,請同時參照圖4和圖5,圖5是圖4的電路方塊所對應的功能方塊圖。藉由圖5的功能方塊可得知,外部電源供應器1a 的電源阻抗匹配電路121a與邏輯電路122a可以有多種實施方式,並不僅限於圖4的電路。如圖5所示,控制器31控制直流/直流轉換器32,控制器31就是對應於圖4的控制積體電路113,直流/直流轉換器32對應於圖4的直流/直流轉換器112。電源阻抗匹配電路33可透過至少一個第二電阻性元件接收正輸出端Ta或負輸出端Tb的電壓(V+或V-),在圖4中電源阻抗匹配電路121a透過第二電阻性元件Rd接收正輸出端Ta的電壓(V+)。依據對應於系統連接端DETb與系統偵測端DETa的連接狀態的電壓偵測信號VDET,邏輯方塊34a、34b、34c則判斷要將外部電源供應器1a切換為深度睡眠模式或正常工作模式。邏輯方塊34a將電壓偵測信號VDET與參考信號Vref作比較,當電壓偵測信號VDET大於或等於參考信號Vref時,邏輯方塊34b判斷電源未連接至系統,而通知控制器31操作於深度睡眠模式。反之,當電壓偵測信號VDET小於參考信號Vref時,邏輯方塊34c判斷電源連接至系統,而通知控制器31操作於正常工作模式。 Next, please refer to FIG. 4 and FIG. 5 at the same time. FIG. 5 is a functional block diagram corresponding to the circuit block of FIG. 4. As can be seen from the functional blocks of FIG. 5, the power supply impedance matching circuit 121a and the logic circuit 122a of the external power supply 1a can have various embodiments and are not limited to the circuit of FIG. As shown in FIG. 5, the controller 31 controls the DC/DC converter 32, which corresponds to the control integrated circuit 113 of FIG. 4, and the DC/DC converter 32 corresponds to the DC/DC converter 112 of FIG. The power source impedance matching circuit 33 can receive the voltage (V+ or V-) of the positive output terminal Ta or the negative output terminal Tb through the at least one second resistive element, and the power source impedance matching circuit 121a receives the second resistive element Rd in FIG. The voltage (V+) of the positive output terminal Ta. According to the voltage detection signal V DET corresponding to the connection state of the system connection terminal DETb and the system detection terminal DETa, the logic blocks 34a, 34b, 34c determine that the external power supply 1a is to be switched to the deep sleep mode or the normal operation mode. The logic block 34a compares the voltage detection signal V DET with the reference signal Vref. When the voltage detection signal V DET is greater than or equal to the reference signal Vref, the logic block 34b determines that the power source is not connected to the system, and notifies the controller 31 that the operation is in depth. Sleep mode. Conversely, when the voltage detection signal V DET is less than the reference signal Vref, the logic block 34c determines that the power supply is connected to the system and notifies the controller 31 that it is operating in the normal operating mode.
請參照圖6,圖6是本發明另一實施例提供的外部電源供應器與所連接的系統的電路方塊圖。圖6的外部電源供應器1b的電力供應單元11與圖3的外部電源供應器1的電力供應單元11相同。圖6進一步揭示了系統連接偵測單元的另一個實現方式。系統連接偵測單元12b包括電源阻抗匹配電路121b以及邏輯電路122b。 Please refer to FIG. 6. FIG. 6 is a circuit block diagram of an external power supply and a connected system according to another embodiment of the present invention. The power supply unit 11 of the external power supply 1b of FIG. 6 is the same as the power supply unit 11 of the external power supply 1 of FIG. Figure 6 further discloses another implementation of the system connection detection unit. The system connection detecting unit 12b includes a power source impedance matching circuit 121b and a logic circuit 122b.
如圖6所示,電源阻抗匹配電路121b包括第二電阻性元件Rd。圖6的電路與圖4的電路大致相同,其差異僅在於將電源阻抗匹配電路121a替換為電源阻抗匹配電路121b,且將圖4的系統連接端DETb所連接的第一電阻性元件Rs改連接至正輸入端Tc,而系統連接端DETb與負輸入端Td不連接。換句話說,系統偵測端DETa透過第二電阻性元件Rd電性連接負輸出端Tb,且系統連 接端DETb透過第一電阻性元件Rs電性連接至系統2之正輸入端Tc。 As shown in FIG. 6, the power source impedance matching circuit 121b includes a second resistive element Rd. The circuit of FIG. 6 is substantially the same as the circuit of FIG. 4 except that the power source impedance matching circuit 121a is replaced with the power source impedance matching circuit 121b, and the first resistive element Rs connected to the system connection terminal DETb of FIG. 4 is connected. Up to the positive input terminal Tc, the system connection terminal DETb is not connected to the negative input terminal Td. In other words, the system detection terminal DETa is electrically connected to the negative output terminal Tb through the second resistive element Rd, and the system is connected. The terminal DETb is electrically connected to the positive input terminal Tc of the system 2 through the first resistive element Rs.
電源阻抗匹配電路121b利用第二電阻性元件Rd維持一個電壓狀態(V-,也就是接地GND),使電壓偵測信號VDET為固定不變(以圖4的情況稱為下拉pull-low)。在另一實施例中,電源阻抗匹配電路121b也可以包括多個第二電阻性元件所組成的電阻電路或分壓電路。 The power supply impedance matching circuit 121b maintains a voltage state (V-, that is, ground GND) by using the second resistive element Rd, so that the voltage detection signal V DET is fixed (referred to as pull-down-low in the case of FIG. 4). . In another embodiment, the power source impedance matching circuit 121b may also include a resistor circuit or a voltage dividing circuit composed of a plurality of second resistive elements.
邏輯電路122b包括比較器CMP與驅動電路DRV。比較器CMP分別接收電壓偵測信號VDET與參考信號Vref,以產生連接狀態信號CS。在圖6中,比較器CMP的正輸入端(+)接收電壓偵測信號VDET與而比較器CMP的負輸入端(-)接收參考信號Vref,但本發明並不因此限定。比較器CMP輸入信號的方式可依據邏輯電路122b的設計而改變。 The logic circuit 122b includes a comparator CMP and a drive circuit DRV. The comparator CMP receives the voltage detection signal V DET and the reference signal Vref, respectively, to generate a connection state signal CS. In FIG. 6, the positive input terminal (+) of the comparator CMP receives the voltage detection signal V DET and the negative input terminal (-) of the comparator CMP receives the reference signal Vref, but the present invention is not limited thereto. The manner in which the comparator CMP inputs the signal can vary depending on the design of the logic circuit 122b.
驅動電路DRV耦接比較器CMP,將比較器CMP所產生之連接狀態信號CS轉換為驅動信號CS’以提供至電力供應單元11之控制晶片(例如是圖6的控制積體電路113),藉此決定是否使外部電源供應器1a由深度睡眠模式切換為正常工作模式。 The driving circuit DRV is coupled to the comparator CMP, and converts the connection state signal CS generated by the comparator CMP into a driving signal CS' to be supplied to the control chip of the power supply unit 11 (for example, the control integrated circuit 113 of FIG. 6). This decision determines whether the external power supply 1a is switched from the deep sleep mode to the normal operation mode.
在本實施例中,驅動電路DRV可以是獨立於控制積體電路113之外的控制晶片或電路,但本發明並不因此限定。在另一實施例中,驅動電路DRV可以被併入電力供應單元11的控制積體電路113中以成為單一個控制晶片。也就是說,邏輯電路122b直接將電壓偵測信號VDET與參考信號Vref做比較而產生連接狀態信號CS,並將連接狀態信號CS提供至電力供應單元11之一控制晶片(即圖6中的控制積體電路113),藉此決定是否使外部電源供應器1b的操作由深度睡眠模式切換為正常工作模式。 In the present embodiment, the drive circuit DRV may be a control chip or circuit independent of the control integrated circuit 113, but the present invention is not limited thereto. In another embodiment, the drive circuit DRV may be incorporated into the control integrated circuit 113 of the power supply unit 11 to become a single control wafer. That is, the logic circuit 122b directly compares the voltage detection signal V DET with the reference signal Vref to generate a connection state signal CS, and supplies the connection state signal CS to one of the power supply units 11 to control the wafer (ie, in FIG. 6 The integrated circuit 113) is controlled, thereby determining whether to switch the operation of the external power supply 1b from the deep sleep mode to the normal operation mode.
接著,請同時參照圖6和圖7,圖7是圖6的電路方塊所對應的功能方塊圖。藉由圖6的功能方塊可得知,外部電源供應器1b的電源阻抗匹配電路121b與邏輯電路122b可以有多種實施方 式,並不僅限於圖6的電路。如圖7所示,控制器41控制直流/直流轉換器42,控制器41就是對應於圖6的控制積體電路113,直流/直流轉換器42對應於圖6的直流/直流轉換器112。電源阻抗匹配電路43可透過至少一個第二電阻性元件接收正輸出端Ta或負輸出端Tb的電壓(V+或V-),在圖6中的電源阻抗匹配電路121b透過第二電阻性元件Rd接收負輸出端Tb的電壓(V-)。依據對應於系統連接端DETb與系統偵測端DETa的連接狀態的電壓偵測信號VDET,邏輯方塊44a、44b、44c則判斷要將外部電源供應器1b切換為深度睡眠模式或正常工作模式。邏輯方塊44a將電壓偵測信號VDET與參考信號Vref作比較,當電壓偵測信號VDET大於或等於參考信號Vref時,邏輯方塊44b判斷電源連接至系統,而通知控制器41操作於正常工作模式。反之,當電壓偵測信號VDET小於參考信號Vref時,邏輯方塊44c判斷電源連接至系統,而通知控制器41操作於深度睡眠模式。 Next, please refer to FIG. 6 and FIG. 7 at the same time. FIG. 7 is a functional block diagram corresponding to the circuit block of FIG. 6. As can be seen from the functional blocks of FIG. 6, the power supply impedance matching circuit 121b and the logic circuit 122b of the external power supply 1b can have various embodiments and are not limited to the circuit of FIG. As shown in FIG. 7, the controller 41 controls the DC/DC converter 42, which corresponds to the control integrated circuit 113 of FIG. 6, and the DC/DC converter 42 corresponds to the DC/DC converter 112 of FIG. The power source impedance matching circuit 43 can receive the voltage (V+ or V-) of the positive output terminal Ta or the negative output terminal Tb through the at least one second resistive element, and the power source impedance matching circuit 121b in FIG. 6 transmits the second resistive element Rd. The voltage (V-) of the negative output terminal Tb is received. According to the voltage detection signal V DET corresponding to the connection state of the system connection terminal DETb and the system detection terminal DETa, the logic blocks 44a, 44b, 44c determine that the external power supply 1b is to be switched to the deep sleep mode or the normal operation mode. The logic block 44a compares the voltage detection signal V DET with the reference signal Vref. When the voltage detection signal V DET is greater than or equal to the reference signal Vref, the logic block 44b determines that the power source is connected to the system, and notifies the controller 41 that the operation is normal. mode. On the other hand, when the voltage detection signal V DET is smaller than the reference signal Vref, the logic block 44c determines that the power source is connected to the system, and notifies the controller 41 to operate in the deep sleep mode.
綜上所述,本發明實施例所提供的外部電源供應器以及應用於外部電源供應器之系統連接偵測單元,透過電壓偵測的方式讓系統連接偵測單元偵測系統的輸入信號(電壓偵測信號),並以邏輯電路判斷方式調整電源供應器之工作模式。於無系統連接/無負載時進入深度睡眠模式,以達極低之輸入功耗以符合國際能源法規。於連接系統時電源供應器即恢復正常工作模式,使輸出穩定於直流,以解決系統抽載時因電源供應器來不及恢復正常工作模式而造成電壓過低,導致系統工作異常之問題,且使外部電源供應器可應用於無電池之電腦系統(例如桌上型電腦)、顯示器或電視等。 In summary, the external power supply provided by the embodiment of the present invention and the system connection detecting unit applied to the external power supply device enable the system to connect to the detecting unit to detect the input signal of the system through the voltage detection method (voltage The signal is detected), and the working mode of the power supply is adjusted in a logic circuit judgment manner. Enter deep sleep mode when there is no system connection/no load to achieve extremely low input power consumption to comply with international energy regulations. When the system is connected, the power supply returns to the normal working mode, so that the output is stabilized in DC, so as to solve the problem that the system is working abnormally due to the voltage being too low due to the power supply being unable to return to the normal working mode when the system is being pumped, and the external operation is caused. The power supply can be applied to a batteryless computer system (such as a desktop computer), a display, or a television.
以上所述僅為本發明之實施例,其並非用以侷限本發明之專利範圍。 The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.
1‧‧‧外部電源供應器 1‧‧‧External power supply
2‧‧‧系統 2‧‧‧System
20‧‧‧系統模組 20‧‧‧System Module
11‧‧‧電力供應單元 11‧‧‧Power supply unit
12‧‧‧系統連接偵測單元 12‧‧‧System connection detection unit
Vout‧‧‧輸出電壓 Vout‧‧‧ output voltage
GND‧‧‧接地 GND‧‧‧ Grounding
L、N‧‧‧交流端點 L, N‧‧‧ exchange endpoint
FG‧‧‧大地端 FG‧‧‧ Earth Terminal
Ta‧‧‧正輸出端 Ta‧‧‧ positive output
Tb‧‧‧負輸出端 Tb‧‧‧negative output
Tc‧‧‧正輸入端 Tc‧‧‧ positive input
Td‧‧‧負輸入端 Td‧‧‧negative input
V+、V-‧‧‧電壓 V+, V-‧‧‧ voltage
DETa‧‧‧系統偵測端 DETa‧‧‧ system detection end
DETb‧‧‧系統連接端 DETb‧‧‧ system connection
Rs‧‧‧第一電阻性元件 Rs‧‧‧First resistive element
111‧‧‧輸入濾波/整流電路 111‧‧‧Input Filter/Rectifier Circuit
112‧‧‧直流/直流轉換器 112‧‧‧DC/DC converter
113‧‧‧控制積體電路 113‧‧‧Control integrated circuit
114‧‧‧回授誤差放大器 114‧‧‧Return error amplifier
121‧‧‧電源阻抗匹配電路 121‧‧‧Power impedance matching circuit
122‧‧‧邏輯電路 122‧‧‧Logical Circuit
VDET‧‧‧電壓偵測信號 V DET ‧‧‧voltage detection signal
Vref‧‧‧參考信號 Vref‧‧‧ reference signal
CS‧‧‧連接狀態信號 CS‧‧‧Connection status signal
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