TW201103118A - Chip package and manufacturing method thereof - Google Patents
Chip package and manufacturing method thereof Download PDFInfo
- Publication number
- TW201103118A TW201103118A TW098142969A TW98142969A TW201103118A TW 201103118 A TW201103118 A TW 201103118A TW 098142969 A TW098142969 A TW 098142969A TW 98142969 A TW98142969 A TW 98142969A TW 201103118 A TW201103118 A TW 201103118A
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- encapsulant
- wafer
- protective layer
- chip package
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims description 86
- 239000008393 encapsulating agent Substances 0.000 claims description 59
- 238000000034 method Methods 0.000 claims description 54
- 239000011241 protective layer Substances 0.000 claims description 37
- 238000000227 grinding Methods 0.000 claims description 22
- 238000007517 polishing process Methods 0.000 claims description 18
- 238000005520 cutting process Methods 0.000 claims description 15
- 239000010410 layer Substances 0.000 claims description 13
- 238000007789 sealing Methods 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 239000000084 colloidal system Substances 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 claims 10
- 241000283690 Bos taurus Species 0.000 claims 1
- 230000007123 defense Effects 0.000 claims 1
- 239000002689 soil Substances 0.000 claims 1
- 238000000465 moulding Methods 0.000 abstract description 4
- 208000032365 Electromagnetic interference Diseases 0.000 abstract description 3
- 150000001875 compounds Chemical class 0.000 abstract 3
- 238000005498 polishing Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000006061 abrasive grain Substances 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 241000283973 Oryctolagus cuniculus Species 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011120 plywood Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
201103118 Aan.fvzz26-NEW-FrN AL-T W-20091215 六、發明說明: 【發明所屬之技術領域】 本發明關於一種半導體元件,特別是有關於— 封裝體。 、梗日日片 【先前技術】 對於大部分的電子元件或系統而言,電磁干 (Electro-magnetic interference,EMI)是一個嚴重 擾 戰性的問題。由於電磁干擾通常會中斷 具有挑 子元件或是電子系蘇的所有電路的二 統需具有有效的電磁干擾防護以確保可有效Ϊ: 、電磁干擾防護對於小尺寸且高密度的封裝 運作的敏感性電子元件特別地重要。於f知技中疋^磁 干擾的防護方式是在電子元件上 電磁 _十上貼附或固疋—金屬片及/ -¥電塾片’ ’、、'、而’刚述防護方式會增加製作成本。 【發明内容】 本發明提供-種晶封錢的製作方法,其設計彈性 較向且較為簡易 /、 本發明提供—種晶片封錢,其對於電軒擾的防護 功效較佳。 本發明提出-種晶片封裝體的製作方法如下所述。首 提供-基板條’基板條具有多個基板單元,且多條鑛 201103118 KEW-FINAL-TW-20091215 =線定義ίϋ各基板單tl。接著,提供至少—晶片於各基板 單70上’其中晶片電性連接至基板單元。然後,於基板條 上形成-封裝膠體以包覆晶片。之後,沿著胸線對封襄 膠體進打-研磨製程,以使封裝膠體的多個頂部邊緣呈非 直角狀,以及進行-切單製程,以沿著鑛切線切穿基板條 而形成多個獨立㈣片封魏。之後,在聽膠體上形成 一防遵層,以共形地覆蓋封裝膠體。 晶 本發明提出一種晶片封裝體包括一基板、至少 片、-封裝膠體以及-防護層。晶纽置於基板上並電性 連接至基板。封裝賴配置於基板上,並至少 的頂部邊緣 板 部分基板,其中封裝膠體的多個頂部邊緣呈非直角^。 ,層配置於封|膠體上,其中防護層共形地覆蓋封裝膠 的丁—、—頂面與多個側壁,且防護層電性連^至基 本發明提出一種晶片封農體包括-基板、至小—曰 片、一封裝膠體以及一防護層。晶片配置於基 曰曰 性連接至基板。封裝雜配置於基板上,並至费並電 與部分基板。防護絲置於縣賴上,其晶片 部邊緣呈非直角狀,且防護層電性連接至基板。°曰的頂 ,广發明可避免防護層在封裂膠J的垂 邊緣上谷易產生裂縫的問題,且防護層可 =角或 寸 封裝體的封㈣體並提供有效的晶片封後蓋晶片 護。在本發明中,由於有完整的防護層覆磁干擾防 裝體的可靠度以及防護的效果。 盍故可提升圭 201103118 i-v w^x'^.z.26-NEW-FINAL-TW-20091215 為讓本發明之上述特徵和優點能更明顯易懂,下 舉實施例,並配合所附圖式作詳細說明如下。 特 【實施方式】 本發明之晶片封裝體的製作方法可用來製作各種封 結構,且較適於製作堆疊式封裝體、多晶片封骏體或高^ 元件封裝體(包括射頻元件封裝體) 圖1A〜圖1G繪示本發明—實施例之晶片封裝體的製 程剖面圖。圖1D’與圖1D,,繪示圖1D的結構的立體圖, 圖1D的結構具有放大圖a或放大圖b中的研磨槽 (grinding trench ) ° 請參照圖1A,提供一基板條100,基板條1〇〇具有多 個基板102 (之後將形成的多條切割線可定義出這些基板 102,切割線如圖1A中的虛線所示),其中各基板1〇2包 括多個配置於其上的接點1〇4以及配置於其中的至少一接 地通道(ground via) 108。在覆晶接合時,接點104可作 為凸塊墊。基板條100可為一壓合板(laminate substrate), 例如印刷電路板(printed circuit board,PCB)。本實施例 包括現行的各種接地通道108,接地通道1〇8係位於基板 102中。對於壓合板而言,接地通道可貫穿整個基板(例 如從頂面延伸至底面),或者是從頂面或底面延伸至基板之 一内層,又或者是延伸於基板的二内層之間。接地通道的 尺寸可依據產品的電性品質來作調整,且鍍通孔(plated through-hole,PTH)或是填滿焊料的槽孔可構成接地通道 5 201103118 Αί,ϋκ^^ζο-ΝΈ W-FINAL-T W-20091215 /插塞(plug)。此外,可用配置有一導電焊料塊的一接地 塾來取代接地通道,其中導電焊料塊是位於基板之上表面 上。 “請參照圖1B,至少一晶片120配置在各基板1〇2的頂 面102a上。雖然本實施例是在基板1〇2上配置晶片120, 然而,在其他實施例中’也可以是在基板1〇2上配置其他 的表面黏著元件。晶片120透過多個凸塊1〇6電性連接至 基板102的多個接點104,其中凸塊106是位於晶片12〇 與接點104之間。雖然在此描述的是覆晶接合技術,在其 他實施例中,亦可以是應用打線接合技術(例如透過導線 連接)。晶片120較佳地配置在基板1〇2的一中心區域中。 請參照圖1C,進行一封膠製程,以於基板條100上形 成一封裝膠體130’其中封裝膠體13〇包覆晶片12〇、接點 104、凸塊1〇6以及至少部分的基板1〇2。封膠製程例如為 一覆蓋成型製程(over-molding process)。封裝膠體13〇 的材質例如為環氧樹脂(epoxy resin)或矽膠(silic〇n resin)。 请參照圖ID,進行-研磨製程,以移除科的封襄膠 體130而形成多條研磨紋路(研磨槽)135。研磨紋路 位於晶片120的周邊。較佳地’封裝膠體13〇中的研磨纹 路13S位於各基板102的邊界或邊緣的正上方。圖出,與 圖1D”!會示圖1D的結構的立體圖,_ m的結構具有放 大圖A或放大圖B中的研磨槽。如圖①與圖⑴,所示, 研磨紋路135位在基板敗的邊界線(虛線)上。在本實 t26-NEW-FINAL-TW-20〇91215 201103118 施例中,之後的鑛切製程(sawingprocess)將切過研磨紋 路135 ’其中研磨紋路135位於鑛切線(sawing line )上(如 虛線所示)。研磨製程例如為一斜圓盤研磨製程(oblique disc grinding process)。斜圓盤研磨製程是將具有斜刀片 之研磨圓盤切進封裝膠體中以形成内壁傾斜的溝槽。以位 於各基板102之邊界正上方的研磨紋路I%為例,研磨製 程可在封裝膠體13〇内形成一環形溝槽(ring_shaped trench) ’其中環形溝槽是沿著各基板102的邊界。 詳細而言’如圖1D、圖id,以及圖id,,所示,研磨紋 路135杈佳為具有反帽型(reverse_hat)截面的環狀溝槽(例 如溝槽的底部較窄且溝槽的頂部較寬)。換言之,研磨製 程可使封裝膠體13〇的頂部邊緣13〇e呈非正交 (non orthogonal)狀或非直角(n〇n right angular )狀。較 佳地,研磨製程可磨鈍封裝膠體13〇的頂部邊緣n〇e。封 裝膠體⑽的頂部邊緣13〇e不是具有一個純角^ (如放 大f 斤不)就疋具有二個鈍角02、…(如放大圖B所 :i 2例來說,對於研磨紋路135而言,鈍角Θ “失於 夕的斜面135a以及封襄膠體130的頂面130a 之間)的角度範圍約介於95。〜165。 於研磨紋路135的钭面8 ,角2(夾 .r ☆的斜面135a以及斜面135b之間)與鈍角 Θ 3 (夾於研磨紋路135的斜而Λ ® 130a ^ ^ .的斜面U5b與封裝膠體13〇的頂 二:Γ角度範圍約介於1〇〇。〜⑽。之間。較 仫地,研磨沬度d的範圍約為封穿脒@ # π /
倍至1/3倍。—般而古,二封裝膠體130的厚度D的W °研磨紋路135的深度大小可依防 7 201103118 ^ 一一一 NEW-FIN A L-TW-20091215 護需求(shielding requisite )、4+ 驶賊认兩。 參數而調整。 封顏的紐品質或是製程 請參考圖1E,可選擇忸砧、仓―, (half-cutting process) + ^ ^ #Ι » ^ 暴^基板_部分頂面1〇2a。—般來說,半切切g 直^板^⑼,以形成-預定深度並形成多個^槽體13= 較佳地,半切切㈣程的切割寬度(例如溝槽137的寬产 〇小於研磨紋路丨35的寬度A(例如研磨製程的研磨寬$ A)。在本實施例中’即使在半切切割製程之後,封裝^ 體130仍然保有純化的頂部邊緣me。接地通道的位置^ 排列可隨產品需求而調整。接地通道例如是位在鑛切線 上,且半切切割製程或是切單製程(singulati〇n process) 可切過接地通道。在圖1E中,半切切割製程是切進位於 鋸切線上的接地通道108。雖然在本實施例中,半切切割 製程是在研磨製程之後進行,但是,在其他實施例中,也 可以是在研磨製程之前進行半切切割製程。當半切切割製 耘疋在研磨製程之前進行時,隨後的研磨製程仍可鈍化半 切切割封裝膠體的頂部邊緣。 之後,請參照圖1F,在封裝膠體13〇上形成一防護層 140 ’以共形地(c〇nf〇rmally)覆蓋封裝膠體13〇的頂面 130a、側壁i3〇b以及頂部邊緣n〇e。形成防護層ho的 方法例如是以喷塗法(spray coating method )、電鑛法 (plating method )或是濺鑛法(sputtering method )沉積一 201103118 ^^x^^26-NEW-FIN AL-TW-20091215 金屬材料(未緣示),以共形地覆蓋封裝膠體13〇以及基板 條100之被溝槽137所暴露出的部分。金屬材料例如為紹、 銅、鉻、金、銀、鎳、焊料或是前述之組合。 原則上,封裝膠體的頂部邊緣既非銳角亦非直角,因 為銳角或直角的頂部邊緣的彼覆性質較差(例如披覆層易 形成裂缝)。由於本實施例之封裝膠體130的頂部邊緣13〇e 不是鈍的就是圓的,因此,有助於增加防護層14〇的覆芸 性(coverage)以及順應性(conformity)。由於防護層復 籲 少或是沒有裂縫,且防護層均勻地覆蓋彎角或邊緣,故可 增加防護層的防護性以及提升封裝體的可靠度。 請參照圖1G ’對基板條1〇〇的一底面1〇2b進行一切 單製程以切割鋸切線並切穿基板條100,以形成多個獨立 的晶片封裝體10。切單製程例如為一刀具切割製程或是一 雷射切割製程。
在下述的實施例中,可進一步地修改以及描述述圖1A 至圖1G所示的晶片封裝體的製作方法。又或者是,依序 # 進行圖1A至圖1C的製程步驟,然後進行一切單製程,以 沿著鋸切線切穿封裝膠體130以及基板條1〇〇,從而形成 多個獨立的晶片封裝體1〇。切單製程亦切穿基板條1〇〇中 的接地通道108。切單製程例如為一刀具切割製程或是— 雷射切割製程。在此,封裝膠體13〇的頂面13〇a與侧壁 130b的交界處標示為封裝膠體13〇的頂部邊緣13此。如圖 2A所示,在切單製程之後,封裝膠體13〇的頂部邊緣13加 大致上呈直角狀。 201103118 wNE W-FINAL-TW-20091215 之後,請參照圖2B,進行一研磨製程,以鈍化晶片封 裝體10的封裝膠體130的頂部邊緣13〇e。當切單^程切 過鋸切線時’在封裝膠體13〇的頂部邊緣13〇e上進行研磨 製程,其中頂部邊緣130e位於各基板》1〇2的邊界或周邊的 正上方。承上述,在研磨製程之前,頂部邊緣130e實質上 呈直角狀,而研磨製程可使封裝膠體13〇的頂部邊緣丨3如 2或圓化。研磨製程例如為—斜圓盤研磨製程或一圓研 $程。如圖2B所示,封裝膠體13〇的頂部邊緣⑽在 2研·程之後會被圓化。無論如何,在本發明的實施 =,封裝膠體130的頂部邊緣13〇e不是鈍 如圖1D中的放大圖A與放大^所示^ Γ冰歹如具有圓弧面,如圖2B中的上方放大圖所示)。 或曲率y依據製程錢而調整純的或圓的頂部邊緣的角度 ㈣i圖2B之後’如圖2c所示,在封裝膠體130上共形 側〜舰防護層140,以覆蓋封裝膠體130之頂面i3〇a、 上=二邊緣。形成_14°的方 ^ - X 、 L;"法電鍍法或是濺鍍法沉積一金屬材料(未 3 蓋封裝#體130以及各基板102的側壁。 純的或二⑽共形地覆蓋封裝霜130之 示),t ▲、遭綠l3〇e (如圖2C中上方局部放大圖所 如尤防濩層140亦具有純的或圓的頂部邊緣140e (例 如在^膠體13〇的頂部邊緣隱上方的圓滑面)。 θ 3繪不本發明〜實施例之晶片封裝體的剖面圖。請 10 26-NEW-FIN AL-TW-20091215 201103118 參照圖3 ’本實施例之晶片封裝體3〇包括一基板IQ〗、多 個接點104、多個凸塊106、至少一晶片120、一封裝勝體 130以及一防護層140。基板1〇2可為一壓合板,例如一雙 層或一四層壓合印刷電路板。晶片12〇可為一半導體晶 片,例如一射頻(radio-frequency,RF)晶片。防護層14〇 的材質例如是銅、鉻、金、銀、鎳、鋁或是前述之合金或 是焊料。晶片120透過接點(凸塊墊)1〇4以及凸兔 電性連接至絲⑽。封裝膠體13(3包)覆部分基m6 塊106以及晶片120。如圖3所示,防護層14〇配置於封 裝膠體130上,以覆蓋封裴膠體13〇的頂面13〇a、側壁13肋 以及鈍的頂部邊緣13〇e。封裝膠體13〇的頂面13〇&與側 壁130b的交界之處在此標示為封裝膠體13〇的頂部邊緣 130e’而封裝膠體130之鈍的頂部邊緣13如的詳細剖面圖 形相似於圖1D的放大圖B。由於半切切割製程沿著鋸二 線切穿封裝膠體130是在形成防護層14〇之前進行,因此, 封裝膠體130可完全被防護層14〇所覆蓋而不會暴露於晶 片封裝體3〇之外。防護層藉由直接接觸基板1〇2的= 少一接地通道108而電性連接至基板1〇2,且防護層 ”也通道⑽而接地。因此’利用基板的金』線或 ,本實施例的防護層可透過基板的接地面而 構中接地。防護層可在封裝結構巾建立—接 = 須使用一外加的接地面。 彳二而毋 MS,”明另—實施例之晶片封裝體的剖面圖。 〇月多*、?、圖4,曰曰片封裴體40主要相似於圖3的封裝結構, 11 201103118 λλερ^ζζο-ΝΕ W-F1N AL-TW-20091215 兩者的差異之處在於晶片封裝體40的封裝膠體l3〇的圓的 頂部邊緣130e。封裝膠體130之圓的頂部邊緣13〇e的詳 細剖面圖形相似於圖2B的放大圖。由於在形成防護層14〇 之前切單製程沿著鋸切線切穿封裝膠體13〇與基S板條 100’因此,基板102的側壁與封裝膠體13〇可全面地被防 護層140所覆蓋且不會暴露於晶片封裝體4〇外。防護層 140藉由直接接觸基板1〇2之至少一接地通道(例如為接 地插塞/填滿焊料的槽孔)108而電性連接至基板,且 防護層140可通過接地通道1〇8而接地。 圖5緣示本發明另一實施例之晶片封裝體的剖面圖。 請參照圖5,晶片封親5G主要相似於圖4的封裝壯構。 此外,封裝膠體m的純的頂部邊緣130e的詳細剖面附目 =於圖Π3的放大圖A。基板1〇2與封裝膠體13〇的侧壁 =防遵層140全面覆蓋,且不會暴露於晶片封褒體刈之 外。防護層M0藉由直接接觸基板1〇 而電性連接爾丨〇2,謂面⑽ 化研磨製程有純化或圓化的效果,故可純 或圓化封裝膠體的頂部邊緣以及頂部彎 實施例 護層可作為一電磁干擾防護,基板上的防 輕射源(滅ati〇ns_ce)的電體級受到周圍 勻覆蓋封裝膠體(特別3干擾在本貫施例中,均 ^ 、'疋在頂部邊緣與彎角的周圍)的防 層了有效加強封褒體對於電磁干擾的防護效果。此: 12 201103118 rt〇^26-NEW-FmAL-TW-20091215 ^裝體的可靠度增加。因為封裝結構的頂部邊緣以及頂部 被圓化或是鈍化,故可減少發生在f角的漏損量,進 而提升封裝結_電性魏。目此,此種設計可應用在高 頻,率的封以料,_是射頻元件。
表雖然本發明已以實施例揭露如上,然其並非用以限定 本lx明,任何所屬技術領域中具有通常知識者,在不脫離 本發明之精神和範㈣,當可作些許之更動與潤飾,故本 發明之保護範15當視後社Ϋ請專職圍所界定者為準。 【圖式簡單說明】 圖1A〜圖1G繪示本發明一實施例之晶片封裴 程剖面圖。 』衣 圖2A〜圖2C繪示本發明另一實施例之晶片封 製程中的某些步驟的剖面圖。 、_的 圖3繪示本發明一實施例之晶片封裝體的剖面圖。 圖4繪示本發明另一實施例之晶片封裝體的剖二: 圖5繪示本發明另一實施例之晶片封裝體的剖面圖。 【主要元件符號說明】 1〇、30、40、50 :晶片封裝體 100 .基板條 102 ·基板 l〇2a :頂面 iMb :底面 13 201103118
AbtJS^//o-NEW-FrNAL-TW-20091215 104 :接點 106 :凸塊 108 :接地通道 109 :接地面 120 :晶片 130 :封裝膠體 130a :頂面 130b :側璧 130e :頂部邊緣 135 :研磨紋路 135a、135b :斜面 137 :溝槽 140 :防護層 140e :頂部邊緣 a、A :寬度 d:研磨深度 D :厚度 0】、02、$3:純角
Claims (1)
- 201103118 AS>JiK2226-NEW-FINAL-T W-20091215 七、申請專利範圍: 1. 一種晶片封裝體的製作方法,包括: 提供一基板條,該基板條具有多個基板單元,且多條 鋸切線定義出各基板單充; 、 提供至亡-晶片於各基板單元上,其中該晶片電性連 接至該基板單元; 於該基板條上形成一封裝膠體以包覆該些晶片; 沿著該些鑛切線對該封裝膠體進行一研磨製程,以 該封裝膠體的多個頂部邊緣呈非直角狀; 進行-切單製程’以沿著該些銀切線切穿該基板條而 形成多個獨立的晶片封裝體;以及 3在該封裝膠體上形成一防護層,以共形地覆蓋該封裝 膠體。 t 2. 如申請專利範圍第i項所述之晶片封裝體的製 方法,其巾在進行該切單製程之前,先進行該研磨製程。 3. 如申請專利範圍第2項所述之晶片難體的 方法’其中在形成該防護層之前,先進行該切單製程。 、4·如申請專利範圍第2項所述之晶片封展體的 方法,其中該研磨製程包括一斜圓盤研磨製程。 方/更=請專利範圍第2項所述之晶片觀體的製作 在進行該研磨製程之後,對該封裝膠體 割製程;以及 牛切切 在該半切切鄕程之後並在該切單製程之前,形成該防 15 201103118 At>tK2226-NEW-FINAL-TW-20091215 護層。 方;專利範㈣5销述之晶片封錢的製作 =法,其巾斜购鄕_—_寬度小 = 的一研磨寬度。 唧熠製矛王 方法:更ϋ請專利範圍第2項所述之晶片縣體的製作 割製研磨製程之前’對該封裝膠體進行-半切切 層。在該研磨製程之後並在該切單製程之前,形成該防護 方法8利範圍第1項所述之晶片封震體的製作 =研I是在?行該切單製程之後才進ί 封裝體的該封歸的邊界線在各獨立的晶片 種晶片封裝體,包括: 11. 一基板; 至少—曰 μ —封’广置於該基板上並電性連接至該基板; 裝膠脰,配置於該基板上,並至少包覆該晶片與 16 201103118 ASbK^:26-:NEW-FINAL-TW-20091215 部分該基板,其中該封裝膠體的多個頂部邊緣呈 狀;以及 月 二防護層,配置於該封裝膠體上,其中該防護層共形 地覆蓋該封裝膠體的該些頂部邊緣、—頂面與多個側壁广 且該防護層電性連接至該基板。 上12.如申凊專利範圍第u項所述之晶片封裝體,其 中。亥防濩層透過該基板的至少一接地通道電性連接該美 板。 土 13.如申請專利範圍第u項所述之晶片封裝體,i 該封裝膠體之非直角的該些頂部邊緣是純的或圓的。 =如中請專利範圍第13項所述之晶片封褒體,其 赴^ +、膠體之鈍的該些頂部邊緣具有至少一鈍角,且該 、角失於該封裝膠體的該側壁與該頂面之間。 / 中兮t如申請專利範圍第14項所述之^封裝體,其 这鈍角的角度範圍約介於%。〜165。之間。 16_ —種晶片封裝體,包括: 一基板; 牵/\\ —一阳片,配置於該基板上,並電性連接至該基板; 部分該基=膠?及配置於該基板上,並至少包覆該晶片與 個頂層’配置於該封裝膠體上,其中該防護層的多 、17 、呈非直角狀,且該防護層電性連接至該基板。 中該防讀如申請專利範圍第16項所述之晶片封裝體,其 "4層透過該基板的至少一接地通道電性連接該基 17 201103118 ASEK2226-NE W-FINAL-TW-20091215 板。 18. 如申請專利範圍第16項所述之晶片封裝體,其 中該防護層之非直角的該些頂部邊緣是鈍的或圓的。 19. 如申請專利範圍第18項-所述之晶片封裝體,其 中該防護層之鈍的該些頂部邊緣具有至少一鈍角,該鈍角 的角度範圍約介於95°〜165°之間。 20. 如申請專利範圍第16項所述之晶片封裝體,其 中該防護層的材質包括紹、銅、絡、金、銀、鎳、焊料或 是前述之組合。 鲁18
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-
2009
- 2009-07-13 US US12/501,636 patent/US8212340B2/en active Active
- 2009-12-15 TW TW098142969A patent/TWI407543B/zh active
- 2009-12-23 CN CN2009102619443A patent/CN101958254A/zh active Pending
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Publication number | Publication date |
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US20110006408A1 (en) | 2011-01-13 |
CN101958254A (zh) | 2011-01-26 |
US8212340B2 (en) | 2012-07-03 |
TWI407543B (zh) | 2013-09-01 |
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