200842803 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種測試系統及測試方法，特別關於一 種平面顯示模組之測試系統及測試方法。 【先前技術】 平面顯示模組可依據驅動方式而區分為被動矩陣型 (Passive韻atrix，PM )及主動矩陣型（Active_Matrix， _ AM)，其中，由於主動矩陣型較被動矩陣型可提供更優良 的性能而成為主流。較常見的主動矩陣型顯示模組有主動 矩陣型液晶顯示模組（AM-LCD Module)或是主動矩陣型 有機發光二極體模組。 凊參照圖1所示，一般平面顯示模組1包含一顯示面 板11及一特殊應用積體電路（ASIC) 12，且在顯示面板 11之一侧設置一垂直移位暫存器14( Vertical Shift Register, 修VSR) ’其係與顯示面板1]L、特殊應用積體電路12電性連 接，在顯示面板11之另一側設置一水平移位暫存器 (Horizontal Shift Register，HSR) 15，其係分別與顯示面 ▲ 板11及特殊應用積體電路12電性連接。垂直移位暫存器 ， 14與水平移位暫存器15係可同時整合於顯示面板η的同 一個基板13上。 顯示面板11係區分為Ν個顯示區111〜11Ν，特殊應 用積體電路12係發送一對反相之時脈訊號ι21、ι22、一 起始脈衝訊號123以及影像訊號124至水平移位暫存器 200842803 15 ;特殊應用積體電路π並發送影像訊號124經由複數 資料線（Source Line)傳送至水平移位暫存器15。其中， 時脈訊號121、122、起始脈衝訊號123及影像訊號124之 ¥序係請參照圖2A所示。 水平移位暫存器15係依摔起始脈衝訊號123開始作 動，其係搭配時脈訊號121、122產生複數個顯示區開啟 成號，藉以控制影像訊號124分別傳送至第一顯示區111〜 第Ν顯示區11Ν，其中第Ν顯示區開啟訊號係控制影像訊 號124傳送至第Ν顯示區11Ν以將各晝素的資料寫入，如 此一來顯示區111〜11Ν即可顯示影像。 然而，受到製程或線路長度等影響，對於水平移位暫 存器15來說，影像訊號124並非和時脈訊號121、122、 起始脈衝訊號123及顯示區開啟訊號同步。請參照圖2Α 所不，若各顯示區開啟訊號之相位領先於影像訊號 時’將導致顯示區ΐη〜11Ν的晝素寫入時間過短，以致於 _產生以影（Remnant Image);另一情況如圖2g所示，各 顯示區開啟訊號之相位落後於影像訊號124時，將導致下 一顯示區之影像訊號124過早寫入，以致於產生重疊影像 (Overlapping Image ) 〇 習知的解決方式是在平面顯示模組〗中内設一相位調 正功，猎由人工方式來進行相位調整以達到相位一致·° 然而，由於成本及生產時間的考量，不可能針對每一平面 顯示模組1來單獨作調整，而是針對同一批生產出來的平 面顯示模組1來一起作調整及設定，即同一乜 J Μ的平面顯示 7 200842803 模組i具有相同的相位調整值，但如此仍會有一些平面顯 示模組1無法適用，以致於需回收無法適用的平面顯示模 組1並逐一檢查以進行相位調整，如此一來，便大幅增加 成本並浪費時間，且降低平面顯示模組1之可靠度及效能。 因此，如何提供一種平面,顯示模組之測試系統及測試 方法，能夠自動針對各平面顯示模組進行相位調整以提高 影像顯示品質，進而節省成本、提升產品可靠度及效能， 實為當前重要課題之一。 【發明内容】 有鑑於上述課題，本發明之目的為提供一種能夠自動 測試平面顯示模組之訊號相位並自動做最佳化調整之測 試系統及測試方法。 緣是，為達上述目的，依本發明之一種平面顯示模組 之測試系統包含一測試影像產生電路、一影像感測單元、 一相位調整電路以及一時序控制電路。測試影像產生電路 係產生一測試影像，且平面顯示模組係由時脈訊號所驅動 以顯示測試影像；影像感測單元係感測平面顯示模組所顯 示之测試影像以產生一擷取影像；相位調整電路係與影像 感測單元電性連接以接收擷取影像，並記錄擷取影像與測 試影像之一影像差異，且藉由改變相位調整訊號反覆測試 來得到最小的影像差異，產出最佳的相位調整信號；時序 控制電路係接收相位調整訊號，並依據相位調整訊號調整 時脈訊號之相位'。 8 200842803 、二人上述目的，依本發明之一種平面顯示模組之測試 ，法^ 3 K影像產生程序、-^定驢程序、-相位 凋二紅=衫像感測程序、一差異記錄程序 '再次執行 ，又疋凋正私序、相位調整程序、影像感測程序及差異記錄 程序^得到複數個影像差異％及一最佳化程序。測試影像 產生程序係產生一測武影像至平面顯示模組·，設定調整程 序係產生一相位調整訊號；相位調整程序依據相位調整訊 號调整一％脈訊號之相位，其中平面顯示模組係由時脈訊 • 號所驅動以顯示測試影像；影像感測程序係感測平面顯示 模組所顯示之測試影像以產生一擷取影像；差異記錄程序 係記錄擷取影像與測試影像之一影像差異；最佳化程序係 從該等影像差異中判斷出差異最小者，並選取差異最小者 所對應之相位調整訊號作為一最佳值。 承上所述，因依本發明之一種平面顯示模組之測試系 統及測試方法中’係將影像感測單元來感測到的擷取影像 來和原始的測試影像進行比較，並依據比較的結果自動地 _進行訊號的相位調整。因而免去習知所需要之回收、人工 再檢查等工作，進而降低成本’並提升產品之可靠度及效 一 能0 【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之一 種平面顯不模組之測試糸統及其測试方法。 請參照圖3所示，本發明較佳實施例之一測試系統2 200842803 係包含一相位調整 、、 時序控制電路23、—、—賴影像產生電路22、-25以及-影像感測校=路/4、一源極驅動電路 別與測試f彡像產_ t整電路21係分 測試影像產生2 = ^影像感測單元26電性連接； 路24電性連接·〜、B守亭控制電路23及伽瑪校正電 電性連接。，键正電路24係與源極驅動電路25200842803 IX. Description of the Invention: [Technical Field] The present invention relates to a test system and a test method, and more particularly to a test system and test method for a flat display module. [Prior Art] The flat display module can be divided into a passive matrix type (Passive rhythm atrix, PM) and an active matrix type (Active_Matrix, _ AM) according to the driving method, wherein the active matrix type can provide better than the passive matrix type. The performance has become mainstream. The more common active matrix display modules include an active matrix liquid crystal display module (AM-LCD Module) or an active matrix organic light emitting diode module. As shown in FIG. 1 , the general flat display module 1 includes a display panel 11 and an application specific integrated circuit (ASIC) 12 , and a vertical shift register 14 is disposed on one side of the display panel 11 ( Vertical Shift ) Register, repair VSR) 'The system is electrically connected to the display panel 1] L, the special application integrated circuit 12, and a horizontal shift register (HSR) 15 is disposed on the other side of the display panel 11. They are electrically connected to the display surface ▲ board 11 and the special application integrated circuit 12, respectively. The vertical shift register 14 and the horizontal shift register 15 can be simultaneously integrated on the same substrate 13 of the display panel η. The display panel 11 is divided into two display areas 111 to 11 Ν, and the special application integrated circuit 12 transmits a pair of inverted clock signals ι21, ι 22, a start pulse signal 123, and an image signal 124 to the horizontal shift register. 200842803 15 ; The special application integrated circuit π and the transmitted image signal 124 are transmitted to the horizontal shift register 15 via a multiple data line (Source Line). The timing signals 121, 122, the start pulse signal 123, and the image signal 124 are shown in FIG. 2A. The horizontal shift register 15 is activated by the falling start pulse signal 123, and the clock signal 121, 122 is used to generate a plurality of display areas, and the control image signals 124 are respectively transmitted to the first display area 111~ The display area 11Ν, wherein the second display area is turned on, and the control image signal 124 is transmitted to the second display area 11 to write the data of each element, so that the display areas 111 to 11 can display the image. However, due to the influence of the process or the length of the line, for the horizontal shift register 15, the image signal 124 is not synchronized with the clock signals 121, 122, the start pulse signal 123, and the display area turn-on signal. Please refer to Figure 2Α. If the phase of the signal in each display area is ahead of the image signal, the result will be that the display time of the display area ΐη~11Ν is too short, so that _ produces a shadow (Remnant Image); As shown in FIG. 2g, when the phase of the display signal of each display area lags behind the image signal 124, the image signal 124 of the next display area is written prematurely, so that an Overlapping Image is generated. The method is to set a phase adjustment function in the plane display module, and the phase adjustment is performed by the manual method to achieve the phase consistency. However, due to the consideration of cost and production time, it is impossible to display the module for each plane. 1 to make adjustments separately, but to adjust and set together the flat display module 1 produced in the same batch, that is, the same 乜J Μ plane display 7 200842803 Module i has the same phase adjustment value, but still Some flat display modules 1 are not suitable, so that it is necessary to recycle the unsuitable flat display module 1 and check them one by one for phase adjustment, thus greatly increasing Cost and waste time, and reduce the reliability and performance of the flat display module 1. Therefore, how to provide a test system and test method for a flat display module can automatically adjust the phase of each flat display module to improve image display quality, thereby saving cost, improving product reliability and performance, and is currently an important issue. one. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a test system and test method capable of automatically testing the signal phase of a flat display module and automatically optimizing it. Therefore, in order to achieve the above object, a test system for a flat display module according to the present invention comprises a test image generating circuit, an image sensing unit, a phase adjusting circuit and a timing control circuit. The test image generation circuit generates a test image, and the flat display module is driven by the clock signal to display the test image; the image sensing unit senses the test image displayed by the flat display module to generate a captured image. The phase adjustment circuit is electrically connected to the image sensing unit to receive the captured image, and records the image difference between the captured image and the test image, and the minimum image difference is obtained by changing the phase adjustment signal to test the image difference. The best phase adjustment signal; the timing control circuit receives the phase adjustment signal and adjusts the phase of the clock signal according to the phase adjustment signal. 8 200842803, the above two purposes of the two, according to the invention of a flat display module test, method ^ 3 K image generation program, - ^ 驴 program, - phase withered red = shirt image sensing program, a difference recording program 'Re-execution, and then the private sequence, phase adjustment program, image sensing program and difference recording program ^ get a plurality of image difference % and an optimization program. The test image generation program generates a test image to the flat display module, and the set adjustment program generates a phase adjustment signal; the phase adjustment program adjusts the phase of the one-frequency signal according to the phase adjustment signal, wherein the planar display module is time-dependent. The pulse signal is driven to display the test image; the image sensing program senses the test image displayed by the display module to generate a captured image; the difference recording program records the image difference between the captured image and the test image; The optimization program determines the smallest difference from the image differences, and selects the phase adjustment signal corresponding to the smallest difference as an optimal value. According to the above, in the test system and the test method of the flat display module according to the present invention, the image captured by the image sensing unit is compared with the original test image, and compared according to the comparison. The result is automatically _ the phase adjustment of the signal. Therefore, the recycling, manual re-inspection, and the like required by the prior art are eliminated, thereby reducing the cost and improving the reliability and efficiency of the product. [Embodiment] Hereinafter, a preferred embodiment according to the present invention will be described with reference to the related drawings. A test system with a flat panel display module and its test method. Referring to FIG. 3, a test system 2 200842803 according to a preferred embodiment of the present invention includes a phase adjustment, timing control circuit 23, -, image generation circuits 22, -25, and - image sensing correction = road /4, a source drive circuit and test f彡 image production _ t whole circuit 21 system test image generation 2 = ^ image sensing unit 26 electrical connection; road 24 electrical connection · ~, B guarding control circuit 23 and gamma correction electrical connection. Key positive circuit 24 and source drive circuit 25
存：盘莫組3係包含-顯示面板3卜-垂直移位暫 存:32^Ϊ千移位暫存器％等元件，其中垂直移位暫 存器33係可同時整合於顯示面板31 此外太二 顯不面板31係具有複數個顯示區域。 此外，本貫施例之平㈣示模組3係可包含—主動 ^且主動矩陣面板係可為但不限於—液晶顯 有機發光二極體面板。 經伽瑪校正電路24處理之後的影像資料係傳送至源 籲極驅動電路25,源極驅動電路25依據影像資料產生資料 訊號D S，並將資料訊號D s傳送至平面顯示模組3的水平 移位暫存器33，時序控制電路23係輸出二時脈訊號 -CKH、XCKH及起始脈衝訊號STH至平面顯示模組％的 ‘水平移位暫存器33，水平移位暫存器33係依據時脈訊號 CKH、XCKH及起始脈衝職STH產生複數個顯示區開啟 訊號以讓各顯示區域依據資料訊號DS來顯示影像。時脈 訊號CKH、XCKH、起始脈衝訊號STH、資料訊號DS及 顯示區開啟訊號之時序作動係請參照圖4所示。 200842803 凊簽妝圖5所示，並俜為岡1 八你馮圖3之測忒糸統2之測試步 驟之流程圖。 百先’在測試影像產生程序剛巾，測試影像產生電 路22係產生-測試影像TI，且測試影像τι係先經由伽瑪 校正電路24進行色彩校正之後傳送至源極驅動電路25。 源極驅動電路25依據測試影像TI產生資料訊號DS至平 面顯讀組3，以供平面顯示模組3顯示測試影像^。 另和在測試影像產生程序p〇1開始前，藉由傳送一 啟動訊號LS至相位調整電路21來啟動測試系統2。 在设定調整程序P02中，相位調整電路2ι產生一相 位調整訊號PAS並傳送至-暫存器28’相位調整訊號㈣ 係-取樣保持的設定值，用來調整訊號的相位。暫存器Μ 係分別與相位調整電路21及時序控制電路23電性連接。 在相位调整程序p〇3中，時序控制電路23依據自暫 存器2δ所得之相位調整訊號PAS來調整時脈訊號ckh、 XCKH及起始脈衝訊號STH之相位，其中相位調整方向可 如圖4所示，並傳送至平面顯示模組3。 在影像感測程序P04中，影像感測單元26感測平面 顯示柄組3所顯示之測試影像以產生一榻取影像ci。於 此，影像感測單元26可具有一電荷耦合元件（Charge Coupled Device，CCD )或一互補金屬氧化導體元件 (Complementary Metal-Oxide Semiconductor，CMOS)等 等具有光電性質之元件。另外，影像感測單元26對測試 影像之感測方式係可一次定位並進行感測，亦可移動位置 11 200842803 並進行感測；並且影像感測單元26可對整個測試影像或 局部測試影像進行感測而產生擷取影像CI。 接著，在差異記錄程序P05中，由於時脈訊號CKH、 XCKH及起始脈衝訊號STH已藉由相位調整訊號pAS而 調整相位，以致顯示區開啟訊,號與資料訊號DS之相位並 非同步；當然，就算時脈訊號CKH、XCKH及起始脈衝訊 號STH未受相位調整訊號PAS調整相位，顯示區開啟訊Storage: the disk group 3 includes - display panel 3 - vertical shift temporary storage: 32 ^ thousand shift register % and other components, wherein the vertical shift register 33 can be integrated into the display panel 31 at the same time The Taisan Display Panel 31 has a plurality of display areas. In addition, the flat (4) display module 3 of the present embodiment may include an active ^ and the active matrix panel may be, but not limited to, a liquid crystal display organic light emitting diode panel. The image data processed by the gamma correction circuit 24 is transmitted to the source ring drive circuit 25. The source drive circuit 25 generates the data signal DS according to the image data, and transmits the data signal D s to the horizontal shift of the flat display module 3. The bit buffer 33, the timing control circuit 23 outputs the two-way signal -CKH, XCKH and the start pulse signal STH to the 'horizontal shift register 33 of the plane display module %, and the horizontal shift register 33 According to the clock signal CKH, XCKH and the starting pulse job STH, a plurality of display area opening signals are generated to allow each display area to display an image according to the data signal DS. Please refer to Figure 4 for the timing of the clock signal CKH, XCKH, start pulse signal STH, data signal DS and display area turn-on signal. 200842803 凊 凊 凊 图 图 图 图 图 图 图 图 图 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊 凊The test image generation circuit 22 generates a test image TI, and the test image τι is first subjected to color correction via the gamma correction circuit 24 and then transmitted to the source drive circuit 25. The source driving circuit 25 generates the data signal DS to the flat reading group 3 according to the test image TI for the flat display module 3 to display the test image ^. In addition, before the start of the test image generation program p〇1, the test system 2 is started by transmitting a start signal LS to the phase adjustment circuit 21. In the setting adjustment program P02, the phase adjustment circuit 2i generates a phase adjustment signal PAS and transmits it to the -stage register 28' phase adjustment signal (4) system-sample hold value for adjusting the phase of the signal. The register system is electrically connected to the phase adjustment circuit 21 and the timing control circuit 23, respectively. In the phase adjustment program p〇3, the timing control circuit 23 adjusts the phases of the clock signals ckh, XCKH and the start pulse signal STH according to the phase adjustment signal PAS obtained from the register 2δ, wherein the phase adjustment direction can be as shown in FIG. Shown and transmitted to the flat display module 3. In the image sensing program P04, the image sensing unit 26 senses the test image displayed by the flat display handle set 3 to generate a couch image ci. Therefore, the image sensing unit 26 may have a photoelectrically-coupled component such as a charge coupled device (CCD) or a complementary metal-oxide semiconductor (CMOS). In addition, the image sensing unit 26 can sense and sense the test image at a time, and can also move the position 11 200842803 and perform sensing; and the image sensing unit 26 can perform the entire test image or the partial test image. The captured image CI is generated by sensing. Then, in the difference recording program P05, since the clock signals CKH, XCKH and the start pulse signal STH have been phase-adjusted by the phase adjustment signal pAS, the display area is turned on, and the phase of the signal and the data signal DS are not synchronized; Even if the clock signal CKH, XCKH and the start pulse signal STH are not adjusted by the phase adjustment signal PAS, the display area is turned on.
號與資料訊號DS之相位亦會受到製程或線路長度等影響 而並非同步。因此，實際擷取到的顯示影像與應當顯示的 測試影像有所不同。相位調整電路21記錄擷取影像〇1與 測试影像TI H彡像差異，影像差異係可記錄測試影像 TI及擷取衫像CI之間的亮度差異、或色度差異等等，影 像差異可儲存於與相位調整電路21電性連接之一記憶單 元27以供後續處理之用。The phase of the signal and the DS signal will also be affected by the process or line length, etc., and will not be synchronized. Therefore, the actual captured image is different from the test image that should be displayed. The phase adjustment circuit 21 records the difference between the captured image 〇1 and the test image TI H image. The image difference can record the brightness difference or the chromaticity difference between the test image TI and the captured image CI, and the image difference can be It is stored in a memory unit 27 electrically connected to the phase adjustment circuit 21 for subsequent processing.
细如例中’測試影像TI係包含一周期性圖案，周 期性圖案可句冬—锸 期性地m- 條紋，黑與白之條紋係周 異。B ^^又置，如此一來即可簡單地檢測出影像的差 替H料訊號DS和時脈訊號⑽、XCKH、起始脈衝 α的内心岣)所不’影像感測單元26產生的擷取影像 元％之水平位詈：：。其中姻係代表影像感測單 色時，表亮度料值。#條紋為黑 度強度純於低準位，當條紋為白色時，亮度強 12 200842803 度係位於高準位。 若資料訊號DS和時脈訊號CKH、XCKH、起始脈衝 訊號STH及顯示區開啟訊號不同步，平面顯示模組3〇顯 示的影像係如圖7(a)所示，可能產生殘影或重疊等現象， 衫像感測单元26產生的操取影像ci的内容係如圖7(b)所 示，在黑與白條紋之間具有灰色條紋，在高準位及低準位 之間具有灰色條紋所對應之中間準位。如此一來，圖6(b) 及圖7(b)之間便有一些影像差異可供比較並記錄。 瞻 然後，再次執行設定調整程序P〇2、與相位調整程序 P03、影像感測程序P04、差異記錄程序p〇5數次，如此相 位調整電路21便可逐次調整相位調整訊號pAS，藉由擷 取影像CI的回授而得到不同的影像差異，且這些影像差 異可儲存於記憶單元27中。 在最佳化程序P06中，相位調整電路21係從這些影 像差異中判斷出差異最小者，並選取差異最小者所對應之 參相位调整訊號PAS作為一最佳值。時序控制電路23係可 依據此最佳值來調整時脈訊號CKH、XCKH及起始脈衝訊 號STH之最佳相位。 最佳值係可於初始化時讀入至暫存器28中，以供時 序控制電路23於初始化時讀取，藉以調整時脈訊號CKH、 XCKH及起始脈衝訊號STH之最佳相位。 經由具有最佳调整相位之時脈訊號及起 始脈衝A號STH所產生之各顯示區開啟訊號係與資料訊 號DS具有致的相位，以致水平移位暫存器、w能夠正確 13 200842803 的依據各顯示區開訊號來取樣對應之資料訊號DS，使平 面顯示模組3之各顯示區能夠依序並正確的經由資料訊號 DS充電，而顯示出資料訊號DS所應具有的影像。 綜上所述，在本實施例中，相位調整電路21係可逐 次調整相位調整訊號PAS ; 3¾序控制電路23係逐次依據 經調整之相位調整訊號PAS調整時脈訊號CKH、XCKH 及起始脈衝訊號STH之相位；平面顯示模組3係由經調整 之時脈訊號CKH、XCKH及起始脈衝訊號STH所驅動以 顯示測試影像TI ;影像感測單元26係逐次感測平面顯示 模組30所顯示之測試影像以產生不同内容之擷取影像 CI ;相位調整電路21係逐次記錄擷取影像CI與測試影像 TI之影像差異’並從這些影像差異中選擇差異最小者所對 應之相位調整訊號PAS作為一最佳值。 在此而注意者，本實施例之測試方法之流程步驟的順 序僅為舉例，並非限制本發明。例如，在測試方法一開始 時，測試影像產生電路程序p〇1之後，可先進行影像感測 耘序P04及差異記錄程序p〇5，然後再執行設定調整程序 P02及相位調整程序pG3以得到其他的影像差異。 另外’本貫施例之最佳化程序除了可藉由判斷最小的 影像差異以得到相教調整之最佳值之外，亦可藉由其他計 算方式，例如内插法或外插法以得到最佳值。 在本貫施例中’相位調整電路21、測試影像產生電路 22、日守序控制電路23、伽瑪校正電路24、源極驅動電路 25及影像感測單& 26係、以實現於-積體電路為例，並且 14 200842803 積體電路可作為平面顯示模組3之驅動積體電路（Driver 1C)。此外，可如圖8所示，將相位調整電路21實現於一 计异裝置2 Γ ’例如為一計算機程式（c〇mpUter program ); 亦可將測試影像產生電路22實現於一啟動裝置22,，且啟 動裝置22’除了傳送測試影像yi至平面顯示模組3之外， 更啟動測試系統2作動。 此外，本實施例之測試系統及測試方法除了可用來得 到相位調整訊號PAS之最佳值之外，亦可應用於產品的統 •計上’例如查看每一批出產之平面顯示模組之良率、或顯 示區開啟訊號與資料訊號之間的相位差分佈等等，以利缺 失改正並提高效能。 綜上所述，因依本發明之一種平面顯示模組之測試系 統及測試方法中，.係將影像感測單元感測到的擷取影像來 和原始的測試影像進行比較，並依據比較的結果自動地進 行訊號的相位調整。因而免去習知所需要之回收、人工再 鲁檢查等工作，進而降低成本，並提升產品之可靠度及效能。 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範疇，而對其進行之等效修改或變更，均 應包含於後附之申睛專利範圍中。 【圖式簡單說明】 圖1為一種習知之平面顯示模組之一示音圖； 圖2A及圖2B為一種習知之平面顯示模組所具有之各 顯示區開啟訊號與影像訊號具有不同相位之示意圖； 15 200842803 圖3為依據本發明較佳實施例之一種平面顯示模組之 測試系統之一示意圖； 圖4為依據本發明較佳實施例之一種平面顯示模組之 • 測試系統所具有之時脈訊號、各顯示區開啟訊號及資料訊 7虎之一不意圖， 參 圖5為依據本發明較佳實施例之一種平面顯示模組之 測試方法之一流程圖； 圖6為依據本發明較佳實施例之一種平面顯示模組之 ❿測試系統所顯示之測試影像於相位一致時所具有之亮度 分佈圖； 圖7為依據本發明較佳實施例之一種平面顯示模組之 測試系統所顯示之測試影像於相位不一致時所具有之亮 度分佈圖；以及 圖8為依據本發明較佳實施例之一種平面顯示模組之 測試系統之另一示意圖。 元件符號說明： 1、3 平面顯示模組 ' 11、31 顯示面板 - 111〜11N 顯示區 12 特殊應用積體電路 121、122 時脈訊號 123、STH 起始脈衝訊號 124 影像訊號 16 200842803As in the example, the test image TI contains a periodic pattern, and the periodic pattern can be sentenced to winter-temporal m-stripes, and the black and white stripes are different. B ^^ is set again, so that the image difference between the H signal signal DS and the clock signal (10), the XCKH, and the inner pulse of the start pulse α can be simply detected. Take the horizontal value of the image element %::. The marriage system represents the brightness value of the table when the image senses a single color. #条纹为黑度 intensity is pure to low level, when the stripe is white, the brightness is strong 12 200842803 Degree is at high level. If the data signal DS and the clock signals CKH, XCKH, the start pulse signal STH and the display area turn-on signal are not synchronized, the image displayed by the flat display module 3〇 is as shown in FIG. 7(a), and may cause image sticking or overlapping. And the like, the content of the operation image ci generated by the shirt image sensing unit 26 is as shown in FIG. 7(b), with gray stripes between the black and white stripes, and gray between the high level and the low level. The intermediate level corresponding to the stripe. As a result, there are some image differences between Figure 6(b) and Figure 7(b) that can be compared and recorded. Then, the setting adjustment program P〇2, the phase adjustment program P03, the image sensing program P04, and the difference recording program p〇5 are executed again several times, so that the phase adjustment circuit 21 can sequentially adjust the phase adjustment signal pAS by 撷Different image differences are obtained by taking back the feedback of the image CI, and these image differences can be stored in the memory unit 27. In the optimization program P06, the phase adjustment circuit 21 judges the smallest difference from these image differences, and selects the phase adjustment signal PAS corresponding to the smallest difference as an optimum value. The timing control circuit 23 can adjust the optimum phase of the clock signals CKH, XCKH and the start pulse signal STH according to the optimum value. The optimum value can be read into the register 28 during initialization for the timing control circuit 23 to read during initialization to adjust the optimum phase of the clock signals CKH, XCKH and the start pulse signal STH. The phase of the open signal and the data signal DS generated by each of the display areas generated by the clock signal having the best adjusted phase and the start pulse A number STH, so that the horizontal shift register and the w can be correct 13 200842803 Each display area is opened to sample the corresponding data signal DS, so that each display area of the flat display module 3 can be sequentially and correctly charged via the data signal DS, and the image which the data signal DS should have is displayed. In summary, in the embodiment, the phase adjustment circuit 21 can adjust the phase adjustment signal PAS one by one; the sequence control circuit 23 sequentially adjusts the clock signals CKH, XCKH and the start pulse according to the adjusted phase adjustment signal PAS. The phase of the signal STH; the flat display module 3 is driven by the adjusted clock signals CKH, XCKH and the start pulse signal STH to display the test image TI; the image sensing unit 26 sequentially senses the flat display module 30 The test image is displayed to generate a captured image CI of different content; the phase adjustment circuit 21 sequentially records the image difference between the captured image CI and the test image TI' and selects the phase adjustment signal PAS corresponding to the smallest difference among the image differences As an optimal value. It is to be noted that the order of the process steps of the test method of the present embodiment is merely an example and does not limit the present invention. For example, at the beginning of the test method, after testing the image generation circuit program p〇1, the image sensing sequence P04 and the difference recording program p〇5 may be performed first, and then the setting adjustment program P02 and the phase adjustment program pG3 may be executed to obtain Other image differences. In addition, the optimization procedure of the present embodiment can be obtained by other calculation methods such as interpolation or extrapolation, in addition to determining the minimum image difference to obtain the optimal value of the teaching adjustment. best value. In the present embodiment, the 'phase adjustment circuit 21, the test image generation circuit 22, the day-to-order control circuit 23, the gamma correction circuit 24, the source drive circuit 25, and the image sensing unit & 26 are implemented in - The integrated circuit is taken as an example, and the 14 200842803 integrated circuit can be used as the drive integrated circuit (Driver 1C) of the flat display module 3. In addition, as shown in FIG. 8, the phase adjustment circuit 21 can be implemented in a metering device 2 Γ ', for example, a computer program (c〇mpUter program); or the test image generation circuit 22 can be implemented in a startup device 22, And the starting device 22' activates the test system 2 in addition to transmitting the test image yi to the flat display module 3. In addition, the test system and the test method of the present embodiment can be applied to the product of the product in addition to the optimum value of the phase adjustment signal PAS. For example, the yield of the flat display module produced in each batch is obtained. Or, the display area opens the phase difference distribution between the signal and the data signal, etc., in order to facilitate the lack of correction and improve performance. In summary, in the test system and the test method of the flat display module according to the present invention, the captured image sensed by the image sensing unit is compared with the original test image, and compared according to the comparison. As a result, the phase adjustment of the signal is automatically performed. This eliminates the need for recycling, manual re-inspection, etc., which reduces the cost and improves the reliability and performance of the product. The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a conventional flat display module; FIG. 2A and FIG. 2B show a display phase of a conventional flat display module having different phases of the open signal and the video signal. 15 200842803 FIG. 3 is a schematic diagram of a test system of a flat display module according to a preferred embodiment of the present invention; FIG. 4 is a test system of a flat display module according to a preferred embodiment of the present invention; FIG. 5 is a flow chart of a test method for a flat display module according to a preferred embodiment of the present invention; FIG. 6 is a diagram of a clock signal, each display area, and a data source. A brightness distribution map of a test image displayed by a test system of a flat display module in a phase-matched manner; FIG. 7 is a test system of a flat display module according to a preferred embodiment of the present invention. a brightness distribution map of the displayed test images when the phases are inconsistent; and FIG. 8 is a test of a flat display module according to a preferred embodiment of the present invention. Another system of FIG. Description of component symbols: 1, 3 flat display module '11, 31 display panel - 111~11N display area 12 special application integrated circuit 121, 122 clock signal 123, STH start pulse signal 124 image signal 16 200842803
13 基板 14、32 .垂直移位暫存器 15、33 水平移位暫存器 2 測試系統 21 相位調整電路 秦 2Γ 計算裝置 22 測試影像產生電路 22， 啟動裝置 23 時序控制電路 24 伽瑪校正電路 25 源極驅動電路 26 影像感測單元 27 記憶單元 28 暫存器 Cl 擷取影像 CKH 時脈訊號 XCKH 時脈訊號 DS 貨料訊號 LS 啟動訊號 PAS 相位調整訊號 TI 測試影像 P01-P06 測試方法之程序 1713 Substrate 14, 32. Vertical shift register 15, 33 Horizontal shift register 2 Test system 21 Phase adjustment circuit Qin 2 Γ Computing device 22 Test image generation circuit 22, Start device 23 Timing control circuit 24 Gamma correction circuit 25 Source Drive Circuit 26 Image Sensing Unit 27 Memory Unit 28 Register C Capture Image CKH Clock Signal XCKH Clock Signal DS Material Signal LS Start Signal PAS Phase Adjustment Signal TI Test Image P01-P06 Test Method Procedure 17