TW200632741A - A method for a processor, and a processor - Google Patents
A method for a processor, and a processorInfo
- Publication number
- TW200632741A TW200632741A TW094132516A TW94132516A TW200632741A TW 200632741 A TW200632741 A TW 200632741A TW 094132516 A TW094132516 A TW 094132516A TW 94132516 A TW94132516 A TW 94132516A TW 200632741 A TW200632741 A TW 200632741A
- Authority
- TW
- Taiwan
- Prior art keywords
- data packet
- processor
- pipeline
- data
- admittance
- Prior art date
Links
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention presents a method for a processor (1), and a processor comprising a processing pipeline (2) and at least one interface (3) for data packets. The method is characterized by giving a second data packet (D2) admittance to the pipeline (2) in dependence on cost information (c1), dependent upon an expected time period of residence of a first data packet (D1) in at least a part (P1, .. , PK) of the pipeline (2). The first data packet (D1) can be identical with the second data packet, but preferably, the first data packet (D1) enters the pipeline (2) before the second data packet (D2).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE0403128A SE0403128D0 (en) | 2004-12-22 | 2004-12-22 | A method for a processor, and a processor |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200632741A true TW200632741A (en) | 2006-09-16 |
TWI394078B TWI394078B (en) | 2013-04-21 |
Family
ID=34075257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW94132516A TWI394078B (en) | 2004-12-22 | 2005-09-20 | A method for a processor, and a processor |
Country Status (3)
Country | Link |
---|---|
CN (1) | CN100570551C (en) |
SE (1) | SE0403128D0 (en) |
TW (1) | TWI394078B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105474168B (en) | 2014-06-30 | 2018-03-09 | 华为技术有限公司 | The data processing method and relevant device that network equipment performs |
CN108628277B (en) * | 2018-08-16 | 2020-07-24 | 珠海格力智能装备有限公司 | Distribution processing method, device and system for workstations |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1021143C (en) * | 1985-10-19 | 1993-06-09 | 霍尼韦尔布尔公司 | Multiprocessor shared pipeline cache memory |
JPH11272627A (en) * | 1998-03-23 | 1999-10-08 | Nec Corp | Pipeline type multiprocessor system |
WO2001016714A1 (en) * | 1999-09-01 | 2001-03-08 | Intel Corporation | Fast write instruction for micro engine used in multithreaded parallel processor architecture |
US6757249B1 (en) * | 1999-10-14 | 2004-06-29 | Nokia Inc. | Method and apparatus for output rate regulation and control associated with a packet pipeline |
US7155570B1 (en) * | 2000-09-29 | 2006-12-26 | Intel Corporation | FIFO write/LIFO read trace buffer with software and hardware loop compression |
KR100800958B1 (en) * | 2001-10-04 | 2008-02-04 | 주식회사 케이티 | Method for controlling traffic flow using token bucket |
-
2004
- 2004-12-22 SE SE0403128A patent/SE0403128D0/en unknown
-
2005
- 2005-09-20 TW TW94132516A patent/TWI394078B/en active
- 2005-12-20 CN CNB2005800445729A patent/CN100570551C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN100570551C (en) | 2009-12-16 |
TWI394078B (en) | 2013-04-21 |
CN101088065A (en) | 2007-12-12 |
SE0403128D0 (en) | 2004-12-22 |
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