NL2013298B1

NL2013298B1 - A Photovoltaic cell with a passivation layer as well as a method for manufacturing such a photovoltaic cell.

Info

Publication number: NL2013298B1
Application number: NL2013298A
Authority: NL
Inventors: Hendrik August Granneman Ernst
Original assignee: Asm Int Nv
Priority date: 2014-08-04
Filing date: 2014-08-04
Publication date: 2016-09-21
Also published as: TW201622161A; WO2016022026A1

Abstract

A method for manufacturing a photovoltaic cell, wherein the method includes providing a wafer of Si-bulk material having a rear surface on a rear side which, in use, will be turned away from the sun and having a front surface on a front side which, in use, will be facing the sun. The method includes depositing an AbO s-layer; depositing a Si02-layer on top of the AbOs-layer; and depositing a SiNx-capping layer on top of the Si02-layer. Also disclosed a photovoltaic cell having such a stack of layers on its rear surface for p-type Si-wafers and on its front surface for n-type Si-wafers.

Description

Title: A Photovoltaic cell with a passivation layer as well as a method for manufacturing such a photovoltaic cell

FIELD

The present invention relates to the production of photovoltaic cells as well as to photovoltaic cells.

BACKGROUND

In the production of photovoltaic cells, there is a constant struggle for obtaining better efficiencies. Generally, photovoltaic cells include a wafer of Si-bulk material. In the Si crystals the incoming photons are converted into electron/hole-pairs. The Si-wafer can be doped, for example with phosphor and/or boron, so that the front side has a positive charge and the rear side has a negative charge or vice versa. Consequently, in the photovoltaic cell a electric field is present. When fight is shed on the front side, electron/hole pair is formed thus forming free charge carriers (electron and holes). These charge carriers tend to flow to the side of the wafer that inherently has the opposite charge due to the doping of the Si-wafer. Electrical conductors both at the front side and the rear side are present to connect the Si-bulk material to an external circuit to be fed with the electric current that is generated in the photovoltaic cell. A more extensive explanation of the working mechanism of photovoltaic cells can be found in httD://science.howstufiworks.com/environmental/energy/solar-cell.htm of which the contents are incorporated herein by reference.

One of the problems in p-type Si photovoltaic cells is the recombination of electrons and holes at the rear surface of the cell. Instead of flowing to an electrical conductor present on that surface to feed the external circuit, the electrons are neutralized at the surface by non-terminated Si-x bonds. Electrons and holes recombine at these sites which leads to a loss of electrical energy available for the electrical circuit. The same problem also occurs at with n-type Si photovoltaic cells but then on the front side. To solve this problem, two solutions are known: 1. Make sure the non-terminated Si-x bonds become terminated by bonding an H-atom to it so as to form Si-H. This reduces the so-called interface state density (Dit); and 2. Deposit a dielectric film with an intrinsic negative charge on or close to the Si surface.

The two solutions can be provided with the application of an Al203-layer. An AhOa-layer contains a large concentration of hydrogen bonded to other atoms in various forms: H2, Al-OH, H2O. The exact composition is unknown, however, the total hydrogen content is 10-15 % (at%). The Al203-layer forms the hydrogen source for terminating the non-terminated Si-x bonds. The AhOe-layer also is a dielectric film with intrinsic negative charge on the Si surface. So electrons that flow to the Si-surface instead of to an electrical conductor are repelled by the negative charge of the negative charge of the Ah03-layer.

Another aspect that plays a role in the present invention is that the interface between the surface of a Si-wafer and the deposited AI2O3 layer is intrinsically covered with a , typically with a thickness of 1 to 1.5 monolayers. Such a SiCh-monolayer may already be present before depositing the AbOe-layer, but if not, then it will be formed during the deposition of the AhOs-layer

SUMMARY

The problem the present invention wants to solve is the formation of blisters between AhOs-layer and the SiCh-monolayer during subsequent process steps in which the wafer is subjected to heat treatment, for example a firing treatment for solidifying a conductive paste that has been applied for the formation of electrical conductors on the surface of the wafer. Such a firing treatment is executed at a temperature of typically approximately 800°C.

Research has revealed that during such a temperature treatment, the hydrogen that is released from the AFOe-layer and that enters the S1O2-monolayer is able to diffuse very effectively through the thin interfacial Si02-monolayer in lateral direction. The hydrogen accumulates at crystal grain boundaries and surface defects of the Si-bulk material thereby creating blisters which are filled with hydrogen, see e.g. the paper: Analysis of Blister Formation in ALD AI2O3 for Silicon Surface Passivation from L. Hennen, E.H.A. Granneman, W.M.M. Kessels, 38th IEEE PVSC conference, June 4-8, 2012, Austin, and the references therein. A Si-wafer covered with an AbOe-layer and being subjected to a subsequent process step involving the application of heat is shown in Fig. 1. Clearly visible are the Si crystals 10, the crystal grain boundaries 12 of the Si-bulk material and the blisters 14 formed by accumulation of hydrogen. At the location of these blisters, the AbOe-layer is lifted off from the Si-bulk material and thus the source of hydrogen -formed by the Ab03-layer - for passivation of the non-terminated Si-x bonds is not present anymore. In some severe cases, the blisters may even tear due to expansion of the hydrogen present therein as a consequence of the applied heat. Blister formation is detrimental to the overall efficiency of the photovoltaic cell due to the reduced passivation performance of the AI2O3-layer. The formation of blisters becomes more severe when a SiNx-capping layer is deposited on top of the AbOe-layer because then the hydrogen can not or only in a very limited amount diffuse out and desorb at the top side of the AbOe-layer. Consequently, the amount of hydrogen that will be released in the SiC>2-layer will be larger and thus the formation of blisters will be more abundant. On the other hand, the application of a SiNx-capping layer is highly desirable because it has two functions.

For p-type cells on the rear surface: 1. to act as a mirror reflecting long-wavelength (IR) radiation back into the cell, thereby increasing the light-capture efficiency; and 2. to provide protection against external influences such as moisture, mechanical impact because the SiNx-capping layer is hard and substantively impermeable for moisture; and for n-type cells, on the front surface: 1. to act as an anti-reflection coating (ARC) so as to transmit radiation in the visible part of the spectrum in the most efficient way; and 2. to provide protection against external influences such as moisture, mechanical impact because the SiNx-capping layer is hard and substantively impermeable for moisture.

As the function of the SiNx layer is different for p- and n-type devices, the thicknesses of the SiNx layer in p- and n-type cells may be different.

Recently, a method for the reduction of blister formation has been proposed that involves a so-called Post-Deposition Anneal (PDA) at a temperature of approximately 600°C during 20 minutes. It should be noted that other combinations of time and temperature in the range of 500°C -800°C will work as well. PDA was first proposed by B. Vermang, et al, Proc. 26th European PVSEC, Hamburg, September 5-8, 2011. Such a PDA reduces the hydrogen content in the AhOe-layer through out-diffusion of hydrogen. An SiNx-capping layer is deposited after the PDA. The procedure works reasonably well, however, the disadvantage is that this procedure adds costs to the photovoltaic cell manufacturing process because an additional PDA furnace must be placed in the production line.

The present invention is directed to providing another solution to alleviate the formation of blisters under an AhOe-layer.

To that end the invention provides a method for manufacturing a photovoltaic cell, the method including in this order: - providing a wafer of Si-bulk material having a rear surface on a rear side which, in use, will be turned away from the sun and having a front surface on a front side which, in use, will be facing the sun - depositing an AhOe-layer on the rear surface for p-type Si-wafers or on the front surface for n-type Si-wafers - depositing a SiC>2-layer on top of the AbOe-layer; and - depositing a SiNx-capping layer on top of the SiC>2-layer.

As the diffusion of hydrogen in S1O2 is very fast, the Si02-layer on top of the Al203-layer acts as a sink for the excess hydrogen that is present in the AbOe-layer. In this way, the hydrogen concentration in the AI2O3-layer is reduced and the formation of blisters caused by lateral diffusion and local accumulation of hydrogen in the interfacial Si02-monolayer will be alleviated or completely prevented even when a SiNx-capping layer is applied on top of the Si02-layer. The PDA will be refrained from and thus the additional furnace in the production line is not necessary thereby reducing the production costs of the photovoltaic cells.

In an embodiment the depositing of the Si02-layer on top of the Al203-layer may be effected by using a PECVD-processing assembly. PECVD is a very quick and efficient process to apply the S1O2- layer.

In an embodiment, the depositing of the SiNx-capping layer on top of the Si02-layer may be effected by using the same PE CVD-processing assembly as the PE CVD-processing assembly that is used for the depositing of the Si02-layer on top of the AbOe-layer. Because both the Si02-layer as well as the SiNx-capping layer are applied with the same PECVD-processing assembly, the novel method for prevention of blisters can be applied with only minimal additional costs for the production line. The PECVD-processing assembly is present anyway for the application of the SiNx-capping layer in a quick and efficient manner. The Si02-layer can be applied with the same tool by simply changing the precursor gases used in the PECVD-processing assembly.

In an embodiment, the depositing of the Ah03-layer may executed with an atomic layer deposition process. With this method, a very thin and accurately formed AbOe-layer may be applied in an efficient manner.

In an embodiment, the method may include: - creating holes and/or trenches that extend through the SiNx-capping layer, Si02-layer deposited on top of the AhOe-layer, the AhOe-layer, and the interfacial Si02-monolayer up to the Si-bulk material; and - screen printing an electrically conductive paste in the holes and/or trenches to create electrical conductors.

This is an efficient method to provide electrical conductors on the rear surface for p-type Si-wafers or on the front side for n-type Si-wafers.

In an embodiment, the creation of the holes and/or trenches may be effected by using a laser.

By using a laser, the applied layers are only very locally removed without destroying the structure of the stack of layers directly adjacent the trenches and the holes. Additionally, the laser abrasion for locally removing the stack of layers can be done very quickly.

In an embodiment, the electrically conductive paste may be an Al-paste for p-type Si-wafers or an Ag-paste for n-type Si-wafers.

In an embodiment, after application of the electrically conductive paste the wafer or the side of the wafer on which the paste has been applied may be subjected to a firing process at a temperature in the range of 700°C - 900°C.

With this firing process, the paste will solidify and be effectively bonded to the Si-bulk material of the wafer as well as the SiNx-capping layer.

The invention also provides a photovoltaic cell comprising: - a wafer of Si-bulk material having a rear surface which, in use, is turned away from the sun and having a front surface which, in use, is facing the sun; - an Al203-layer deposited directly on the rear surface for p-type Si-wafers or on the front surface for n-type Si-wafers; - an interfacial Si02-monolayer between the Si-bulk material of the wafer and the AhOe-layer; - a Si02-layer on top of the A^Oe-layer; and - a SiNx-capping layer on top of the SiC>2-layer.

With such a photovoltaic cell, the formation of blisters under the Al203-layer is alleviated or even prevented. A PDA-treatment can be refrained from and, consequently, the production line does not need to include a PDA furnace which is a reduction in costs for the production line of approximately 400,000-600,000 $.

In an embodiment, the Al203-layer may be an ALD-deposited layer and the SiO2-layer on top of AhOe-layer and the SiNx-capping layer may be PECVD-deposited layers.

Because both the SiC>2-layer as well as the SiNx-capping layer may be formed with the same PECVD-processing assembly, the additional costs for realizing the solution according to the invention may be very limited.

Good results with no or only very limited formation of blisters may be obtained when: - the interfacial Si02-monolayer formed during the AI2O3 deposition process has a thickness in the range of 0,5 to 1.5 monolayer in other words a thickness of less than 1 nm; - the AhOe-layer has a thickness in the range of 2-40 nm, preferably approximately 6 nm; - the Si02-layer on top of the AhOs-layer has a thickness in the range of 10-400nm, preferably approximately 40nm; and/or - the SiNx-capping layer has a thickness in the range of 20-300nm, preferably approximately lOOnm for capping the rear side of p-type cells and 80nm for ARC layer on the front side of n-type cells.

For a Si-wafer that is of the p-type, the thickness of the Si02-layer and the thickness of the SiNx-capping layer may, in an embodiment, each be chosen such that the stack of these two layers acts as a mirror that reflects IR-wavelength radiation from the rear side of the cell back into the cell to increase the light-capture efficiency.

In further elaboration of that embodiment, the Si02-layer may have a thickness of approximately 40 nm and the SiNx-capping layer may have a thickness of approximately 80 nm.

For a Si-wafer that is of the n-type, the thickness of the SiC>2-layer on top of the AROe-layer and the thickness of the SiNx-capping layer may, in an embodiment, each be chosen such that the stack of these two layers acts as anti-reflection coating that transmits fight in the visible range of the radiation spectrum so as to increase the fight-capture efficiency.

In a further elaboration of that embodiment, the SiC>2-layer may have a thickness of approximately 40 nm and the SiNx-capping layer may have a thickness of approximately 80 nm.

In an embodiment, the Si02-layer deposited on the AhOe-layer may have a thickness that is at least three times, and preferably at least four times the thickness of the AhOe-layer.

In such an embodiment, the hydrogen absorption capacity of the deposited Si02-layer suffices to reduce the hydrogen content in the AI2O3-layer with a factor 4 or 5 which is enough to prevent or largely prevent the formation of blisters.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a picture of the surface of Si-bulk material that has been covered with an AhOe-layer and that has undergone a heat treatment in a subsequent process step;

Fig. 2 shows a cross sectional view of an example of a p-type photovoltaic cell according to the invention;

Fig. 3 is a detail III from figure 2; and

Fig. 4 is detail IV from figure 2.

DETAILED DESCRIPTION

It should be noted that the embodiments of the invention are not limited to examples shown in the figures. Some of the embodiments provide solutions to the problem of water ingress as mentioned above. The embodiments may be applied independently from each other or may be combined.

In the example given below, we focus on the manufacturing of passivating film stacks on the rear side of p-type cells. For readers skilled in the art it will be obvious that the same principle holds for the front surface of n-type cells on which an AbCL-layer is applied for passivating the non-terminated Si-x bonds.

Fig. 1 shows a picture of the rear side of a prior art photovoltaic cell. Clearly visible are the Si-crystals 10 and crystal boundaries 12. On the rear surface of the Si-bulk material the following stack of layers is present: - an interfacial Si02-monolayer having a thickness of approximately 1 or 1,5 monolayers formed during the deposition of an AbOa-layer; - a Ah03-layer; and - SiNx-capping layer.

After a subsequent application of heat, e.g. during a firing process step in which the temperature is raised up to approximately 800°C, hydrogen from the AhOe-layer is released to the native Si02-monolayer. Due to very fast lateral diffusion of hydrogen in the native Si02-monolayer blisters 14 are formed.

Figs. 2-4 show an example of a photovoltaic cell in which various embodiments described in the introductory portion of this specification are realized. The photovoltaic cell 20 includes a wafer 22 of Si, in this example Si of the p-type. The front surface 22a may be texturized to increase the surface area thereof. The front surface 22a may be doped with phosphor or boron to provide a charge at that surface. When the Si-bulk material is of the p-type, the front surface 22a may be doped with phosphor so that the front surface 22a will be negatively doped. This creates an electrical field extending perpendicularly to the front and the rear surfaces 22a, 22b within the Si-wafer 22. Relative to the front surface 22a, the remainder of the Si-bulk material of the Si-wafer is positively charged. When hit by a photon, an electron/hole pair is formed and the electron tends to move to the positive side of the Si-wafer. At the rear side electrical conductors 24 are in electrically conductive contact with the Si-bulk material of the Si-wafer. At the front side electrical conductors 26 are in electrically conductive contact with the Si-bulk material of the Si-wafer as well. These electrical conductors 24, 26 are connected to an electrical circuit that consumes electrical energy. In the example, reference number 28 indicates the phosphor doped part of the Si-bulk material. On the phosphor doped part a native Si02-monolayer 28’ of 1 or 1.5 monolayers thickness may be present. On top of the negatively doped layer, a SiNx-capping layer 30 may be applied as well as an anti-reflection layer 32. Optionally, before depositing the SiNx-capping layer 30, a thin Si02-layer 42 having a thickness of a few nm may be applied and on top of that a thin AhOe-layer 44 having a thickness of a few nm. When the Si02-layer 42 is thick enough, the negative charge of the AhOe-layer 44 is shielded and only the positive effect of the large hydrogen supply of the AhOe-layer 44 remains in order to passivate the dangling Si-x bonds.

As shown in figure 2, an interfacial Si02-monolayer 34 is present between the Si-bulk material 22 and an AhOe-layer 36 that is deposited on the Si-bulk material 22. The Si02-monolayer may already be present before deposition of the AhOe-layer 36 but when no such Si02-monolayer 34 is natively present, then it will be created during the deposition AhOe-layer 36 because of the use oxidizing gases during deposition of the Al203-layer 36 such as 0 2 or H2O. In the present example the deposition of the AhOe-layer 36 is done at the rear side because the example relates to a p-type Si-wafer. When dealing with a n-type Si-wafer, the stack of layers that in this example is present on the rear side would be present on the front side. The interfacial Si02-monolayer 34 has a thickness D1 of approximately 0.5 to 2 nm. On top of the interfacial SiO2-monolayer 34 the AhOe-layer 36 is present. The thickness D2 of the AhOe-layer may be in the range of 2-40, preferably approximately 6 nm. On top of the Al203-layer 36, a Si02-layer 38 is provided which serves to reduce the hydrogen content in the Al203-layer 36 so that the formation of blisters is prevented when the wafer is subjected to subsequent processing steps in which heat is supplied to the wafer. The Si02-layer may have a thickness D3 in the range of 10-100 nm, preferably approximately 40 nm. On top of the Si02-layer 38 a SiNx-capping layer 40 is provided to protect the underlying layers from moisture and provide protection against mechanical impact. The SiNx-capping layer may have a thickness D4 in the range of 20-200 nm, preferably approximately 80 nm.

For p-type Si-wafers, the Si02-layer 38 in combination with the SiNx-capping layer 40 may act as a mirror to reflect IR-radiation, which will increase the efficiency of the photovoltaic cell. To that end, the SiC>2-layer may have a thickness D3 of approximately 40 nm and the SiNx-capping layer may have a thickness D4 of approximately 80 nm.

For n-type Si-wafers, the thickness of the Si02-layer on top of the Al203-layer and the thickness of the SiNx-capping layer may each be chosen such that the stack of these two layers acts as anti-reflection coating that transmits light in the visible range of the radiation spectrum so as to increase the light-capture efficiency. To that end, the SiC>2-layer may have a thickness of approximately 40 nm and the SiNx-capping layer may have a thickness of approximately 80 nm.

Although illustrative embodiments of the present invention have been described above, in part with reference to the accompanying figures, it is to be understood that the invention is not hmited to these embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the figures, the disclosure, and the appended claims. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, it is noted that particular features, structures, or characteristics of one or more embodiments may be combined in any suitable manner to form new, not explicitly described embodiments.

Claims

1. Een werkwijze voor het vervaardigen van een fotovoltaïsche cel, waarbij de werkwijze in deze volgorde omvat: - het verschaffen van een wafer van Si-bulkmateriaal die een achteroppervlak aan een achterzijde heeft die, in gebruik, is afgekeerd van de zon en die een vooroppervlak aan een voorzijde heeft die, in gebruik, naar de zon is gericht; - het deponeren van een AhOa-laag op het achteroppervlak voor p-type Si-wafers of op een vooroppervlak voor n-type Si-wafers; - het bovenop de AhOe-laag deponeren van een Si02-laag; en - het bovenop de Si02-laag deponeren van een SiNx-afdeklaag.A method for manufacturing a photovoltaic cell, the method comprising in the following order: - providing a wafer of Si-bulk material that has a rear surface at a rear that, in use, faces away from the sun and that has a has a front surface that faces the sun when in use; - depositing an AhOa layer on the back surface for p-type Si wafers or on a front surface for n-type Si wafers; depositing an SiO 2 layer on top of the AhOe layer; and - depositing a SiNx cover layer on top of the SiO 2 layer.

2. De werkwijze volgens conclusie 1, waarbij het deponeren van de S1O2-laag op de AhOe-laag wordt uitgevoerd onder gebruikmaking van een PECVD-bewerkingssamenstel.The method of claim 1, wherein depositing the S102 layer on the AhOe layer is performed using a PECVD processing assembly.

3. De werkwijze volgens conclusie 2, waarbij het deponeren van de SiNx-afdeklaag bovenop de Si02-laag wordt uitgevoerd onder gebruikmaking van hetzelfde PECVD-bewerkingssamenstel als het PECVD-bewerkingssamenstel dat is gebruikt voor het deponeren van de Si02-laag op de AhOe-laag.The method of claim 2, wherein depositing the SiNx cover layer on top of the SiO 2 layer is performed using the same PECVD processing assembly as the PECVD processing assembly used to deposit the SiO 2 layer on the AhOe low.

4. De werkwijze volgens één van de conclusies 1-3, waarbij het deponeren van de AhOe-laag wordt uitgevoerd met een atoomlaagdepositiebewerking.The method of any one of claims 1-3, wherein depositing the AhOe layer is performed with an atomic layer position operation.

5. De werkwijze volgens conclusie 1, omvattend: - het creëren van gaten en/of sleuven die zich uitstrekken door de SiNx-afdeklaag, de Si02-laag die op de AbOa-laag is gedeponeerd, de AI2O3-laag, en een tussenlaagse Si02-monolaag tot in het Si-bulkmateriaal; en - het screenprinten van een elektrisch geleidende pasta in de gaten en/of sleuven om elektrische geleiders de creëren.The method of claim 1, comprising: - creating holes and / or slots extending through the SiNx cover layer, the SiO2 layer deposited on the AbOa layer, the Al2 O3 layer, and an interlayer SiO2 monolayer down to the Si bulk material; and - screen printing an electrically conductive paste in the holes and / or slots to create electrical conductors.

6. De werkwijze volgens conclusie 5, waarbij het creëren van de gaten en/of sleuven wordt uitgevoerd onder gebruikmaking van een laser.The method of claim 5, wherein the creation of the holes and / or slots is performed using a laser.

7. De werkwijze volgens conclusie 5 of 6, waarbij de elektrische geleidende pasta een Al-pasta is voor p-type Si-wafers of een Ag-pasta voor n-type Si-wafers.The method of claim 5 or 6, wherein the electrically conductive paste is an Al paste for p-type Si wafers or an Ag paste for n-type Si wafers.

8. De werkwijze volgens één van de voorgaande conclusies, waarbij na het aanbrengen van de elektrisch geleidende pasta de wafer of de zijde van de wafer waarop de pasta is aangebracht wordt onderworpen aan een gloeibewerking bij een temperatuur in het bereik van 700°C - 900°C.The method according to any of the preceding claims, wherein after applying the electrically conductive paste the wafer or the side of the wafer on which the paste is applied is subjected to an annealing operation at a temperature in the range of 700 ° C - 900 ° C.

9. Een fotovoltaïsche cel omvattend: - een wafer van Si-bulkmateriaal met een achteroppervlak dat, in gebruik, is afgekeerd van de zon en met een vooroppervlak dat, in gebruik, naar de zon is gekeerd; - een ADOa-laag die direct op het achteroppervlak voor p-type Si-wafers of op het vooroppervlak voor n-type Si-wafers is gedeponeerd; - een tussenlaagse Si02-monolaag die is gevormd tussen het Si-bulkmateriaal van de wafer en de AhOa-laag; - een Si02-laag bovenop de AhOe-laag; en - een SiNx-afdeklaag bovenop de SiCL-laag.A photovoltaic cell comprising: - a wafer of Si-bulk material with a back surface that, in use, faces away from the sun and with a front surface that, in use, faces the sun; - an ADOa layer deposited directly on the rear surface for p-type Si wafers or on the front surface for n-type Si wafers; - an interlayer SiO 2 monolayer formed between the Si bulk material of the wafer and the AhOa layer; - an SiO 2 layer on top of the AhOe layer; and - a SiNx cover layer on top of the SiCL layer.

10. De fotovoltaïsche cel volgens conclusie 9, waarbij de AbOa-laag een ALD-gedeponeerde laag (Atomic Layer Deposition) is en waarbij de S1O2-laag bovenop de AbOe-laag en de SiNx-afdeklaag PECVD-gedeponeerde lagen (Plasma Enhanced Chemical Vapour Deposition) zijn.The photovoltaic cell according to claim 9, wherein the AbOa layer is an ALD deposited layer (Atomic Layer Deposition) and wherein the S1O2 layer on top of the AbOe layer and the SiNx cover layer PECVD deposited layers (Plasma Enhanced Chemical Vapor) Deposition).

11. De fotovoltaïsche cel volgens conclusie 9 of 10, waarbij tussenlaagse Si02-monolaag een dikte heeft in het bereik van 0,5 - 2 nm.The photovoltaic cell according to claim 9 or 10, wherein interlayer SiO 2 monolayer has a thickness in the range of 0.5 - 2 nm.

12. De fotovoltaïsche cel volgens één van de conclusies 9-11, waarbij de AhCL-laag een dikte heeft in het bereik van 2-40 nm, bij voorkeur ongeveer 6 nm.The photovoltaic cell according to any of claims 9-11, wherein the AhCL layer has a thickness in the range of 2-40 nm, preferably about 6 nm.

13. De fotovoltaïsche cel volgens één van de conclusies 9-12, waarbij de Si02-monolaag bovenop de Ah03-laag een dikte heeft in het bereik van 10 - 100 nm.The photovoltaic cell according to any of claims 9-12, wherein the SiO 2 monolayer on top of the AhO 3 layer has a thickness in the range of 10 - 100 nm.

14. De fotovoltaïsche cel volgens één van de conclusies 9-13, waarbij de SiNx-afdeklaag een dikte heeft in het bereik van 20-200 nm, bij voorkeur ongeveer 80 nm.The photovoltaic cell according to any of claims 9-13, wherein the SiNx cover layer has a thickness in the range of 20-200 nm, preferably about 80 nm.

15. De fotovoltaïsche cel volgens één van de conclusies 9-14, waarbij de Si-wafer van het p-type is en waarbij de dikte van de Si02-laag en de dikte van de SiNx-afdeklaag elk zodanig zijn gekozen dat de stapel van deze twee lagen als een spiegel werken die straling reflecteert met een golflengte in het infraroodbereik vanaf een achterzijde van de cel terugwaarts in de cel om de licht-invangefficiency te vergroten.The photovoltaic cell according to any of claims 9-14, wherein the Si wafer is of the p-type and wherein the thickness of the SiO 2 layer and the thickness of the SiNx cover layer are each selected such that the stack of these two layers act as a mirror that reflects radiation with a wavelength in the infrared range from a backside of the cell back into the cell to increase the light capture efficiency.

16. De fotovoltaïsche cel volgens conclusie 15, waarbij de Si02-laag een dikte heeft van ongeveer 40 nm en waarbij de SiNx-afdeklaag een dikte heeft van ongeveer 80 nm.The photovoltaic cell of claim 15, wherein the SiO 2 layer has a thickness of about 40 nm and wherein the SiN x cover layer has a thickness of about 80 nm.

17. De fotovoltaïsche cel volgens één van de conclusies 9-14, waarbij de Si-wafer van het n-type is en waarbij de dikte van de SiC>2-laag bovenop de AhOe-laag en de dikte van de SiNx-afdeklaag zodanig zijn gekozen dat de stapel van deze twee lagen als een anti-reflectiecoating functioneert die licht in het zichtbare gebied van het stralingsbereik doorlaat om aldus de licht-invangefficiency te vergroten.The photovoltaic cell according to any of claims 9-14, wherein the Si wafer is of the n-type and wherein the thickness of the SiC> 2 layer on top of the AhOe layer and the thickness of the SiNx cover layer such have been chosen that the stack of these two layers function as an anti-reflection coating that transmits light in the visible region of the radiation range so as to increase the light capture efficiency.

18. De fotovoltaïsche cel volgens conclusie 17, waarbij de Si02-laag een dikte heeft van ongeveer 40 nm en waarbij de SiNx-afdeklaag een dikte heeft van ongeveer 80 nm.The photovoltaic cell of claim 17, wherein the SiO 2 layer has a thickness of about 40 nm and wherein the SiN x cover layer has a thickness of about 80 nm.

19. De fotovoltaïsche cel volgens één van de conclusies 9-18, waarbij de Si02-laag die is gedeponeerd op de AhOe-laag een dikte heeft die ten minste drie keer, en bij voorkeur ten minste vier keer de dikte van de AhOa-laag bedraagt.The photovoltaic cell of any one of claims 9-18, wherein the SiO 2 layer deposited on the AhOe layer has a thickness that is at least three times, and preferably at least four times, the thickness of the AhOa layer amounts.