MXPA00001397A - A modular time-space switch - Google Patents

Abstract

The present invention relates to a switch structure for circuit switching. According to the invention, part of the space switch functionality of a time-space (TS) switch core is broken out and arranged in groups of switch adapter boards, and the TS-switch core itself is divided into a matrix of smaller and independent TS-modules that are associated with the switch adapter boards. Each group of switch adapter boards is co-operating with a predetermined row of TS-modules in the matrix for input of data to the TS-modules in that row, and with a predetermined column of TS-modules in the matrix for output of data from the TS-modules of that column. In this way, it is possible to implement the switch structure into a number of subracks with a reasonable number of interconnections between different subracks, thus obtaining a truly modular TS-switch structure.

Description

C0 MUT7? MODULAR TIME-SPACE D0R TECHNICAL FIELD OF THE INVENTION The invention relates in general terms to the technology of telecommunication, data communication and switching, and more particularly to a new switching architecture for switching circuits. BACKGROUND OF THE INVENTION Switching is basically a matter of organizing the flow of information between subscribers in a telecommunication system or of communicating data in such a way that they can communicate with each other. Therefore, switches are fundamental components of the communication system. They allow a subscriber to connect with any other remote subscriber in the system. In accordance with a particular type of switching which is known as circuit switching, the subscriber information is normally assigned to time segments and the actual switching is carried out in these time segments. Accordingly, in this case, a switch can be defined as a structure for handling time slots in such a way that the subscriber information is switched or connected from an arbitrary input point of the switch to an arbitrary output point. The basic building blocks of the switches are generally time switch stages (T) and space switch stages (S). By combining the time switch stages and the space switch stages in different ways, several switching structures are obtained. Examples of such switching structures are time-space-time (TST) switches, or space-time-space switches (STS), time-space switches (TS), TSST switches and SSTSS switches. The time-space switch (TS) is especially interesting because of its many advantages. First, and most importantly, the TS switch is inherently strictly non-blocking for point-to-point connections as well as for broadcast. For other types of switches, point-to-point blocking can be alleviated by applying the well-known Clos theorem. For TST switches, for example, Clos's theorem states that the number of internal time slots must be duplicated in order to achieve non-blocking for point-to-point connections. However, when it comes to emission, blocking will occur in the TST switches. Examples of other advantages of the TS switch structure are shown below: short delay through the switch; - single path selection; and - simple control path.

Furthermore, the voice storage memories that are commonly used in TS switches are more economical, making the switch structure TS interesting also for larger switches. However, due to the large number and complexity of internal connections between the voice stores, control stores and multiplexers in a TS switch structure, the switch TS is generally considered as indivisible and non-modular. The internal components of a TS switch must be arranged together tightly in order to make virtually all connections. For this reason, the TS switch must be installed in a single sub-frame. Accordingly, the size of the sub-frame sets a limit for the maximum capacity of the TS switch and the available sub-frames are limited in size. Large conventional TS switches have a capacity of 128 K, even when state-of-the-art TS switches have reached up to 216 K when the technology limit is sought, tightening as many components and possible cable connections in the same sub -frame. In many telecommunication applications, higher capacities, of the order of 256 or 512 K, are required, which makes the conventional TS switch structure insufficient. further, there is no simple way to offer capacity growth for smaller conventional TS switches at capacities that are within the conventional capability range of up to 128K. As an example, it is not easy to extend a conventional TS switch installed with a capacity of 16 K at a capacity of 64 K. This makes the conventional TS switch structure not only insufficient in terms of its maximum capacity but also inflexible in terms of its capacity growth. European patent application 0,558,291 A2 presents a reconfigurable switch memory which is applicable to time switches and space switches in such a way that two very different time switching functions can be implemented efficiently by a type of switching unit. European patent application 0,558,291 A2 also has a reconfigurable STM switching unit that can operate in either a one-bit or a 5-bit mode in such a way that the granularity of the switch can be varied. In accordance with the European patent application, a simple way to offer growth is through the use of more switching units and operating these units in parallel. The international patent application with the publication number 095/32599 presents a cross-connection architecture for switching digital signals in which the input stage is composed of time-space switch blocks (TS) in parallel, the center stage is It consists of parallel blocks formed by time and space switches (STS; TxT-S) and the output stage consists of space-time switch blocks (ST) in parallel. In order to make the architecture nonblocking, the number of blocks in the center stage is doubled compared to the minimum number of blocks. Apparently, the international patent application WO 95/32599 relates to a complex multi-stage switching architecture. COMPENDIUM OF THE INVENTION The invention overcomes these drawbacks and other drawbacks of the prior art. A general object of the invention is to provide a flexible and robust switch architecture for circuit switching. Another object of the present invention is to offer a modular switch structure in which non-blocking and the possibility of increasing capacity are combined. A modular switch has advantages in terms of costs and flexibility. By way of example, it is possible to start with a small switch with a single switch module or only some modules at a relatively low cost. If the need for greater capacity subsequently arises, then an appropriate number of additional switch modules are easily added in such a way that the overall switch is larger. It is also desired to employ the Time-Space (TS) switch structure with all its advantages, as the basis for the modular switch architecture. Particularly, high capacities such as 256 K, 512 K or more must be easy to realize with this new modular TS switch architecture. These and other objects are solved by the invention defined in the appended claims. The general idea in accordance with this invention is to split part of the space switch functionality (s) from the time-space switch (TS) core and to arrange this part of the space functionality in groups of switch adapter boards, and dividing the relatively large TS switch core into a smaller independent TS module matrix that are associated with the switch adapter boards. Each group of switch adapter boards cooperates with a predetermined row of TS modules for data entry to the modules, and with a predetermined column of TS modules for data output from the modules. By splitting the space switch (s) functionality into two parts, a first part in the TS modules and a second part in the switch adapter boards, and by interconnecting the TS modules and adapter boards In this manner, it is possible to implement the switch structure in several subframes with a reasonable number of interconnections between different subframes, thus obtaining a truly modular switching architecture based on TS modules and switch adapter boards. This also makes it possible to build large TS switch structures of 512K or more. The switch architecture according to the present invention offers the following advantages: - no strict blocking; - modularity (with capacities of, for example, 8 K to 512 K or more) including all the advantages of modular structures in terms of cost, flexibility and simplicity .; - single path selection; and - short delay through the switch. Other advantages offered by the present invention will be observed upon reading the following description of the embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The novel features of the present invention are presented in the appended claims. The invention itself, however, as well as other features and advantages thereof will be better understood with reference to the detailed description of the specific embodiments that follow, when read in combination with the accompanying drawings, wherein: 1 is a schematic diagram of an illustrative example of a time-space switch unit; Figure 2 is a schematic diagram of an illustrative example of the overall architecture of a global switch structure based on TS modules in accordance with a first embodiment of the invention; Figure 3 is a schematic diagram of an illustrative example of a switch structure with a 2x2 matrix of TS modules; Fig. 4 is a schematic diagram illustrating the design principle of switch structures of different capacities based on TS modules; Fig. 5 is a schematic block diagram of an illustrative example of a 512 K switch according to the invention; Figure 6 is a schematic diagram of an illustrative example of the overall architecture of a modular switch structure in accordance with a second embodiment of the invention; Figure 7 is a schematic diagram of a group of switch adapter boards according to the second embodiment of the invention; Fig. 8 is a schematic diagram similar to the diagram of Fig. 1 illustrating a switch module TS which is divided into several fractional switch modules TS; Figure 9 is a schematic diagram of an example of a switch structure with a 2x2 matrix of TS module where equipment for writing control information is provided; Fig. 10 is a schematic diagram illustrating an example of a group of switch adapter boards according to the invention, wherein each switch adapter board includes a modified complete TS module to allow bit-level switching; Fig. 11 is a schematic diagram illustrating a switch structure according to the invention, wherein a sub-speed switch is connected in parallel with a TS switch module; Fig. 12 is a schematic diagram illustrating the principle of design of switch structures of different sizes that support a normal commutation oriented to words as well as sub-speed switching; and Figure 13 is a schematic diagram of pertinent parts of a switch adapter board associated with a total sub-speed switching capacity. DETAILED DESCRIPTION OF MODALITIES OF THE INVENTION For a better understanding of the present invention, it is useful to begin by explaining the principle of a time-space switching unit. A common way to define a time-space switch is to say that it is a switching unit in which all the inputs can be written to a number of voice stores in such a way that the written data is accessible from all the outputs. Next, an illustrative example of a time-space switch unit will be provided. However, it will be understood that this example does not limit the scope of the present invention since it is possible to employ other types of time-space switch units. Figure 1 is a schematic diagram of an illustrative example of a time-space switching unit (TS). The switch unit TS 10 basically comprises a voice store array SS where data is stored in the form of user information. The TS 10 switch unit further comprises MUX multiplexers and CS control stores associated with the SS voice stores. The switch unit of TS 10 has several input terminals IN0 to IN7 connected to several input lines, which are known as HWH motorway horizontals, and several output terminals OUT0 to 0UT7 connected to several output lines, which are known as HWV highway verticals.

The user information is provided in the HWH highway horizontals to the INO input terminals to IN7 and subsequently the SS voice stores: each SS voice store in a given row of voice store array is connected to the same terminal input so that all SS voice stores in this row receive the same data set. In addition, each column of voice stores SS is associated with a respective control store CS which controls the data read from one of the voice stores SS in the column. The reading of the data from the SS voice stores gives the time-space switch unit 10 its time-switching functionality. Each column of voice stores SS is also associated with a respective controllable multiplexer MUX in such a way that each voice store SS in the column is connected to the multiplexer MUX. In figure 1, for simplicity and in order to facilitate the reading of the drawing, a single line interconnecting all the SS voice stores of a column with a common multiplexer MUX is shown. However, it will be understood that there is a separate connection for each SS voice store in the column to the MUX multiplexer. The MUX multiplexer is connected to the corresponding control store CS and is controlled by said corresponding control store CS, and the MUX multiplexer determines from which voice store SS in the column these data must be read in response to a control information stored in the CS control warehouse. The OUTO output terminals up to 0UT7 act as an interface between the MUX multiplexers and the external HWV motorway verticals. The MUX controllable multiplexers provide the time-space switch unit 10 with its space switching functionality. As mentioned above, the TS switch is inherently strictly non-blocking. Another inert advantage of the TS switch is the simple path selection, since from a multiple position given in the output to a given multiple position in the input there is only one path and that path is always available for the connection between these multiple positions. The TS switch unit 10 illustrated in Figure 1 has 8 HWH input lines and 8 HWV output lines with an 8x8 matrix of SS voice stores. If one considers, as an example, that each HWH input line handles 8192 time segments and that each SS voice store has 8192 positions, the result will be a traditional 64K TS switch unit. Throughout the presentation, when a 1K switch unit is mentioned, we are referring in fact to a 1024 multi-position switch unit (MUP). In this way, a 64K switch unit means a switch unit of 65536 multiple positions. Conventionally, if a 128K TS switch is desired as an example, the number of input lines as well as the number of output lines must be doubled, that is 16 instead of 8, and the voice store matrix 13 of an 8x8 matrix towards a 16x16 matrix. The number of connections in the TS switch rises dramatically, and the voice stores must be arranged close to each other in a single subframe in order to realize virtually all interconnections. Due to this fact, larger TS switch structures are conventionally almost impossible to perform in practice. This problem is solved by the invention by making the global TS switch structure modular. In accordance with the present invention, a part of the space switch functionality of the TS switch core is divided and arranged into groups of switch adapter boards, and the TS switch core itself is divided into a matrix TS module modules, or TS switch units associated with the switch adapter boards. Each group of switch adapter boards cooperates with a predetermined row of TS modules to input data to the modules, and with a predetermined column of TS modules to send data from the modules. In this way, it is possible to increase the TS switch structure in several sub-racks with a reasonable number of interconnections between different sub-racks, thus obtaining a truly modular TS switch structure. The modularity of the switch means that relatively small building blocks are handled in such a way that the technical complexity never reaches unreasonable levels. Figure 2 is a schematic diagram of an illustrative example of the overall architecture of a modular switch structure based on TS modules according to a first embodiment of the invention. The modular switch structure 20 comprises a matrix 21 of switch units TS which is also known as switch modules TS, XMBO-0 through SMB7-7, and several switch adapter boards 22 arranged in groups SABO-7, SAB8- 15, ..., SAB56-63. Each group of switch adapter boards is associated with a predetermined row of TS XMB modules in matrix 21 to input data to be stored in the voice stores of these TS XMB modules. Each switch adapter board group is also associated with a predetermined column of TS XMB modules in the array 21 to send data selected from the Ts XMB modules in the column. The SSAB switch adapter boards generally act as the input interface as well as the output interface of the switch structure 20. The association of each group of switch adapter boards with a respective predetermined column of TS modules is indicated in the figure 2, where each group of switch adapter boards is enclosed together with its corresponding column of TS XMB modules by means of solid lines. The bold lines in figure 2 are provided only to facilitate the reading of the drawing. The association of each group of switch adapter boards with a respective predetermined row of TS modules is quite straightforward and therefore is not indicated in Figure 2. Typically, switchboard boards SAB and TS modules XMB are They arrange in sub-frames in such a way that each sub-frame comprises: - a group of switch adapter boards; - a TS module constituting the initial switch together with the switch adapter boards in the sub-frame; - a selectable number of TS modules interconnected to the switch adapter boards in the sub-rack but capable of being interconnected with switch adapter boards in other sub-racks. These TS modules are used to extend the switch above the capacity of the initial switch. Figure 3 is a more detailed schematic diagram of an illustrative example of a switch structure according to the first embodiment of the invention with a 2x2 matrix of TS modules. The switch structure 30 comprises the four XMBO-0 to XMB1-1 TS modules arranged as a 2x2 matrix and 16 SABO switch adapter boards up to SAB15. For simplicity, only switch boards SABO, SAB1 and SAB15 are illustrated. The SABO switch adapter boards up to SAB15 are arranged in 2 groups with 8 boards in each group; SAB0-SAB7 in the first group, and SAB8-SAB15 in a second group. In this example, each TS XMB module is a 64K TS switch unit, preferably similar to the unit illustrated in Figure 1, with a voice warehouse array of 8x8, eight input terminals IN and 8 terminals Output OUT. The first group of SABO-7 adapter boards is associated with the first row of TS modules XMBO-0 and SMB0-1, and each SAP switch adapter board in this group is associated with a respective predetermined input terminal position of the TS modules XMBO-0 and SMB0-1 in this row for data transfer from the switch adapter board to the TS module SS voice stores associated with this input terminal position.

Correspondingly, the second group of SAP adapter boards 8-15 is associated with the second row of TS modules XMB1-0 and XBM1-1. Each switch adapter board SAB in the second SAB group 8-15 is associated with a respective predetermined input terminal position of the TS modules XMB1-0 and XMB1-1 in the second row to transfer data to the associated voice stores with this input terminal position. In this particular example, each switch adapter board SAB comprises an input interface for numerous incoming digital links on the front, a time multiplexing unit 32, a distribution point 33, a controllable selector 34, a control store 35, and a time demultiplexing unit 36. The time multiplexing unit 32 multiplexes data from the incoming links into a single data stream multiplexed in time, and the output terminal of the time multiplexing unit 32 is it is connected to the distribution point 33 which receives the multiplexed data stream from the time multiplexing unit 32. The distribution point 33 is connected to the input terminals IN of the TS switch module at a predetermined position of input terminal, and distributes the multiplexed data through a horizontal highway interface in such a way that all the SS voice stores, in each of the TS modules in the associated row, connected to an input terminal IN in this position receives the multiplexed data. With reference to figure 3, it can be seen that the distribution point 33 of the SABO switch adapter board is connected to the first input terminal of the TS module XMBO-0 as well as to the first input terminal of the module of TS XMBO-1. The distribution point of SAB1 is connected to the second input terminal of XMBO-0 and XMB0-1, while the distribution point of SAB15 is connected to the last input terminal of XMB1-0 and XMB1-1. Each group of switch adapter boards is also associated with a predetermined column of TS XMB modules in the array. The first group of SABO-7 adapter boards is associated with the first column of TS modules XMBO-0 and XMB1-0, and each SAB switch adapter board in this group is associated with a predetermined predetermined output position. of the TS XMBO-0 and XMB1-0 modules in this column to collect data from the OUT output terminals in this position. Correspondingly, the second group of adapter boards SAB 8-15 is associated with the second column of TS modules XMB0-1 and XMB1-1. The controlled selector 34 is connected to the output terminals of the switching module OUT at a predetermined output terminal position to receive data therefrom. The control store CS 35 is connected to the selector 34 and has control information that controls the selector 34. The controlled selector 34 selects data from one of the output terminals OUT at the predetermined output terminal position according to the selector produces data, in response to the control information contained in the control store CS 35. In this example, the selector 34 is preferably 2/1 MUX, and the output of the selector 34 is connected to a time demultiplexing unit. 36 that has an output interface for several outgoing digital links. Referring again to Figure 3, it can be seen that the controlled selector 34 of the SABO switch adapter board is connected to the first output terminal of the TS module XMBO-0 as well as to the first output terminal of the TS module. XMB1-0 The selector of SAB1 is connected to the second output terminal of XMBO-O and XMB1-0, while the selector of SAB 15 is connected to the last output terminal XMB0-1 and XMB1-1. The 8/1 MUX multiplexers in the TS modules act as a first part of the space switching functionality and the TS 30 switch structure, and the controllable selectors 34 on the switch adapter boards act as a second part of the space switching functionality. The division of functionality allows a modular switch structure. However, it should be emphasized that the functionality of the controllable selectors 34 is in fact the selection of a reduced set of data from a larger set of data obtained from the TS XMB modules. It will be noted that the input terminal of the distribution point 33 can operate with the input interface of the switch adapter board instead of the time multiplexing unit 32, and that the output terminal of the selector 34 can act as the interface of output from the switch adapter board instead of the time multiplexing unit 36. Obviously, it will be understood by those skilled in the art that the global switch not only includes the switch structure 30 but also includes auxiliary devices, such as for example, a control unit (not shown) and a clock and a synchronization signal generation system (not illustrated). Fig. 4 is a schematic diagram illustrating the design principle of the switch structures of different sizes based on TS XMB modules and SAB switch adapter boards. Consider, for example, that each TS XMB module is a 64 K TS switch unit. Then, in order to obtain a 128 K switch structure, you have to use 4 TS XMB switch modules that can be arranged as a 2x2 matrix, and two groups of switch adapters SAB07 and SAB8-15. For the 192K switch structure, 9 TS XMB switch modules that can be arranged as a 3x3 matrix and three groups of switch adapters SABO-7, SAB8-15, SAB16-23 should be used. The modular TS switch concept according to the invention allows even larger switches. By using additional switch modules (XMB), and SAP switch adapter boards, TF switch structures of up to 512K or more can be easily obtained. Table I below illustrates the relationship between the total switch size and the number of required TS XMB switch modules and required SAB switch adapter boards, considering that each TS switch module has a total capacity of 64 K with a 8x8 matrix of voice stores, and that each switch adapter board has a selector 8/1. Table I Switch Size (K) TS Module No. Switchboard No. Switch No. 8 1 1 16 1 64 1 128 4 16 192 9 24 256 16 32 320 25 40 384 36 48 448 49 56 512 64 64 The 16K switch comprises a single TS module that uses 16K of the total of 64K, and two associated switch adapter boards, while the 8K switch comprises a single TS module that employs 8K of the total of 64K, and one board of single switch adapter. The 8K switch and the 16K switch are indicated in Table I to provide an illustration of how the concept of the present invention is applied to very small switches. Obviously, it will be understood that it is possible to employ switch modules that are less than 8K or greater than 64K. As a first example, a TS switch module with a 2x2 matrix of voice stores, where each voice store can contain 512 multiple positions, will constitute a 1K switch unit. As a second example, a TS switch module with a 16x16 matrix of voice stores, where each voice store can contain 8192 multiple positions, will constitute a 128K switch unit. In the latter case, through the use of an 8x8 matrix of 128K TS switch modules and 8 switch adapter board groups designed to work with 128K TS switch modules, a switch structure with a capacity will be obtained 1024K global further, apart from the TS switch modules oriented towards the word, it is possible to use TS switch modules oriented towards bits. in one embodiment of the present invention, at least one of the TS switch modules comprises a bit-oriented time-space switch unit. It has been shown that the present invention offers a truly modular TS switch structure based on only two different types of units: the XMB time-space switch modules and SAB switch adapter boards. It is possible to start with a small TS switch structure with only a few units at a relatively low cost. Then, if a larger switch capacity is required, the TS switch structure can be easily extended by the addition of more units. In this way, the effective cost will correspond closely to the actual demand for capacity. In addition, a similar or identical programmatic as well as similar or identical maintenance routines can be employed for switches of all sizes since the primary building blocks, i.e. the TS modules and the switch adapter boards, are identical. Example of a 512K switch. Figure 5 is a schematic block diagram of an illustrative example of a 512K switch according to the first embodiment of the invention. The communication switch 50 comprises a switch structure 52 for actual switching functionality, a clock and a synchronization system 56 for providing clock signals and synchronization signals to the circuits in the switch structure 52, and a control unit 58 to control the switching operations of the switch structure 52. If the switch structure 52 is constructed based on 64K TS switch modules, it can be seen from table I above that 64 modules of TS for a switch structure of 512K. Accordingly, the 512K switch structure 52 basically comprises 64 TS switch modules 53 that can be arranged in an 8x8 matrix, and 64 switch adapter boards 54 that can be arranged in 8 groups, with 8 switch adapter boards in each group. The rows of the matrix 53 of the TS modules are designated RO to R7 and the columns as CO to C7. The TS modules themselves are indicated as XMBO-O through XMB7-7, and the eight groups of switch adapter boards are indicated as SABO-7 through SAB56-63, in the same manner as in Figure 2. First, each group of switch adapter boards is associated with the TS XMB switch modules of a predetermined row of the switch module matrix 53 to input data to the TS switch modules of this row, and are the switch modules TS of a predetermined column of the switch module matrix 53 to produce data from the TS switch modules of this column. Table II below illustrates this relationship. Table II Group of panels associated row of associated column of adapter - TS modules of TS switch modules SABO-7 RO [XMBO-O to XMBO-7] CO [XMBO-O to XMB7-0] SAB8-15 Rl [XMBl-0 to XMB1-7] Cl [XMB0-1 to XMB7-1] SAB16-23 R2 [XMB2-0 to XMB2-7] C2 [XMBO-2 to XMB7-2] SAB24-31 R3 [XMB3-0 to XMB3-7] C3 [XMBO-3 to XMB7-3] SAB32-39 R4 [XMB4-0 to XMB4-7] C4 [XMBO-4 to XMB7-4] SAB40-47 R5 [XMB5-0 to XMB5-7] C5 [XMB0-5 to XMB7-5] SAB48-55 R6 [XMB6-0 to XMB6-7] C6 [XMB0-6 to XMB7-6] SAB56-63 R7 [XMB7-0 to XMB7-7] C7 [XMB0-7 to XMB7-7] The switch adapter boards generally act as the input interface and output interface of the switch structure (52) as well as the global switch (50). In addition, each switch adapter board SAB has an input interface (not shown) for four digital links, where each digital link can carry 2048 time slots of a bit rate of 196 Mb / s. The digital links are multiplexed in a highway horizontal interface (not illustrated) capable of transporting 8192 time segments. Preferably, the highway horizontal interface has 8 highways and a total data rate of 786 Mb / s. The multiplexed data is sent on all allowed highway horizontals from a common distribution point (not shown) on the switch adapter board. The bit rates are indicated to provide the reader with an idea of the commutation complexity in this example, and should not be interpreted as precise frequencies. Consider, by way of example, that each TS module in matrix 53 is similar to the module illustrated in figure 1. Thus, each TS switching module has 64 voice stores that can be arranged according to a 8x8 voice store array, 8 input terminals INO to IN7, one for each row of voice stores, 8 output terminals OUT0 to OUT7, one for each column of voice stores, 8 multiplexers and 8 control stores. Since each highway interface can transport 8192 time segments, each voice store is designed to have 8192 multiple locations. This means that each TS switch module has a capacity of 8x8192 = 65536 multiple positions, i.e., a 64K switch unit. The working frequency is approximately 65 MHz. Each multiplexer in the TS module is associated with a respective column of the voice store array such that the voice stores in the column are connected to the inputs of the multiplexer. The output terminals of the multiplexers are respectively connected to the output terminals OUT0 to OUT7 of the TS switch module. A control store connected to all the voice stores in the column and to the multiplexer associated with the same voice store column is also associated to each column of the voice store array. Each control store has control information that controls: the reading of data from each of the voice stores in the voice store column; and from each voice store in the voice store column the data that must be retrieved by the multiplexer. Each switch adapter board in a given group of 2U switch adapter boards is associated with a respective predetermined input terminal position of the TF switch modules in the row of TF modules associated with this group of switch adapter boards. The data is distributed from the distribution point on the switch adapter board, in the Highway Horizontals, to the switch module input terminals at the given input terminal position. In each TS module, each voice store in a predetermined row of the voice store array is connected to the same input terminal to allow all voice stores in this row of voice stores to receive the same set of voice stores. data from a Highway Horizontal. It is important to understand that in a given TS module, different input terminals are connected to Highway Horizontals that come from different switch adapter board boards in the same group of switch adapter boards. Each switch adapter board in a given group of switch adapter boards is also associated with a respective predetermined output terminal position of the switch modules TS in the column of the TS modules which is associated with this group of boards switch adapter, and comprises a controllable selector (not shown) connected to the switch module output terminals in this output terminal position through an Expressway Vertical interface of 8 motorways. This Highway Vertical interface is capable of transporting 8192 time segments, and has a total data rate of 786 Mb / s. The controllable selector receives data from all output terminals at the output terminal position to select data from one of the output terminals as selector output data. The selector output data is demultiplexed in time and sent from the switch adapter board in four outgoing digital links, each digital link is capable of transporting 2048 time slots at a bit rate of 196 Mb / s. Table III below illustrates the relationship between the switch adapter boards on the one hand and the input terminal positions and output terminal positions on the other hand. Table III Terminal position terminal position adapter RL SABO INO output input switch [XMBO-O to XMB OUT0 of Cl [XMBO-O to 0-7] XMB7-0] SAB1 INI of Rl OUTl of Cl SAB2 IN2 of Rl OUT2 of Cl SAB3 IN3 of Rl 0UT3 of Cl SAB4 IN4 of Rl 0UT4 of Cl SAB5 IN5 of Rl 0UT5 of Cl SAB6 IN6 of Rl OUT6 of Cl SAB7 IN7 of Rl OUT7 of Cl SAB8 INO of R2 [XMBl-0 to XMB OUT of C2 [XMB0-1 to 1-7] XMB7-1] SAB9 INI of R2 OUT1 OF C2 SAB15 INI7 of R2 OUT7 of C2 SAB16 INO of R3 [XMB2-0 to XMB OUT of C3 [XMBO-2 to 2-7] XMB7-2] SAB63 IN7 of R7 [XMB7-0 to XMB OUT of C7 [XMBO-7 to 7-7] XMB7-7] As an example, Table III indicates that the SABO switch adapter board is associated with the input terminal position InoO of that of row Rl, and with the position of output terminal OUT0 of column Cl. A point-to-point connection between a given multiple input position (MUP) and a given multiple output position (MUP) in the switch is generally set under the control of a global control system (not shown) that provides connection adjustment instructions to the control unit 58. The control unit 58 then establishes the corresponding control stores in the switch structure 52 in accordance with the instructions from the global control system, thereby creating a circuit between the input MUP and the output MUP. The switch structure according to the present invention is operable for data circuit switching, and each group of switch adapter boards cooperates with a predetermined row of TS modules for inputting data to circuit, in the TS modules in this row , and with a predetermined column of TS modules to send a selected subset of the data available in the output terminals of the TS modules in this column. An expert in switching technology will have no problem understanding the relationships between the subsets of data handled by the switch as well as the general flow of data through the switch. It will be understood that the term "voice store" does not only refer to a store for voice data but should be interpreted as any memory for storing user information in general. The term "voice store" has been chosen because of its accepted and common use as a memory in relation to the technology of telecommunication and switching. Since it is possible to arrange a complete group of switch adapter boards in a single circuit board, the term switch adapter unit may be more suitable than the term switch board board. However, when each switch adapter unit is provided on a single circuit board, the term switch board board is obviously appropriate. In the case of smaller switch structures, it is convenient to provide each TS module in a separate single circuit board. In the case of larger switch structures, it may be more profitable to fix several TS modules on the same board. In the latter case, the TS modules are preferably arranged in the circuit boards in the form of a column such that all the TS modules belonging to the same column are provided on the same circuit board. Obviously, other ways of arranging the switch adapter units and the TS modules in the circuit boards can also be contemplated. Second embodiment Figure 6 is a schematic diagram of an illustrative example of the overall architecture of a modular control structure in accordance with a second embodiment of the invention. The overall architecture of the modular switch structure 60 illustrated in Figure 6 is similar to the architecture of the switch structure 20 of Figure 2. The switch structure 60 comprises a matrix 61 of switch modules TS, XMBO-1 a XMB7-6, and several switch adapter boards 62, also called switch adapter units, arranged in SABO-7 groups, SAB8-15, ..., SAB56-63. However, as can be seen in Figure 6, there is no diagonal TS module in the matrix 61, and therefore the matrix 61 is incomplete. The switching functionality corresponding to the diagonal TS modules illustrated in the switch structure 20 of Fig. 2 is now incorporated in the switch adapter boards SAB in the switch structure 60 of Fig. 6. The switch modules of TS XMB0-1 to XMB7-6 are preferably similar to the TS switch unit illustrated in Figure 1. In the same manner as in the first embodiment of the invention, each group of switch adapter boards is associated with a Default row of TS XMB modules in array 61 to enter data to be stored in the voice stores of these TS modules. Each group of switch adapter boards is also associated with a predetermined column of TS XMB modules in matrix 61 for sending selected data from the TS XMB modules in the column. The association of each group of switch adapter boards with a respective column of TS modules is indicated in Figure 6, where each group of switch adapter board is enclosed together with its corresponding column of TS XMB modules by means of of solid lines. The solid lines in figure 6 are provided only to facilitate the reading of the figure. The switching functionality that corresponds to a given diagonal TS module is now divided and incorporated into the group of switch adapter boards that is associated with the TS module column where the TS diagonal module was previously located. so that each switch adapter board in this group of switch adapter boards comprises a fractional TS module. Preferably, the voice store columns that preconstitute the diagonal TS module are now relocated to the switch adapter boards such that the fractional TS module in each switch adapter board in a group of adapter boards switch includes a respective column of voice stores. Obviously, each fractional TS module also includes a multiplexer and a control store that are associated with the voice store column. This will be described in more detail below or in relation to Figure 8. In this way, each switch adapter board includes its own time-space switching functionality. Thus, it is possible to start with a small TS switch structure comprising only a single switch adapter board. In the case of a small switch structure of this type, no TS module is required since the switch adapter board itself includes a TS switching functionality. The switch structure easily extends to a complete group of switch adapter boards, still without using any TS module. Thus, in the case of small switch structures, only one type of circuit board, the switch adapter board, is required. However, if two groups of switch adapter boards or more are required, then it is necessary to have non-diagonal TS modules. Table IV below illustrates the relationship between the total switch size and the number of required TS switch modules XMB and SAB switch adapter boards required, in accordance with the second embodiment of the invention. It is considered that each switch adapter board has an 8K switching capability, that a group of 8 switch adapter boards has a switching capacity of 64K, and that each TS module is a 64K TS switch unit. Table IV Switch size (K) No. of TS modules No. of switch adapter boards 0 1 16 0 2 64 0 8 128 2 16 192 6 24 256 12 32 320 20 40 384 30 48 448 42 56 512 56 64 By incorporating the switching functionality of the diagonal TS modules into the switchboard adapter boards, the number of TS modules needed in the switch structure according to the second embodiment of the invention will be reduced in comparison with the first mode. This is apparent from Table IV and Table I. In the case of larger switch structures, which require two groups of switch adapter boards or more, the switch adapter boards and their corresponding TS modules they are usually arranged in sub-frames. Each subframe typically includes: - a group of switch adapter boards that can perform commutation within the subframe; - A selectable number of TS modules that can be connected with switch adapter boards in other sub-racks. These TS modules are used when the switch is extended above the capacity of a group of switch adapter boards. Figure 7 is a schematic diagram of an example of a group of switch adapter boards according to the second embodiment of the invention. The group comprises 8 switchboard boards from SABO to SAB7. For simplicity, only the switch adapter boards SABO, SAB1 and SAB7 are illustrated. In this particular example, each switch adapter board SAB comprises an input interface for several incoming digital links in the front, a time multiplexing unit 72, a fractional time-space switch module FTSS, a controllable selector 74 , a control store 75 and a time demultiplexing unit 76. The time multiplexing unit 72 ultiplexes data from the incoming links into 7 horizontal freeway (HWH) and 8 horizontal freeway (LHWH). The fractional time-space switch module FTSS has 8 input terminals IN and one output terminal OUT, and includes a column of voice stores, SS, an associated multiplexer 8/1 MUX and a control store CS. The horizontal HWH motorway 7 are able to connect with non-diagonal XMB TS modules belonging to a predetermined row in the array 61 (FIG. 6). One of the 8 LHWH Local Highway Horizontals passes to the FTSS fractional TS switch module on the current switch adapter board, and the remaining 7 LHWHs are connected to the other switch adapter boards on the same group of switchboards. switch adapter and more particularly to the FTSS fractional TS switching modules there. Each switch adapter board SAB in a group of switch adapter boards is associated with a predetermined input terminal position of the non-diagonal XMB switch modules (Figure 6) in the row associated with this group of adapter boards of the switch, in the same manner as in the first embodiment of the invention (see table III above), with the input terminals of the fractional time-space switch modules FTSS of the switches adapter board SAB belonging to this group of switch adapter boards, in a predetermined input terminal position. With reference to Figure 7, it can be seen that the LHWHs of the SABO switch adapter board are connected to the first input terminal of the fractional TS switch module FTSSO in SABO, and to the first input terminal of FTSS1 in SAB1 and the first entry terminal of FTSS7 in SAB7. The LHWHs the switch adapter board SAB1 are connected to the second input terminal of the fractional TS switch module FTSS1 in SAB1, and to the second FTSSO input terminal in SABO and to the second input terminal of FTSS7 in SAB7. The LHWHs of switchboard adapter board SAB7 are connected to the last input terminal of FTSS7 in SAB7, and to the last input terminal of FTSSO in SABO and to the last input terminal of FTSS1 in SAB1. Each switch adapter board SAB in a switch adapter board group is also associated with a respective predetermined output terminal position of the non-diagonal TF switch modules XMB (Figure 6) in the matrix column associated with this group of switch adapter boards, in the same manner as in the first embodiment of the invention (see Table III above). The controllable sector 74 is connected through 7 HWV Highway Verticals to the TS switch module output terminals in this predetermined output terminal position and through a LHWV Local Highway Vertical to the output terminal OUT of Fractional time-space switch module FTSS on the current switch adapter board to receive data from there. The control store CS 75 is connected to the selector 74 and maintains control information that controls the selector 74. The controlled selector 74 selects data from one of the above-mentioned output terminals as selector output data., in response to the control information maintained in the control store CS 75. In this example, the selector 74 is a 8/1 MUX, and the output of the selector 74 is connected to a time demultiplexing unit 76 having a Exit interface for several outgoing digital links. Fig. 8 is a schematic diagram similar to the diagram of Fig. 1, illustrating a TS switch module divided into several fractional TS switch modules FTSSO to FTSS7. As mentioned above, in the second embodiment of the invention, the switching functionality corresponding to a given diagonal TS switch module is divided into fractional TS switch modules incorporated in the switch adapter boards of a given panel group. of switch adapter. Each fractional TS switch module that was previously located in a diagonal TS switch module is now relocated to a respective switch adapter board in the given set of switch adapters. By way of example, it can be seen from FIGS. 7 and 8 that the fractional TS switch module FTSSO is relocated to the switchboard adapted by the SABO switch, that FTSS1 is relocated to SAB1 and that FTSS7 is relocated to SAB7 . Thus, the fractional TS switch modules FTSS0-FTSS7 of the switch adapter boards SAB0-SAB7 in the group of switch adapter boards illustrated in figure 7 together correspond to a complete TS switch module XMB which can be operated to receive data from the SAB switch adapter boards in the group and also to provide data to the SAB switch adapter boards in the same group. Obviously, the relocation of the TS module switching functionality in switch adapter boards is carried out for all diagonal TS modules. However, it will be understood that the switch modules from which the switching functionality is relocated in switch adapter board groups do not necessarily have to be diagonal TS nodes. On the contrary, the requirement is that, for each group of switch adapter boards, the fractional time-space switching functionalities of the group of switchboard boards or boards constitute a time-space switching functionality that (a ) is operable to perform time-space data switching within the switch adapter board group and b) cooperates with the space switching functionality of the group of switch adapter boards such that the switch functionality of space selectively produces data commuted by the time-space switching functionality. Writing control information about the switching structure As mentioned above, a point-to-point connection is usually established under the control of a control system or a control unit that establishes the appropriate control stores in the switching structure with the object of creating a circuit between a predetermined input multiple position and a predetermined multiple output position. Since the space switching functionality of the switching structure of the present invention is generally divided between the TS modules and the switch adapter boards, there are control stores in the TS modules as well as in the adapter boards. switch. This means that for each connection, the control system must provide control information to the control store in a predetermined switch adapter board as well as a predetermined control store in the associated TS module. The normal procedure is to let the programmatic traffic control in the control system communicate with both control stores. In accordance with the present invention, the writing of the control information in the control stores is solved in a more efficient way. This solution will be described as reference to Figure 9. Figure 9 is a schematic diagram of an example of a switch structure with a 2x2 matrix of TS modules. The switch structure 80 illustrated in Figure 9 is similar to the switch structure 30 illustrated in Figure 3. However in Figure 9, an equipment is indicated to provide control information to the control stores in accordance with the invention. For reasons of simplicity, only the parts of the switch structure 80 that are relevant to the control information aspect of the present invention will be described below. According to the present invention, for each point-to-point connection, the programmatic traffic control in the control system (not illustrated) writes the control information that establishes a complete point-to-point connection, in a single write point as a record. From this point, the control information is provided to the relevant control stores through equipment links. Thus, the switch structure 80 further comprises several registers 81 and associated equipment links 82, 83, 84. Each register 81 is associated with a respective switch adapter board. For simplicity, only a single record 81 and a single set of equipment links 82, 83, 84 are indicated in Figure 9. Register 81 is operative to receive control information including a first control code Cl and a second control code C2. The first control code Cl refers to the control store 85 in the switch adapter board SABO, and the second control code C2 refers to the control store 86-87 in one of the associated TS modules XMBO-O and XMB1 -0. The equipment link 82 connects the register 81 to the control store 85 on the SABO switch adapter board. The equipment links 83 and 84 are selectively activated and connect the register 81 to the control stores 86 and 87 respectively. The first control code as provided for the control store 85 through the equipment link 82. This first control code Cl controls the multiplexer 2/1 MUX associated with the control store 85, and also controls which of the links of equipment 83 and 84 must be activated. Then, the second control code C2 is provided in the activated equipment link 83/84 to the corresponding control store 86/87. Preferably, each register 81 is arranged in its associated switch adapter board. In accordance with the present invention, there is generally no need to change the traffic control programmatic for the switch structure of the present invention as compared to the traffic control programmatic for a conventional non-modular TS switch core. This will be explained below with reference to an illustrative example. First, consider that each input line to the TS XMB modules handles 8192 time segments, and that each SS voice store and CS control store in the TS modules has 8192 positions, such that the global switch structure 80 has a capacity of 128K and can handle 131072 time segments numbered from 0 to 131071. As a first example, if the incoming time slot 65535 of the global switch 60 must be retrieved by SABO, the programmatic control system writes the number of time slice 65535 in the form of the binary code O ^ lll Llll ^ lll ^ llll, in the record 81 associated with SABO. In this example, the first control code Cl is the most significant bit, a "0", and the second control code C2 includes the remaining bits of the time segment number. The first control code Cl is provided to the control store 85 on the SABO switch adapter board via the equipment link 82, and controls the multiplexer 2/1 MUX associated with the control store 85. In this example, a "0" refers to the echo that the 2/1 MUX multiplexer is set to be in contact with the first output of the TS XMBO module The first control code Cl also activates one of the programmatic links 83 and 84. In this example, a "0" indicates that the equipment link 83 is activated, so that the second control code C2 is provided. to the control store 86 in the TS XMBO-O module and the incoming time segment of the TS module XMBO-O corresponding to the control code C2, ie, the time slice 65535, is retrieved from the first output of the TS module XMBO-0 As a second example, if the incoming time segment 131071 in the global counter 80 must be retrieved by SABO, the programmatic control system writes the time segment number 131071, in the form of the binary code 1_1111_1111_1111_1111, Jan 1 register 81 associated with SABO. The first control code Cl is the most significant bit "1" and the second control code C2 includes the remaining bits of the time segment number. Since Cl is equal to "1", the multiplexer 2/1 MUX associated with the control store 85 is set to be in contact with the first output of the other TS module XMB1-0. Now, 1 first control code Cl, "1", activates the equipment link 84, and the second control code C2 is provided to the control store 87 in the TS module XMB0-1. Accordingly, the incoming time segment of the TS module XMB1-0 corresponding to the binary control code C2, i.e., the time slice 65535 the XMB1-0, is retrieved from the first output of the TS module XMB1-0. Obviously, it is necessary to provide an address information that decides which outgoing time segment should be switched on inbound time segment recovered. The address information determines the storage locations in the control warehouses 85 and 86/87 where the control codes Cl and C2 are written, respectively. Preferably, a conventional write logic receives the control code and the address code in question and performs the actual writing of the control code in the corresponding control store in accordance with the associated address code. The traffic control programmatic only writes the control information associated with a point-to-point connection to a single point in the same way as in a conventional equivalent TS switch core. In this way, the traffic control programmatic does not need to worry about the configuration of the internal equipment of the switch structure and the programmatic traffic control already developed for conventional TS 'switch cores can be used. In a larger matrix of TS modules, the first control code will naturally include more than a single bit.

Switching sub-speed For example, in digital mobile telephony, the voice information is normally coded by a voice coder in such a way that a lower bit rate is obtained. The basic principle in voice solidification is to make the sound and signal finally decoded as best as possible at the lowest possible bit rate. For example, in a GSM system, a total speed transmission is usually carried out at a bit rate of 13.0 kbit / s, while a total speed transmission in a D-AMPS system is performed at a speed of 7.95 kbps per second. Thus, traffic between mobile phones and base station controllers is generally carried out at a relatively low bit rate such as 13.0 kbit / s. However, traffic between the base station controllers and the mobile switching centers frequently employ the normal public transmission network operating at a higher bit rate such as 64.0 kbit / s. If the base station controllers could switch 13.0 kbit / s of GSM traffic directly into a 64.0 kbit / s transmission network, a large part of the bandwidth capacity would be wasted. In this case, each channel would occupy only a quarter of the bit conditions of a time segment. However, by switching circuits of this traffic at bit level rather than word level, it is possible to fully mold the bandwidth capacity offered by the normal public transmission network. According to the prior art, this is usually solved by the use of an external bit oriented switch, also known as an underspeed switch, connected in series with an ordinary switch so that two different switches are used to establish the connections. The solution of the prior art has several obvious drawbacks. First, the input and output terminals of the ordinary switch that are connected to the sub-speed switch can not be used for normal traffic. Second, the traffic to be switched in the sub-speed switch has to be switched through the ordinary switch in the sub-speed switch and then back to the ordinary switch again, before being switched out of there. This naturally causes substantial traffic delays. However, by using the modular TS switch structure according to the second embodiment of the invention as a base, the sub-speed switching is efficiently integrated into the main switch structure. This will be explained below with reference to Figure 10. Figure 10 is a schematic diagram similar to the diagram of Figure 7, illustrating an example of a group of switch adapter boards according to the invention. The main difference between the diagram of figure 7 and the diagram of figure 10 is that instead of the fractional TS module, a complete TS module is provided on each switch adapter board to allow bit-level switching. The TS modules incorporated in the SABO to SAB7 switch adapter boards are modified to operate as SRSO to SRS7 bit-oriented underspeed switch modules. Switching at the bit level instead of at the word level also requires an additional multiplexer 8/1 MUXs connected in series with each of the 8/1 MUXs that are necessary for a word-oriented switching. This evidently means that each control store CS in the sub-speed switch module SRS is associated with two multiplexers 8/1 MUX instead of only 1, and that the control store CS includes additional control information to control the additional multiplexer. . Each additional multiplexer 8/1 MUX sends a selected single bit, and the output bits of all additional multiplexers in a sub-speed switch module SRS are combined in a data word by a bit converter in words B / W. In general, a bit-oriented time-space switch unit performs a controlled field of bit position and time slot word of selected bits in the received timeslot words. In the SRSO underspeed switch module on the SABO switch adapter board, word-oriented switching and bit-oriented switching are truly integrated. The switch module SRSO includes an additional multiplexer MUX connected to the output terminal of the bit converter in words B / W and a second output terminal of the first 8/1 MUX in the first voice store column, to receive words from switch data normally from the first 8/1 MUX and data words switched to sub-speed from the bit converter in B / W words. The control store CS associated with the first voice store column is also connected to the MUX, and further includes a control information which controls the selection of data from the MUX is controlled to select data from the second terminal output of the first 8/1 MUX in the first voice store column, a word-oriented switching is performed, while if the MUX is controlled to select data from the bit converter in words B / W, then it is carried out a bit-oriented switching.

However, since word switching can be performed at the word level as well as at the bit level, it is also possible to carry out the switching only by using the output of the bit converter in words B / W, as illustrated in the sub-speed switch modules SRS1 and SRS7 on switch adapter boards SAB1 and SAB7. Either way, the output terminal of the SRS sub-speed switch module is connected in the Local Freeway Vertical to the switch adapter board selector in the same manner as described in relation to Figure 7. In all others aspects, the overall switch structure is similar to the structure described in relation to figure 6 and figure 7. In this way, global sub-rate switching is provided efficiently within a given group of switch adapter boards , while normal switching is provided between different groups of switch adapter boards. It will be understood that the SABO switch adapter board of Figure 10 itself constitutes a TS switch where word-oriented switching and bit-oriented switching are integrated, while each of the switch adapter boards SAB1 a SAB7 constitutes a TS switch oriented towards bits. It is possible to combine several switch adapter boards of the same type as SABO in order to form a group of switch adapter boards, in the same way as illustrated in Figure 10, within which an under-speed switching is obtained. total integrated. It is also possible to combine several switch adapter boards of the same type as SAB1 to form a group of switch adapter boards. Another solution according to the present invention is the connection of a sub-speed switch "in parallel" with a TS switch. In this way, all the switch terminals of the TS switch unit can be used for normal traffic, and the delay of the sub-speed switched traffic is reduced compared to the delay according to the solution of the prior art which employs an ordinary switch connected in series with a sub-speed switch. This solution will be described below with reference to Figure 11. Figure 11 is a schematic diagram illustrating a switch structure with a sub-speed switch connected in parallel with a switch module TS. The switch structure includes a TS XMB module, an associated group of SABO switch adapter boards to SAB7, and an SRS sub-speed switch module connected in parallel with the TS XMB module. The TS XMB module cooperates with the switch adapter boards SABO to SAB7 in substantially the same manner as described above in connection with Figure 3. However, since there is only one single TS module, the switch adapter boards are transparent in terms of switching functionality and therefore are not taken into account at this point. The SRS sub-speed switch module is similar to the TS module in terms of overall equipment configuration. The sub-speed switch SRS comprises a matrix of SS voice stores and associated multiplexers and control stores. However, the SS voice stores in the SRS sub-speed switch are prepared to store bits instead of storing entire words in the storage positions. The SRS sub-speed switch is additionally equipped with an input terminal IN and an output terminal OUT. The time segments provided to a predetermined input terminal of the TS XMB module are also distributed to the IN input terminal of the SRS sub-speed switch such that the SRS sub-speed switch continuously receives time slots. On the SRS sub-speed switch, the data words in the received time segments are disassembled at the bit level in such a way that each data word is divided into several bits BITO to BIT7. Each bit is then distributed to a respective row of voice stores in the SRS sub-speed switch, and stored in all the SS voice stores in this row. The multiplexers 8/1 MUXs controller by the associated control stores CS are operative to produce bits selected from the voice stores. The selected output bits of multiplexers 8/1 MUX in the sub-speed switch SRS are combined in a bit converter into words in an entire word which is sent to the TS module XMB. The TS XMB module further comprises an additional input terminal for receiving data from the SRS sub-speed switch. The additional input terminal is connected to an additional 2/1 MUX that also receives data from a predetermined 8/1 MUX in the TS XMB module. The CS control store associated with this default 8/1 MUX is also connected to the additional 2/1 MUX, and contains additional control information to control the 2/1 MUX. If the 2/1 MUX is set to receive the output of the SRS sub-speed switch, the TS module supports a sub-speed switch, whereas if the 2/1 MUX is set to receive data from the associated 8/1 MUX in the TS module then the TS module supports a normal switching towards words. In this way, sub-speed switching as well as normal switching are supported. Considering that each TS module has a capacity of 64K, the SRS sub-speed switch has a capacity of 8K. A larger modular TS switch structure supporting a word-oriented normal switching, as well as a sub-speed switching is obtained based on the switching structure in accordance with the first embodiment of the invention by connecting a sub-speed switch in parallel with each of the TS modules in a modular switch structure. This is illustrated schematically in Figure 12. Figure 12 is a schematic diagram illustrating the principle of designing switch structures of different sizes that support both normal switching and sub-speed switching. The diagram in Figure 12 is similar to the diagram in Figure 4. However, the different switch structures in Figure 12 are based on SAB switch adapter boards, and aggregates of TS XMB modules and sub-speed switch modules MR. These switching structures will have a total sub-rate switching, supported by the associated SRS sub-speed switch modules, for a switch adapter board in each group of switch adapter boards. The switch structures according to FIG. 12 are further modified compared to the switch structure described with reference to FIGS. 2 to 4, leaving each sub-speed switch module SRS to set the output bits that are not associated with connections. currently set to "zero" and providing each SAB switch adapter board operative to selectively receive data words that come from SRS sub-speed switch modules, with a 0 circuit that receives data from the TS XMB modules in the column of TS module associated. Fig. 13 is a schematic diagram of pertinent parts of a switch adapter board SAB associated with a full sub-speed switching capability. The switcher adapter board switch 8/1 MUX receives data from the TS modules in the associated column and the same data is distributed to a circuit 0, which carries out an operation 0, towards bits in the received data. The output terminal of the OR circuit on the SAB switch adapter board is connected to an additional controllable 2/1 MUX that also receives the output of the 8/1 MUX selector. For sub-speed switching, when the output data of the SRS sub-speed switching modules are sent to the switch adapter boards via 2/1 MUX in the TS modules, the results of the O operation are sent to the time demultiplexer by the 2 / 1 MUX on the SAB switch adapter board. Since the output bits that are not associated with established connections are set to "0", the relevant output bits will pass through the gate O. In this way, a sub-rate switching for modular switch structures is implemented successfully. Additional information on switching, switch control procedures and signaling on switches can be found, for example, in the AX documentation of Telefonaktiebolaget L M Ericsson. The embodiments described above are merely examples, and it should be understood that the present invention is not limited to these embodiments. Obviously it is possible to incorporate the present invention into specific forms other than those described without departing from the spirit of the invention. Additional modifications and improvements that preserve the underlying and claimed basic principles are within the scope and spirit of the invention.

Claims (22)

1. CLAIMS A switch structure for circuital data switching, characterized in that said switch structure (20; 30; 52; 60; 80) comprises several time-space switch modules (XMB) that can be arranged in the form of a matrix ( 21; 53; 61) with columns and rows of said time-space switch modules; and several switch adapter units (SAB) that can be arranged in groups, each of these groups of switch adapter units (SAB) is associated with the time-space switch modules (XMB) of a predetermined row of said switch module matrix (21; 53; 61) to input data to the time-space switch (XMB) modules of said row, and with the time-space switch modules (XMB) of a predetermined column of said switch module matrix (21; 53; 61) to send data from the switch modules (XMB) of said column, and each of said groups of said switch adapter units (XMB); switch (SAB) having a space switching functionality that is operative in the process of sending data from the associated time-space switch modules (XMB). A switch structure for the circuital data switching, according to claim 1, wherein each of the time-space switch modules (XMB) includes: several input terminals (IN) for receiving data; several voice stores (SS) for storing data, said voice stores (SS) can be arranged in a matrix of voice stores having columns and rows, each voice store (SS) in a predetermined row of said store array of voice is connected to the same input terminal (IN) to allow all voice stores (SS) in said row of voice stores to receive the same data set; several multiplexers (MUX) each of which is associated with the voice stores (SS) of a respective column of said voice store array; several control stores (CS), each of said control stores (CS) is associated with a respective column of said voice store array and with the multiplexer (MUX) associated with the same column of voice stores, and retaining control information that controls: -the reading of data from one of the voice stores (SS) in the column of voice stores; and - from which voice store (SS) in said column of voice stores these data should be recovered as a column output by said multiplexer (MUX); and several output terminals (OUT) respectively connected to said multiplexers (MUX) to receive said column outputs. A switch structure for the circuital data switching according to claim 2, characterized in that each switch adapter unit (SAB) in a predetermined group of switch adapter units is associated with a predetermined output terminal position of the time-space switch modules (XMB) in the switch module column associated with said group of switch adapter units and includes a controllable selector (34; 74) connected to the switch module output terminals (OUT) at said output terminal position to receive column outputs from all the switch module output terminals (OUT) at said position to select one of them as selector output data. A switch structure for the circuital data switching according to claim 3, characterized in that each switch adapter unit (SAB) includes a control store (35; 75) for storing a selector control information, said store of control (35; 75) is connected to said controllable selector (34; 74) in such a way that said selector (34; 74) is controllable by said selector control information. A switch structure for circuit data switching, according to claim 3, characterized in that each switch adapter unit (SAB) further includes a time demultiplexing unit (36).; 76) that responds to said selector output data from said controllable selector (34; 74) and that has an output interface for at least one outgoing digital link. A switch structure for the data circuit switching according to claim 2, characterized in that each switch adapter unit (SAB) in a predetermined group of switch adapter units is associated with a predetermined input terminal position of the switches. time-space switch modules (XMB) in the row of switch module associated with said group of switch adapter units, and includes devices (33) for distributing data to the switch module input (IN) terminals in said input terminal position. A switch structure for the data circuit switching according to claim 6, characterized in that each switch adapter unit (SAB) further includes: an input interface for at least one incoming digital link; and a time multiplexing unit (32; 72) for multiplexing data from said at least one incoming digital link in time multiplexed data, said time multiplexing unit (32; 72) being connected to said distribution device (33), to send said data multiplexed in time there. A switch structure for the circuital data switching according to claim 1, characterized in that said time-space switch modules (XMB) operate independently of each other. A switch structure for the data circuit switching according to claim 1, wherein each of said switch adapter units (SAB) includes a space switching functionality unit (34, 35; 74, 75) for selecting a reduced set of data from the data obtained from the associated time-space switch modules (XMB). A switch structure for the data circuit switching according to claim 1, characterized in that at least one of said time-space switch modules (XMB) comprises a word-oriented time-space switch unit. A switch structure for the data circuit switching according to claim 1, characterized in that at least one of said time-space switch modules (XMB) comprises a time-space-oriented bit-time switch unit. A switch structure for the circuital data switching according to claim 1, wherein each of said switch adapter units (SAB) is provided on a separate circuit board. A switch structure for the circuital data switching according to claim 1, wherein each group of switch adapter units is on a separate circuit board. A switch structure for the circuital data switching according to claim 1, wherein each time-space switch module (XMB) is provided on a separate circuit board. A switch structure for the circuital data switching according to claim 1, wherein each group of switch adapter units (SAB) and its associated column of time-space switch modules (XMB) is provided in a sub-unit. Separate frame. A switch structure for the circuital data switching, characterized in that said switch structure (20; 30; 52) comprises: several time-space switch modules (XMB) that can be arranged in the form of a matrix (21; 53) with columns and rows of said time-space switch modules (XMB), each of said time-space switch modules (XMB) has input terminals (IN) to receive data, media (SS, MUX, CS) for data time-space switching and output terminals (OUT) to send data; and several switch adapter units (SAB) that can be arranged in groups, each of said groups of switch adapter units is associated with the time-space switch modules (XMB) of a predetermined row of said matrix (21).; 53) to input data to the time-space switch modules (XMB) of said row, and with the time-space switch modules (XMB) of a predetermined column of said matrix (21; 53) to send data from the switch modules (XMB) of said column; each switch adapter unit (SAB) of a group of switch adapter units is associated with a predetermined input terminal position of the time-space switch modules (XMB) in the row associated with said group of units. switch adapter and with a predetermined output terminal position of the time-space switch modules (XMB) in the column associated with said group of switch adapter units, and including a device (33) for distributing data to the switch module input terminals (IN) at said input terminal position, and a controllable selector (34) connected to the switch module output terminals (OUT) at said output terminal position to receive data from all the output terminals (OUT) in said position to select data from one of said output terminals (OUT) as selector output data, the input terminal of said output Distribution device (33) acts as the input interface of the switch adapter unit, and the output terminal of said selector (34) acts as the output interface of the switch adapter unit. A switch structure for the circuital data switching, characterized in that said switch structure (60) comprises: several time-space switch modules (XMB) that can be arranged in the form of a matrix (61), said matrix (61) has columns and rows of said time-space switch modules (XMB); and several switch adapter units (SAB) that can be arranged in groups, each of said groups of switch adapter units is associated with the time-space switch modules (XMB) of a predetermined row of said matrix (61). ) to input data to the time-space switch (XMB) modules of that row, and with the time-space switch modules (XMB) of a predetermined column of said array (61) to send data from the switch modules (XMB) of said column, each of said groups of switch adapter units (SAB) has a switching functionality of space that is operative in the process of sending data from the associated time-space switch modules (XMB); each time-space switch module (XMB) in said array (61) is operable to receive data from a predetermined group of switch adapter units and to provide data to another predetermined group of switch adapter units; each switch adapter unit (SAB) further includes a fractional time-space switching functionality, and, for each group of switch adapter units, the fractional time-space switching functionalities of the group of switch adapter units together they constitute a time-space switching functionality that is operable to carry out the time-space data switching within the group of switch adapter units (SAB), and cooperates with the space switching functionality of the group of switching adapter units such that said space switching functionality selectively produces data switched by said time-space switching functionality. 18. A switch structure for circuit data switching according to claim 17, characterized in that the fractional time-space switching functionality of at least one of said switch adapter boards is bit oriented. 19. A switch structure for circuit data switching according to claim 18, characterized in that said fractional time-space switching functionality is in the form of a bit-oriented time-space switch unit which, in operation , performs a controlled change of bit position and time segment word of selected bits in time segment words received as data by said bit-oriented time-space switch unit. 20. A switch structure for circuit data switching according to claim 17, characterized in that the fractional time-space switching functionality of at least one of said switch adapter boards is operable to alternately perform a switch. oriented towards words and a bit-oriented switching. 21. A switch structure for the circuital data switching according to claim 17, characterized in that the time-space switching functionality of at least one of said groups of switch adapter boards is oriented to bits. 22. A switch structure for the circuital data switching according to claim 17, characterized in that each of said time-space switch modules (XMB) in said matrix (61) has input terminals (IN) to receive data, first means for time-space data switching (SS, MUX, CS), and output terminals (OUT) for sending data, and because said fractional time-space switching functionality is in the form of a unit of data. fractional time-space switch (FTSS) having input terminals (FTSS-IN), a second device for time-space data switching (FTSS-SS, -MUX, -CS) and at least one output terminal (FTSS-OUT), each switch adapter unit (SAB) of a group of switch adapter units is associated with a predetermined input terminal position of the time-space switch (XMB) modules in an associated row with said group d e switch adapter units and with the input terminals (FTSS-IN) of the fractional time-space switch units (FTSS) of the switch adapter units (SAB) belonging to said group of adapter boards. switch in said input terminal position, and also with a predetermined output terminal position of the time-space switch modules (XMB) in the column associated with said group of switch adapter units, and including devices for distributing data to the input terminals ( IN) of switch module in said input terminal position and to the fractional switch unit input terminals (FTSS-IN) in said input terminal position, and a controllable selector (74) connected to the output terminals switch module (OUT) in said output terminal position and the output terminal (FTSS-OUT) of the fractional time-space switch unit (FTSS) in said switch adapter unit (SAB) to receive data from said output terminals (OUT, FTSS-OUT) to select one of them as selector output data. A communication switch for the circuital data switching, characterized in that said switch (50) comprises: a switch structure (52) that includes: several time-space switch modules (XMB) that can be arranged in the form of a matrix ( 53) with columns and rows of said time-space switch modules (XMB); and several switch adapter units (SAB, 54) that can be arranged in groups, each of said groups of switch adapter units (SAB) is associated with the time-space switch (XMB) modules of a predetermined row of said switch module matrix (53) to input data to the time-space switch (XMB) modules of each row, and with the time-space switch (XMB) modules of a predetermined column of said time-space switch module (XMB). switch module (53) to produce data from the switch modules (XMB) of said column, each of said groups of said switch adapter units (SAB) has a space switching functionality that is operative in the process of sending data from the associated time-space switch modules (XMB), said switch adapter units (SAB) are operative to act as an input interface and as an output interface of said switch tador (50); a generation system (56) of clock signal and synchronization signal to provide clock signals and synchronization signals to the switching structure (52); and a control unit (58) for controlling the switching operations of the switch structure (52).