MX352450B - Manejo dinámico de memoria heterogénea. - Google Patents
Manejo dinámico de memoria heterogénea.Info
- Publication number
- MX352450B MX352450B MX2015010046A MX2015010046A MX352450B MX 352450 B MX352450 B MX 352450B MX 2015010046 A MX2015010046 A MX 2015010046A MX 2015010046 A MX2015010046 A MX 2015010046A MX 352450 B MX352450 B MX 352450B
- Authority
- MX
- Mexico
- Prior art keywords
- memory
- computing device
- soc
- type
- dram
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/501—Performance criteria
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Human Computer Interaction (AREA)
- Power Sources (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Memory System (AREA)
- Dram (AREA)
- Debugging And Monitoring (AREA)
Abstract
Un método para operar un dispositivo de cómputo incluye manejar, en forma dinámica, por lo menos dos tipos de memoria con base en cargas de trabajo o solicitudes de diferentes tipos de aplicaciones. Un primer tipo de memoria puede ser una memoria de alto desempeño que puede tener un ancho de banda más alto, una menor latencia de memoria y/o un menor consumo de energía. En una modalidad, el dispositivo de cómputo incluye un sistema en un chip (SoC) que incluye una DRAM I/O Amplia colocada con uno o más núcleos del procesador. Una memoria de acceso aleatorio dinámico de Tasa de Dobles Datos de Baja Energía 3 (LRDDR3 DRAM) está conectada externamente con el SoC o es una parte incorporada del SoC. en otras modalidades, el dispositivo de cómputo puede estar incluido en por lo menos un teléfono celular, un dispositivo móvil, un sistema incrustado, un juego de video, una consola de medios, una computadora laptop, una computadora desktop, un servidor o en un centro de datos.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/758,613 US9110592B2 (en) | 2013-02-04 | 2013-02-04 | Dynamic allocation of heterogenous memory in a computing system |
PCT/US2014/013468 WO2014120698A1 (en) | 2013-02-04 | 2014-01-29 | Dynamic management of heterogeneous memory |
Publications (2)
Publication Number | Publication Date |
---|---|
MX2015010046A MX2015010046A (es) | 2016-03-04 |
MX352450B true MX352450B (es) | 2017-11-24 |
Family
ID=50156901
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX2015010046A MX352450B (es) | 2013-02-04 | 2014-01-29 | Manejo dinámico de memoria heterogénea. |
Country Status (11)
Country | Link |
---|---|
US (1) | US9110592B2 (es) |
EP (1) | EP2951689A1 (es) |
JP (1) | JP2016510471A (es) |
KR (1) | KR102207598B1 (es) |
CN (1) | CN105144106B (es) |
AU (1) | AU2014212559A1 (es) |
BR (1) | BR112015018321A2 (es) |
CA (1) | CA2898127A1 (es) |
MX (1) | MX352450B (es) |
RU (1) | RU2015132229A (es) |
WO (1) | WO2014120698A1 (es) |
Families Citing this family (52)
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JP6448254B2 (ja) * | 2014-08-19 | 2019-01-09 | ラピスセミコンダクタ株式会社 | メモリ制御装置及びメモリ制御方法 |
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US9606851B2 (en) | 2015-02-02 | 2017-03-28 | International Business Machines Corporation | Error monitoring of a memory device containing embedded error correction |
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JP6519228B2 (ja) * | 2015-02-27 | 2019-05-29 | 富士通株式会社 | データ配置決定装置、データ配置決定プログラム及びデータ配置決定方法 |
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KR102631351B1 (ko) * | 2016-10-07 | 2024-01-31 | 삼성전자주식회사 | 피어-투 피어 통신을 수행할 수 있는 저장 장치와 이를 포함하는 데이터 저장 시스템 |
US10482007B2 (en) * | 2016-12-06 | 2019-11-19 | Noblis, Inc. | Memory allocation on non-volatile storage |
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US10180793B2 (en) | 2017-01-31 | 2019-01-15 | Hewlett Packard Enterprise Development Lp | Performance attributes for memory |
US10368128B2 (en) * | 2017-08-11 | 2019-07-30 | Microsoft Technology Licensing, Llc | Memory allocation type for media buffer |
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KR102394695B1 (ko) * | 2017-11-08 | 2022-05-10 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 그것의 동작방법 |
US11636014B2 (en) | 2017-10-31 | 2023-04-25 | SK Hynix Inc. | Memory system and data processing system including the same |
KR20200088634A (ko) | 2019-01-15 | 2020-07-23 | 에스케이하이닉스 주식회사 | 메모리 시스템, 데이터 처리 시스템 및 데이터 처리 시스템의 동작방법 |
KR102482896B1 (ko) | 2017-12-28 | 2022-12-30 | 삼성전자주식회사 | 이종 휘발성 메모리 칩들을 포함하는 메모리 장치 및 이를 포함하는 전자 장치 |
US11010330B2 (en) | 2018-03-07 | 2021-05-18 | Microsoft Technology Licensing, Llc | Integrated circuit operation adjustment using redundant elements |
US11307796B2 (en) * | 2018-09-27 | 2022-04-19 | International Business Machines Corporation | Mapping memory allocation requests using various memory attributes |
US10831659B2 (en) | 2018-09-28 | 2020-11-10 | International Business Machines Corporation | Scope resolution tag buffer to reduce cache miss latency |
KR102149153B1 (ko) * | 2018-10-08 | 2020-08-28 | 울산과학기술원 | 이종 메모리를 활용한 범용 gpu에서의 페이징 방법 및 장치 |
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US10983832B2 (en) | 2019-02-14 | 2021-04-20 | International Business Machines Corporation | Managing heterogeneous memory resource within a computing system |
KR102666123B1 (ko) | 2019-07-05 | 2024-05-16 | 에스케이하이닉스 주식회사 | 메모리 시스템, 메모리 컨트롤러 및 메모리 시스템의 동작 방법 |
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KR20200139433A (ko) | 2019-06-04 | 2020-12-14 | 에스케이하이닉스 주식회사 | 컨트롤러의 동작 방법 및 메모리 시스템 |
KR20200137181A (ko) | 2019-05-29 | 2020-12-09 | 에스케이하이닉스 주식회사 | 메모리 시스템에서 맵정보를 전송하는 장치 |
KR20210004322A (ko) | 2019-07-04 | 2021-01-13 | 에스케이하이닉스 주식회사 | 메모리 시스템에서 맵정보 및 리드카운트를 전송하는 장치 및 방법 |
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-
2013
- 2013-02-04 US US13/758,613 patent/US9110592B2/en not_active Expired - Fee Related
-
2014
- 2014-01-29 RU RU2015132229A patent/RU2015132229A/ru not_active Application Discontinuation
- 2014-01-29 CA CA2898127A patent/CA2898127A1/en not_active Abandoned
- 2014-01-29 JP JP2015556089A patent/JP2016510471A/ja active Pending
- 2014-01-29 MX MX2015010046A patent/MX352450B/es active IP Right Grant
- 2014-01-29 AU AU2014212559A patent/AU2014212559A1/en not_active Abandoned
- 2014-01-29 WO PCT/US2014/013468 patent/WO2014120698A1/en active Application Filing
- 2014-01-29 CN CN201480006767.3A patent/CN105144106B/zh not_active Expired - Fee Related
- 2014-01-29 KR KR1020157020998A patent/KR102207598B1/ko active IP Right Grant
- 2014-01-29 EP EP14706160.0A patent/EP2951689A1/en not_active Ceased
- 2014-01-29 BR BR112015018321A patent/BR112015018321A2/pt not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US20140223098A1 (en) | 2014-08-07 |
MX2015010046A (es) | 2016-03-04 |
CN105144106B (zh) | 2020-05-05 |
RU2015132229A (ru) | 2017-02-08 |
WO2014120698A1 (en) | 2014-08-07 |
BR112015018321A2 (pt) | 2017-07-18 |
CN105144106A (zh) | 2015-12-09 |
KR102207598B1 (ko) | 2021-01-25 |
US9110592B2 (en) | 2015-08-18 |
KR20150114958A (ko) | 2015-10-13 |
JP2016510471A (ja) | 2016-04-07 |
EP2951689A1 (en) | 2015-12-09 |
AU2014212559A1 (en) | 2015-07-30 |
CA2898127A1 (en) | 2014-08-07 |
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