KR930005196A - 반도체 기억장치 - Google Patents
반도체 기억장치 Download PDFInfo
- Publication number
- KR930005196A KR930005196A KR1019920014874A KR920014874A KR930005196A KR 930005196 A KR930005196 A KR 930005196A KR 1019920014874 A KR1019920014874 A KR 1019920014874A KR 920014874 A KR920014874 A KR 920014874A KR 930005196 A KR930005196 A KR 930005196A
- Authority
- KR
- South Korea
- Prior art keywords
- terminal
- bit line
- scr
- semiconductor memory
- emitter
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/415—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
- G11C11/4116—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/10—SRAM devices comprising bipolar components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 일실시예를 도시한 반도체 기억장치의 회로도,
제2도는 실시예의 반도체 기억장치를 사용하여 선택회로를 구성한 예의 회로도.
Claims (1)
1쌍의 pnp형 트랜지스터 및 1쌍의 더블에미터형 트랜지스터에 의해 구성되어 있는 SCR형 메모리셀과, 상기 SCR형 메모리셀에 정보를 기입하기 위한 전용 트랜지스터로서 배설되고, 콜렉터가 상기 SCR형 메모리셀의 전압유지노드에 접속되는 동시에, 베이스가 워드선택선에 접속되는 npn트랜지스터와, 상기 SCR형 메모리셀을 구성하는 더블에미터형 트랜지스터의 에미터가 접속되는 제1의 단자와, 상기 기입 전용으로 배설된 npn 트랜지스터의 에미터가 접속되는 제2의 단자를 구비하고, 상기 제1의 단자에 독출용 비트라인을 접속하는 동시에, 상기 제2의 단자에는 상기 독출용 비트라인과는 별도로 배설되는 기입용 비트라인을 접속하여 하나의 정보기억단위를 구성할 수 있도록 한 것을 특징으로 하는 반도체 기억장치.
※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3233846A JPH0548029A (ja) | 1991-08-21 | 1991-08-21 | 半導体記憶装置 |
JP91-233846 | 1991-08-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR930005196A true KR930005196A (ko) | 1993-03-23 |
Family
ID=16961488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920014874A KR930005196A (ko) | 1991-08-21 | 1992-08-19 | 반도체 기억장치 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5287303A (ko) |
EP (1) | EP0530623B1 (ko) |
JP (1) | JPH0548029A (ko) |
KR (1) | KR930005196A (ko) |
DE (1) | DE69222722T2 (ko) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1489577A (en) * | 1973-10-02 | 1977-10-19 | Plessey Co Ltd | Solid state circuits |
US4409673A (en) * | 1980-12-31 | 1983-10-11 | Ibm Corporation | Single isolation cell for DC stable memory |
US4635087A (en) * | 1984-12-28 | 1987-01-06 | Motorola, Inc. | Monolithic bipolar SCR memory cell |
JPH0482085A (ja) * | 1990-07-25 | 1992-03-16 | Toshiba Corp | スタティック型メモリセル |
-
1991
- 1991-08-21 JP JP3233846A patent/JPH0548029A/ja active Pending
-
1992
- 1992-08-18 US US07/931,799 patent/US5287303A/en not_active Expired - Fee Related
- 1992-08-19 KR KR1019920014874A patent/KR930005196A/ko not_active Application Discontinuation
- 1992-08-21 DE DE69222722T patent/DE69222722T2/de not_active Expired - Fee Related
- 1992-08-21 EP EP92114347A patent/EP0530623B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69222722T2 (de) | 1998-05-07 |
JPH0548029A (ja) | 1993-02-26 |
EP0530623B1 (en) | 1997-10-15 |
EP0530623A3 (en) | 1995-05-03 |
EP0530623A2 (en) | 1993-03-10 |
DE69222722D1 (de) | 1997-11-20 |
US5287303A (en) | 1994-02-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |