KR930005191A - 상보형 금속 산화물 반도체(cmos)집적 회로용 정전방전보호 - Google Patents
상보형 금속 산화물 반도체(cmos)집적 회로용 정전방전보호 Download PDFInfo
- Publication number
- KR930005191A KR930005191A KR1019920014950A KR920014950A KR930005191A KR 930005191 A KR930005191 A KR 930005191A KR 1019920014950 A KR1019920014950 A KR 1019920014950A KR 920014950 A KR920014950 A KR 920014950A KR 930005191 A KR930005191 A KR 930005191A
- Authority
- KR
- South Korea
- Prior art keywords
- electrostatic discharge
- conductive ring
- pad
- cmos
- metal oxide
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims 4
- 230000000295 complement effect Effects 0.000 title 1
- 229910044991 metal oxide Inorganic materials 0.000 title 1
- 150000004706 metal oxides Chemical class 0.000 title 1
- 239000003990 capacitor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000003068 static effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 제1실시예에 대한 회로도,
제4도는 제3도에 예시된 회로를 통한 ESD전류 경로도,
제5도는 반전 턴온 전압레벨을 낮춘 개선된 수동 클램프 회로의 한 실시예를 예시한 도면.
Claims (1)
- CMOS 반도체 디바이스에 있어서, 정전 방전으로부터 상기 디바이스의 손상을 방지하며, 제1도전성 반도체 기판, 상기 반도체 기판의 상부 표면상에 배치되어 있으며 캐패시터에 의해 전기적으로 연결되는 제1 및 제2의 공간 도전링, 신호 패드, 상기 제1도전링으로 부터 정전 방전 전류를 상기 패드로 흐르게 하며, 삭 패드에 접속된 에미터, 상기 제1도전링에 접속된 콜렉터 및 상기 제2도전링에 접속된 베이스를 갖는 3단자 NPN 트랜지스터, 및 상기 패드로부터 정전 방전전류를 상기 제2도전링에 흐르게 하며, 상기 패드에 접속 에미터, 상기 제2도전링에 접속된 콜렉터 및 상기 제1도전링에 접속된 베이스를 지니는 3단자 PNP 트랜지스터를 포함하고, 상기 NPN 및 상기 PNP 트랜지스터가 상기 결합 캐패시터와 병렬로 접속되어 있는 회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/748,119 US5301084A (en) | 1991-08-21 | 1991-08-21 | Electrostatic discharge protection for CMOS integrated circuits |
US7/748119 | 1991-08-21 | ||
US07/748119 | 1991-08-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930005191A true KR930005191A (ko) | 1993-03-23 |
KR100260960B1 KR100260960B1 (ko) | 2000-07-01 |
Family
ID=25008109
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920014950A KR100260960B1 (ko) | 1991-08-21 | 1992-08-20 | 상보형 금속 산화물 반도체 집적 회로용 정전방전보호 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5301084A (ko) |
JP (1) | JP3174636B2 (ko) |
KR (1) | KR100260960B1 (ko) |
Families Citing this family (49)
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US5644460A (en) * | 1994-01-21 | 1997-07-01 | National Semiconductor Corporation | Multi-rail electrostatic discharge protection device |
EP0688054A3 (en) * | 1994-06-13 | 1996-06-05 | Symbios Logic Inc | Protection against electrostatic discharges for a semiconductor integrated circuit device |
US5610791A (en) * | 1994-09-26 | 1997-03-11 | International Business Machines Corporation | Power sequence independent electrostatic discharge protection circuits |
FR2725848A1 (fr) * | 1994-10-17 | 1996-04-19 | Sgs Thomson Microelectronics | Dispositif de protection d'un circuit contre des surtensions |
EP0740344B1 (en) * | 1995-04-24 | 2002-07-24 | Conexant Systems, Inc. | Method and apparatus for coupling multiple independent on-chip Vdd busses to an ESD core clamp |
US5532178A (en) * | 1995-04-27 | 1996-07-02 | Taiwan Semiconductor Manufacturing Company | Gate process for NMOS ESD protection circuits |
US5615073A (en) * | 1995-06-22 | 1997-03-25 | National Semiconductor Corporation | Electrostatic discharge protection apparatus |
US5745323A (en) * | 1995-06-30 | 1998-04-28 | Analog Devices, Inc. | Electrostatic discharge protection circuit for protecting CMOS transistors on integrated circuit processes |
EP0758129B1 (en) * | 1995-08-02 | 2001-05-23 | STMicroelectronics S.r.l. | Flash EEPROM with integrated device for limiting the erase source voltage |
WO1997010615A1 (en) * | 1995-09-11 | 1997-03-20 | Analog Devices, Inc. (Adi) | Electrostatic discharge protection network and method |
KR100211537B1 (ko) * | 1995-11-13 | 1999-08-02 | 김영환 | 정전기 방지기능을 갖는 트랜지스터 및 그 제조방법과 이를 이용한 데이타 출력버퍼 |
KR100211539B1 (ko) | 1995-12-29 | 1999-08-02 | 김영환 | 반도체소자의 정전기방전 보호장치 및 그 제조방법 |
US5751525A (en) * | 1996-01-05 | 1998-05-12 | Analog Devices, Inc. | EOS/ESD Protection circuit for an integrated circuit with operating/test voltages exceeding power supply rail voltages |
US6172590B1 (en) | 1996-01-22 | 2001-01-09 | Surgx Corporation | Over-voltage protection device and method for making same |
US5949694A (en) * | 1996-04-26 | 1999-09-07 | Texas Instruments Incorporated | Method and system for extracting high current parasitic bipolar transistor parameters of an MOS device during overvoltage events |
US5892262A (en) * | 1996-06-03 | 1999-04-06 | Winbond Electronics Corp. | Capacitor-triggered electrostatic discharge protection circuit |
US5917689A (en) * | 1996-09-12 | 1999-06-29 | Analog Devices, Inc. | General purpose EOS/ESD protection circuit for bipolar-CMOS and CMOS integrated circuits |
US5838146A (en) * | 1996-11-12 | 1998-11-17 | Analog Devices, Inc. | Method and apparatus for providing ESD/EOS protection for IC power supply pins |
KR100470183B1 (ko) * | 1997-08-30 | 2005-06-08 | 주식회사 하이닉스반도체 | 반도체소자의정전기보호회로 |
US5926353A (en) * | 1998-03-02 | 1999-07-20 | Hewlett-Packard Co. | Method for protecting mixed signal chips from electrostatic discharge |
US6130459A (en) | 1998-03-10 | 2000-10-10 | Oryx Technology Corporation | Over-voltage protection device for integrated circuits |
US6064094A (en) * | 1998-03-10 | 2000-05-16 | Oryx Technology Corporation | Over-voltage protection system for integrated circuits using the bonding pads and passivation layer |
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US6583972B2 (en) | 2000-06-15 | 2003-06-24 | Sarnoff Corporation | Multi-finger current ballasting ESD protection circuit and interleaved ballasting for ESD-sensitive circuits |
US6472286B1 (en) * | 2000-08-09 | 2002-10-29 | Taiwan Semiconductor Manufacturing Company | Bipolar ESD protection structure |
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JP2002305254A (ja) * | 2001-04-05 | 2002-10-18 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
DE10148794B4 (de) * | 2001-10-02 | 2005-11-17 | Infineon Technologies Ag | Verfahren zum Herstellen eines MOS-Transistors und MOS-Transistor |
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US6952333B1 (en) | 2003-09-15 | 2005-10-04 | National Semiconductor Corporation | ESD protection circuit for high-voltage, high DV/DT pads |
US6970336B2 (en) * | 2003-10-10 | 2005-11-29 | Freescale Semiconductor, Inc. | Electrostatic discharge protection circuit and method of operation |
US7446990B2 (en) * | 2005-02-11 | 2008-11-04 | Freescale Semiconductor, Inc. | I/O cell ESD system |
KR100795328B1 (ko) * | 2006-11-30 | 2008-01-21 | 삼성전자주식회사 | 정전기 방전 특성을 고려한 전계효과 트랜지스터의 모델링회로 |
US7804669B2 (en) * | 2007-04-19 | 2010-09-28 | Qualcomm Incorporated | Stacked ESD protection circuit having reduced trigger voltage |
US9343900B2 (en) * | 2008-07-24 | 2016-05-17 | Robert Bosch Gmbh | Passive network for electrostatic protection of integrated circuits |
CN101916992B (zh) * | 2010-07-28 | 2013-07-31 | 锐迪科创微电子(北京)有限公司 | pHEMT射频开关静电保护装置及包含该装置的射频前端模块 |
JP5703103B2 (ja) * | 2011-04-13 | 2015-04-15 | 株式会社東芝 | 半導体装置及びdc−dcコンバータ |
JP5696074B2 (ja) | 2012-03-16 | 2015-04-08 | 株式会社東芝 | 半導体装置 |
US9972999B2 (en) * | 2014-08-08 | 2018-05-15 | Qorvo Us, Inc. | Electrostatic discharge (ESD) protection circuit |
US10147688B2 (en) | 2016-02-25 | 2018-12-04 | Allegro Microsystems, Llc | Integrated circuit device with overvoltage discharge protection |
US9941224B2 (en) * | 2016-08-24 | 2018-04-10 | Allegro Microsystems, Llc | Multi-die integrated circuit device with capacitive overvoltage protection |
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JPS6048106B2 (ja) * | 1979-12-24 | 1985-10-25 | 富士通株式会社 | 半導体集積回路 |
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JPH07105472B2 (ja) * | 1988-07-29 | 1995-11-13 | 株式会社東芝 | 入力保護回路 |
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CA1314946C (en) * | 1989-02-01 | 1993-03-23 | Colin Harris | Protection of analog reference and bias voltage inputs |
US4930036A (en) * | 1989-07-13 | 1990-05-29 | Northern Telecom Limited | Electrostatic discharge protection circuit for an integrated circuit |
-
1991
- 1991-08-21 US US07/748,119 patent/US5301084A/en not_active Expired - Lifetime
-
1992
- 1992-08-20 KR KR1019920014950A patent/KR100260960B1/ko not_active IP Right Cessation
- 1992-08-21 JP JP22297292A patent/JP3174636B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH05283618A (ja) | 1993-10-29 |
JP3174636B2 (ja) | 2001-06-11 |
US5301084A (en) | 1994-04-05 |
KR100260960B1 (ko) | 2000-07-01 |
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