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Application filed by 안시환, 삼성전자 주식회사filedCritical안시환
Priority to KR870014027ApriorityCriticalpatent/KR890010706A/en
Publication of KR890010706ApublicationCriticalpatent/KR890010706A/en
퍼스널 컴퓨터의 암호와 회로Password and circuit of personal computer
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명의 회로도.1 is a circuit diagram of the present invention.
Claims (1)
비교회로부(1)의 핀(P0-P7), (Q0-Q7)단자와 출력단자에는 램(RAM)의 어드레스단자(AD)와 딥스윗치단(Sw1)과 앤드개이트(A1)의 입력단을 각각 연결하고, 상기 램(RAM)의 칩선택신호단자에는 D플립플롭(FF1)을 통해 낸드게이트(N1)의 입력단을 연결함과 더불어 전원단과 스타트단에드 앤드게이트(A1)와 낸드게이트(N1)의 입력단이 연결된 상기 내드게이트(N1)의 출력단에는 비 메스커블인터럽트를 연결하여 구성됨을 특징으로 하는 퍼스널 컴퓨터의 암호화회로.Pin (P 0 -P 7 ), (Q 0 -Q 7 ) and output terminals of the comparison circuit section (1) Is connected to the address terminal AD of the RAM, the input terminal of the deep switch stage Sw 1 and the end gate A 1 , respectively, and the chip select signal terminal of the RAM. The N gate is connected to an input terminal of the NAND gate N 1 through a D flip-flop FF 1 , and the NAD gate N to which an input terminal of the power supply terminal and the start end ED gate A 1 and the NAND gate N 1 are connected. 1 ) non mesable interrupt on output An encryption circuit of a personal computer, characterized in that configured to connect.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR870014027A1987-12-091987-12-09
Encryption circuit of personal computer
KR890010706A
(en)