KR20050037712A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
- Publication number
- KR20050037712A KR20050037712A KR1020030072960A KR20030072960A KR20050037712A KR 20050037712 A KR20050037712 A KR 20050037712A KR 1020030072960 A KR1020030072960 A KR 1020030072960A KR 20030072960 A KR20030072960 A KR 20030072960A KR 20050037712 A KR20050037712 A KR 20050037712A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- insulating film
- forming
- metal wiring
- interlayer insulating
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 45
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 25
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 26
- 150000004767 nitrides Chemical class 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000008239 natural water Substances 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 5
- 239000012790 adhesive layer Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 소정의 구조가 형성된 반도체 기판 상부에 도전층 및 절연막을 형성하는 단계와, 상기 도전층 및 상기 절연막을 패터닝하여 금속 배선을 형성하는 단계와, 전체 구조 상부에 층간 절연막을 형성한 후 평탄화시키는 단계와, 상기 층간 절연막의 소정 영역을 식각하여 상기 절연막을 노출시키는 단계와, 상기 노출된 절연막을 제거하는 단계를 포함하여, 층간 절연막을 형성한 후 비아 홀을 형성하기 위한 식각 공정에서 금속 배선 상부의 손실을 방지하여 비아 홀의 면저항 특성을 향상시킬 수 있고, 감광 물질과의 선택비 부족에 의한 금속 배선의 패턴 불량을 방지할 수 있는 반도체 소자의 제조 방법이 제시된다. The present invention relates to a method for manufacturing a semiconductor device, comprising the steps of: forming a conductive layer and an insulating film on a semiconductor substrate having a predetermined structure; forming a metal wiring by patterning the conductive layer and the insulating film; Forming an interlayer insulating layer thereon, and planarizing the same; exposing the insulating layer by etching a predetermined region of the interlayer insulating layer; and removing the exposed insulating layer; The method of manufacturing a semiconductor device capable of improving the sheet resistance characteristic of the via hole by preventing the loss of the upper portion of the metal wiring in the etching process for forming the metal, and preventing the pattern defect of the metal wiring due to the lack of selectivity with the photosensitive material. Presented.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 질화막을 적용하여 금속 배선을 형성함으로써 이후 층간 절연막을 형성한 후 비아 홀을 형성하기 위한 식각 공정에서 금속 배선 상부의 손실을 방지할 수 있고, 감광 물질과의 선택비 부족에 의한 금속 배선의 패턴 불량을 방지할 수 있는 반도체 소자의 제조 방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and in particular, by forming a metal wiring by applying a nitride film to prevent the loss of the upper portion of the metal wiring in the etching process for forming the via hole after forming the interlayer insulating film thereafter, The present invention relates to a method for manufacturing a semiconductor device capable of preventing a pattern defect of a metal wiring due to lack of a selection ratio with a substance.
도 1은 종래의 반도체 소자의 제조 방법을 설명하기 위해 도시한 소자의 단면도로서, 금속 배선을 형성한 후 층간 절연막의 소정 영역을 식각하여 금속 배선을 노출시키는 비아 홀을 형성하는 방법을 예를들어 설명하기 위한 단면도이다.1 is a cross-sectional view of a device illustrated to explain a conventional method of manufacturing a semiconductor device. For example, a method of forming a via hole exposing a metal wiring by etching a predetermined region of an interlayer insulating layer after forming the metal wiring is illustrated. It is sectional drawing for illustration.
도 1을 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 제 1 Ti막(12), 제 1 TiN막(13), Al막(14), 제 2 Ti막(15) 및 제 2 TiN막(16)을 적층한 후 패터닝하여 금속 배선(100)을 형성한다. 이러한 구조의 금속 배선(100)에서 제 1 Ti막(12)은 접착층의 역할을 하고, 제 1 TiN막(13)은 확산 방지막의 역할을 한다. 그리고, Al막(14)은 저항이 낮기 때문에 주로 전기 신호를 전달하는 역할을 한다. 또한, 제 2 Ti막(15)은 접착층의 역할을 하고, 제 2 TiN막(16)은 감광 물질의 패터닝시 빛을 흡수하여 빛의 반사를 줄여주는 반사 방지막의 역할을 한다. 이렇게 금속 배선(100)을 형성한 후 전체 구조 상부에 층간 절연막(17)을 형성하고, 화학적 기계적 연마 공정을 실시하여 층간 절연막(17)을 평탄화시킨다. 그리고, 층간 절연막(17)의 소정 영역을 식각하여 금속 배선(100)을 노출시키는 비아 홀(18)을 형성한다.Referring to FIG. 1, a first Ti film 12, a first TiN film 13, an Al film 14, a second Ti film 15, and a second layer are formed on a semiconductor substrate 11 on which a predetermined structure is formed. The TiN film 16 is stacked and then patterned to form the metal wiring 100. In the metal wiring 100 having such a structure, the first Ti film 12 serves as an adhesive layer, and the first TiN film 13 serves as a diffusion barrier. In addition, since the Al film 14 has a low resistance, the Al film 14 mainly serves to transmit an electrical signal. In addition, the second Ti film 15 serves as an adhesive layer, and the second TiN film 16 serves as an anti-reflection film that absorbs light during patterning of the photosensitive material to reduce reflection of light. After forming the metal wiring 100, an interlayer insulating layer 17 is formed on the entire structure, and a chemical mechanical polishing process is performed to planarize the interlayer insulating layer 17. Then, the via hole 18 exposing the metal wiring 100 is formed by etching a predetermined region of the interlayer insulating layer 17.
그러나, 금속 배선(100)의 패턴 밀도에 따라 층간 절연막(17)의 형성 및 연마 공정에서 층간 절연막(17)의 두께 차이가 발생되는데, 초기에는 층간 절연막(17)의 두께 차이가 약 1000Å 정도 나지만 층간 절연막(17)이 다층으로 형성되면서 크게는 약 5000Å 정도 차이가 나게 된다. 그런데, 층간 절연막(17)의 두께가 차이나더라도 비아 홀 식각 공정은 두께 차이에 따라 식각 깊이를 조절하여 실시할 수 없다. 따라서, 바아 홀을 형성하기 위한 식각 공정을 실시할 때 층간 절연막의 두께가 얇은 영역(A)이 층간 절연막의 두께가 두꺼운 영역(B)보다도 금속 배선(100)의 제 2 TiN막(16)이 더 손실됨을 볼 수 있다.However, depending on the pattern density of the metal wiring 100, a difference in thickness of the interlayer insulating layer 17 may occur during the formation and polishing of the interlayer insulating layer 17. Initially, the thickness difference of the interlayer insulating layer 17 may be about 1000 μs. As the interlayer insulating layer 17 is formed in multiple layers, the interlayer insulating layer 17 is largely about 5000 kV. However, even if the thickness of the interlayer insulating layer 17 is different, the via hole etching process may not be performed by adjusting the etching depth according to the thickness difference. Therefore, when the etching process for forming the bar hole is performed, the region A of which the thickness of the interlayer insulating film is thin is larger than the region B of which the thickness of the interlayer insulating film is thicker. You can see more loss.
이렇듯, 패턴 밀도의 차이에 따라 한개의 칩 또는 웨이퍼에 형성되는 층간 절연막의 두께가 다르게 되고, 비아 홀의 식각량이 다르게 되어 금속 배선의 제 2 TiN막의 손실량도 다르게 된다. 금속 배선의 제 2 TiN막의 손실량은 비아 저항에 직접적인 영향을 주게 되는데, 비아 홀의 면저항을 낮추기 위해서는 제 2 TiN막의 손실량을 더 많게하면 된다. 이는 금속 배선의 제 2 TiN막의 두께를 변화시키고 비아 홀을 형성하기 위한 건식 식각을 실시한 후 비아 홀의 면저항을 확인한 결과에 의해 증명되는데, 제 2 TiN막의 두께가 얇은 영역에서 비아 홀의 면저항이 낮아 비아 홀의 면저항 특성이 좋은 것을 확인 할 수 있다. 따라서, 이러한 제 2 TiN막의 손실 차이에 의해 비아 홀의 면저항 특성이 지역에 따라 달라지게 된다.As described above, the thickness of the interlayer insulating film formed on one chip or wafer is different according to the difference in the pattern density, and the etching amount of the via hole is different, so that the loss amount of the second TiN film of the metal wiring is also different. The loss amount of the second TiN film of the metal wiring directly affects the via resistance. In order to lower the sheet resistance of the via hole, the loss amount of the second TiN film may be increased. This is proved by the result of checking the sheet resistance of the via hole after changing the thickness of the second TiN film of the metal wiring and forming the via hole. It can be confirmed that the sheet resistance characteristics are good. Therefore, the sheet resistance characteristic of the via hole varies depending on the region due to the loss difference of the second TiN film.
또한, 금속 배선의 패터닝시 감광 물질과의 선택비 부족으로 인해서 금속 배선에 손상을 주어 금속 배선의 패턴 불량을 초래할 수가 있다.In addition, due to the lack of selectivity with the photosensitive material during patterning of the metal wiring, the metal wiring may be damaged, resulting in a pattern defect of the metal wiring.
본 발명의 목적은 질화막을 적용하여 금속 배선을 형성함으로써 이후 층간 절연막을 형성한 후 비아 홀을 형성하기 위한 식각 공정에서 금속 배선 상부의 손실을 방지하여 비아 홀의 면저항 특성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.An object of the present invention is to form a metal wiring by applying a nitride film to prevent the loss of the upper portion of the metal wiring in the etching process for forming the via hole after forming the interlayer insulating film thereafter to improve the sheet resistance characteristics of the via hole It is to provide a manufacturing method.
본 발명의 다른 목적은 질화막을 적용하여 금속 배선을 형성함으로써 감광 물질과의 선택비 부족에 의한 금속 배선의 패턴 불량을 방지할 수 있는 반도체 소자의 제조 방법을 제공하는데 있다. Another object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent a pattern defect of a metal wiring due to lack of selectivity with a photosensitive material by forming a metal wiring by applying a nitride film.
본 발명에 따른 반도체 소자의 제조 방법은 소정의 구조가 형성된 반도체 기판 상부에 도전층 및 절연막을 형성하는 단계와, 상기 도전층 및 상기 절연막을 패터닝하여 금속 배선을 형성하는 단계와, 전체 구조 상부에 층간 절연막을 형성한 후 평탄화시키는 단계와, 상기 층간 절연막의 소정 영역을 식각하여 상기 절연막을 노출시키는 단계와, 상기 노출된 절연막을 제거하는 단계를 포함한다.A method of manufacturing a semiconductor device according to the present invention includes the steps of forming a conductive layer and an insulating film on the semiconductor substrate having a predetermined structure, forming a metal wiring by patterning the conductive layer and the insulating film, and over the entire structure Forming an interlayer insulating film, and then planarizing, exposing the insulating film by etching a predetermined region of the interlayer insulating film, and removing the exposed insulating film.
또한, 본 발명에 따른 반도체 소자의 제조 방법은 소정의 구조가 형성된 반도체 기판 상부에 제 1 Ti막, 제 1 TiN막, Al막, 제 2 Ti막 및 제 2 TiN막을 순차적으로 형성하는 단계와, 상기 제 2 TiN막 상부에 절연막을 형성하는 단계와, 상기 제 1 Ti막 내지 상기 절연막을 패터닝하여 금속 배선을 형성하는 단계와, 전체 구조 상부에 층간 절연막을 형성한 후 평탄화시키는 단계와, 상기 층간 절연막의 소정 영역을 식각하여 상기 절연막을 노출시키는 단계와, 상기 노출된 절연막을 제거하는 단계를 포함한다. In addition, the method of manufacturing a semiconductor device according to the present invention includes the steps of sequentially forming a first Ti film, a first TiN film, an Al film, a second Ti film and a second TiN film on a semiconductor substrate having a predetermined structure; Forming an insulating film over the second TiN film, patterning the first Ti film to the insulating film to form a metal wiring, forming an interlayer insulating film over the entire structure, and then planarizing the interlayer Etching the predetermined region of the insulating film to expose the insulating film; and removing the exposed insulating film.
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 설명하기로 한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
도 2(a) 및 도 2(b)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도로서, 금속 배선을 형성한 후 층간 절연막의 소정 영역을 식각하여 금속 배선을 노출시키는 비아 홀을 형성하는 방법을 예를들어 설명하기 위한 단면도이다.2 (a) and 2 (b) are cross-sectional views of a device for explaining a method of manufacturing a semiconductor device according to the present invention. After forming the metal wires, the vias are exposed by etching a predetermined region of the interlayer insulating film. It is sectional drawing for demonstrating, for example, the method of forming a hole.
도 2(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(21) 상부에 제 1 Ti막(22), 제 1 TiN막(23), Al막(24), 제 2 Ti막(25) 및 제 2 TiN막(26)을 순차적으로 형성한 후 그 상부에 질화막(27)을 형성한다. 그리고, 이들을 패터닝하여 금속 배선(200)을 형성한다. 이러한 구조의 금속 배선(200)에서 제 1 Ti막(22)은 접착층의 역할을 하고, 제 1 TiN막(23)은 확산 방지막의 역할을 한다. 그리고, Al막(24)은 저항이 낮기 때문에 주로 전기 신호를 전달하는 역할을 한다. 또한, 제 2 Ti막(25)은 접착층의 역할을 하고, 제 2 TiN막(26)은 감광 물질의 패터닝시 빛을 흡수하여 빛의 반사를 줄여주는 반사 방지막의 역할을 한다. 그리고, 질화막(27)은 하드 마스크로 작용하여 금속 배선(200)을 형성하기 위한 식각 공정시 감광 물질의 선택비 부족을 보상해주어 금속 배선의 패터닝을 용이하게 한다. 이렇게 금속 배선(200)을 형성한 후 전체 구조 상부에 층간 절연막(28)을 형성하고, 화학적 기계적 연마 공정을 실시하여 층간 절연막(28)을 평탄화시킨다. 그리고, 층간 절연막(28)의 소정 영역을 식각하여 금속 배선(200)을 노출시키는 비아 홀(29)을 형성한다. 비아 홀을 형성하기 위한 식각 공정은 질화막(27)에서 식각이 정지되도록 CxFy(x, y는 자연수) 가스를 기본으로 진행한다. 이때, 질소 또는 산소등을 추가하여 식각 공정을 실시하여도 된다. CxFy 가스를 기본으로 식각 공정을 진행하면 층간 절연막(28)과 질화막(27)의 선택비는 10:1 이상으로 되어 질화막(27)에서 식각이 정지된다.Referring to FIG. 2A, a first Ti film 22, a first TiN film 23, an Al film 24, and a second Ti film 25 are formed on a semiconductor substrate 21 on which a predetermined structure is formed. And a second TiN film 26 are sequentially formed, and then a nitride film 27 is formed thereon. Then, these are patterned to form the metal wiring 200. In the metal wiring 200 having such a structure, the first Ti film 22 serves as an adhesive layer, and the first TiN film 23 serves as a diffusion barrier. In addition, since the Al film 24 has low resistance, the Al film 24 mainly serves to transmit an electrical signal. In addition, the second Ti film 25 serves as an adhesive layer, and the second TiN film 26 serves as an anti-reflection film that absorbs light and reduces reflection of light when the photosensitive material is patterned. In addition, the nitride layer 27 serves as a hard mask to compensate for the lack of selectivity of the photosensitive material during the etching process for forming the metal line 200, thereby facilitating the patterning of the metal line. After forming the metal wiring 200, the interlayer insulating film 28 is formed on the entire structure, and the chemical mechanical polishing process is performed to planarize the interlayer insulating film 28. Then, the via hole 29 exposing the metal wire 200 is formed by etching a predetermined region of the interlayer insulating layer 28. The etching process for forming the via hole is performed based on CxFy (x, y is natural water) gas so that the etching is stopped in the nitride film 27. At this time, an etching process may be performed by adding nitrogen or oxygen. When the etching process is performed based on the CxFy gas, the selectivity between the interlayer insulating film 28 and the nitride film 27 is 10: 1 or more, and the etching is stopped in the nitride film 27.
이렇게 높은 선택비를 갖고 있는 가스로 식각 공정을 진행하면 금속 배선(200)의 패턴 밀도에 따라 층간 절연막(28)의 두께 차이가 심하더라도 금속 배선(200) 상부의 층간 절연막(28)은 전부 식각되고, 질화막(27)에서 식각이 정지되므로 금속 배선의 제 2 TiN막(26)의 손실은 없게 된다.When the etching process is performed using a gas having such a high selectivity, the interlayer insulating film 28 on the upper portion of the metal wiring 200 is etched even if the thickness difference of the interlayer insulating film 28 is large depending on the pattern density of the metal wiring 200. Since the etching is stopped in the nitride film 27, there is no loss of the second TiN film 26 of the metal wiring.
도 2(b)를 참조하면, 비아 홀에 의해 노출된 질화막(28)을 CF4, O2 및 Ar으로 활성화된 플라즈마를 이용한 건식 식각 공정으로 제거한다. 이때, 질화막(28)을 제거하기 위한 식각 공정은 CxFy 또는 CHF3, N2, He등의 가스를 추가하여 실시해도 된다. 이렇게 질화막(27)을 제거하면 금속 배선(200)의 제 2 TiN막(26)이 어느정도 손상되는데, 이러한 손상 정도는 층간 절연막(28)의 두께 정도에 관계없이 일정하게 된다.Referring to FIG. 2B, the nitride film 28 exposed by the via hole is removed by a dry etching process using plasma activated with CF 4 , O 2, and Ar. At this time, the etching process for removing the nitride film 28 may be performed by adding a gas such as CxFy or CHF 3 , N 2 , He, or the like. When the nitride film 27 is removed in this manner, the second TiN film 26 of the metal wire 200 is damaged to some extent, and the degree of damage becomes constant regardless of the thickness of the interlayer insulating film 28.
상술한 바와 같이 본 발명에 의하면 질화막을 적용하여 금속 배선을 형성함으로써 감광 물질과의 선택비 부족으로 인한 금속 배선의 패턴 불량을 해결할 수 있다.As described above, according to the present invention, a metal wiring may be formed by applying a nitride film to solve a pattern defect of the metal wiring due to lack of selectivity with the photosensitive material.
또한, 층간 절연막을 형성한 후 비아 홀을 형성하기 위한 건식 식각 공정에서 금속 배선의 패턴 밀도에 따른 층간 절연막의 두께 차이에 따라 식각량이 달라지데 되는데, 질화막을 적용하여 금속 배선을 형성함으로써 질화막이 식각 정지막으로 작용하기 때문에 층간 절연막의 두께만큼 더 식각 공정을 실시하여도 두께 차이를 극복할 수 있다.In addition, in the dry etching process for forming the via hole after forming the interlayer insulating film, the etching amount is changed according to the thickness difference of the interlayer insulating film according to the pattern density of the metal wiring, and the nitride film is etched by forming the metal wiring by applying the nitride film. Since it acts as a stop film, even if the etching process is performed as much as the thickness of the interlayer insulating film, the thickness difference can be overcome.
그리고, 비아 홀을 형성한 후 노출된 질화막을 제거하기 때문에 이 공정에서 금속 배선의 제 2 TiN막의 손상을 일정하게 할 수 있어 비아 홀의 면저항 특성을 거의 동일하게 유지할 수 있다. 즉, 제 2 TiN막의 손상 조절은 비아 홀의 면저항과 직접적인 연관이 있기 때문에 비아 홀의 면저항을 낮추려면 제 2 TiN막을 많이 손상시키면 된다.Since the exposed nitride film is removed after the via hole is formed, damage to the second TiN film of the metal wiring can be made constant in this process, and the sheet resistance characteristics of the via hole can be maintained almost the same. That is, since the damage control of the second TiN film is directly related to the sheet resistance of the via hole, the second TiN film may be damaged much to lower the sheet resistance of the via hole.
도 1은 종래의 반도체 소자의 제조 방법을 설명하기 위해 도시한 소자의 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a sectional view of a device shown for explaining a conventional method for manufacturing a semiconductor device.
도 2는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 소자의 단면도. Figure 2 is a cross-sectional view of the device shown for explaining a method for manufacturing a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 및 21 : 반도체 기판 12 및 22 : 제 1 Ti막11 and 21: semiconductor substrate 12 and 22: first Ti film
13 및 23 : 제 1 TiN막 14 및 24 : Al막13 and 23: first TiN film 14 and 24: Al film
15 및 25 : 제 2 Ti막 16 및 26 : 제 2 TiN막15 and 25: 2nd Ti film 16 and 26: 2nd TiN film
17 및 28 : 층간 절연막 27 : 질화막17 and 28: interlayer insulation film 27: nitride film
100 및 200 : 금속 배선 100 and 200: metal wiring
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030072960A KR20050037712A (en) | 2003-10-20 | 2003-10-20 | Method of manufacturing a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030072960A KR20050037712A (en) | 2003-10-20 | 2003-10-20 | Method of manufacturing a semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20050037712A true KR20050037712A (en) | 2005-04-25 |
Family
ID=37240328
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020030072960A KR20050037712A (en) | 2003-10-20 | 2003-10-20 | Method of manufacturing a semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20050037712A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100717502B1 (en) * | 2005-12-29 | 2007-05-14 | 동부일렉트로닉스 주식회사 | Fabricating method of metal line in semiconductor device |
US7655562B2 (en) | 2006-12-04 | 2010-02-02 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor memory device |
-
2003
- 2003-10-20 KR KR1020030072960A patent/KR20050037712A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100717502B1 (en) * | 2005-12-29 | 2007-05-14 | 동부일렉트로닉스 주식회사 | Fabricating method of metal line in semiconductor device |
US7655562B2 (en) | 2006-12-04 | 2010-02-02 | Hynix Semiconductor Inc. | Method of manufacturing semiconductor memory device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100571417B1 (en) | Dual damascene wiring of semiconductor device and manufacturing method thereof | |
KR100333382B1 (en) | Method for forming multi-level metal interconnection of semiconductor device | |
TWI236094B (en) | Method for forming multi-layer metal line of semiconductor device | |
US6831007B2 (en) | Method for forming metal line of Al/Cu structure | |
KR20070008118A (en) | Method for forming the metal contact of semiconductor device | |
KR20050037712A (en) | Method of manufacturing a semiconductor device | |
US20080153279A1 (en) | Method For Manufacturing Semiconductor Device | |
KR100876532B1 (en) | Manufacturing Method of Semiconductor Device | |
KR100460772B1 (en) | Method for fabricating semiconductor device | |
KR100578223B1 (en) | Method of fabricating of dual damascene of semiconductor device | |
KR100372770B1 (en) | A method of manufacturing self align contact of semiconductor device | |
KR101081851B1 (en) | Method of forming a dual damascene pattern in a semiconductor device | |
KR100503381B1 (en) | Metal line in a semiconductor and method for forming the same | |
KR100421278B1 (en) | Fabricating method for semiconductor device | |
KR100532981B1 (en) | Etching method of semiconductor device | |
KR100411026B1 (en) | Method of manufacturing a semiconductor device | |
KR100279047B1 (en) | A fabricating method of contact hole of semiconductor device | |
KR100780616B1 (en) | Method for fabricating semiconductor device | |
KR19990060819A (en) | Metal wiring formation method of semiconductor device | |
KR100223283B1 (en) | Semiconductor element metal film manufacturing method | |
KR100571408B1 (en) | Dual damascene wiring manufacturing method of semiconductor device | |
KR100900773B1 (en) | Method for fabricating contact hole in semiconductor device | |
KR100792392B1 (en) | Method for forming metal interconnecting line using low permittivity layer | |
KR20080074504A (en) | Semiconductor device and method of manufacturing thereof | |
KR100415988B1 (en) | Method for forming a via hole |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
WITN | Withdrawal due to no request for examination |