KR20030052828A - Fabricating method of metal wire in semiconductor - Google Patents
Fabricating method of metal wire in semiconductor Download PDFInfo
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- KR20030052828A KR20030052828A KR1020010082944A KR20010082944A KR20030052828A KR 20030052828 A KR20030052828 A KR 20030052828A KR 1020010082944 A KR1020010082944 A KR 1020010082944A KR 20010082944 A KR20010082944 A KR 20010082944A KR 20030052828 A KR20030052828 A KR 20030052828A
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- forming
- tungsten
- metal wiring
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 69
- 239000002184 metal Substances 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 28
- 239000010937 tungsten Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910001930 tungsten oxide Inorganic materials 0.000 claims abstract description 21
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 14
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 10
- 238000007872 degassing Methods 0.000 claims description 8
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 2
- YZCKVEUIGOORGS-NJFSPNSNSA-N Tritium Chemical compound [3H] YZCKVEUIGOORGS-NJFSPNSNSA-N 0.000 claims 1
- 229910001873 dinitrogen Inorganic materials 0.000 claims 1
- VVRQVWSVLMGPRN-UHFFFAOYSA-N oxotungsten Chemical class [W]=O VVRQVWSVLMGPRN-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 48
- 239000010410 layer Substances 0.000 description 13
- 238000000151 deposition Methods 0.000 description 9
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 8
- 229910052731 fluorine Inorganic materials 0.000 description 8
- 239000011737 fluorine Substances 0.000 description 8
- 238000009832 plasma treatment Methods 0.000 description 5
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- XROWMBWRMNHXMF-UHFFFAOYSA-J titanium tetrafluoride Chemical compound [F-].[F-].[F-].[F-].[Ti+4] XROWMBWRMNHXMF-UHFFFAOYSA-J 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 210000004185 liver Anatomy 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로서, 특히 FSG(Fluorine doped Silicate Glass)를 사용하는 다층 배선 구조에서 CMP(Chemical Mechanical Polishing) 후 금속막의 증착 전 잔류 텅스텐 산화물을 제거하여 플러그와 금속 배선간의 접촉 특성을 향상시키는 안정적인 금속 배선을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices. In particular, in a multilayer wiring structure using Fluorine doped Silicate Glass (FSG), a plug and a metal wiring are removed by removing residual tungsten oxide before deposition of a metal film after CMP A method of forming a stable metal wiring to improve the contact characteristics of the liver.
최근 디자인 룰(design rule)이 0.25㎛ 이상으로 반도체 소자가 고집적됨에 따라 반도체 소자 제조시 다층의 배선이 요구되고, 이에 따라 배리어 메탈(barrier metal), 텅스텐 플러그, CMP, 금속 배선 형성 등의 공정 조합으로 이루어진 다층 금속 배선 공정의 적용이 대부분 사용되고 있다.As semiconductor devices are highly integrated with a design rule of 0.25 μm or more, multilayer wiring is required in the manufacture of semiconductor devices, and accordingly, a process combination such as barrier metal, tungsten plug, CMP, and metal wiring is formed. The application of the multilayer metal wiring process which consists of these is used mostly.
또한, 소자의 고직접화가 될수록 접촉 저항 및 RC 딜레이 시간(RC delay time)이 중요해지고 있고, 상기 RC 딜레이 시간을 줄이기 위해서 층간절연막으로 저유전율을 갖는 FSG(Fluorine doped Silicate Glass)를 많이 사용하고 있다.In addition, contact resistance and RC delay time become more important as the device becomes more directly connected, and in order to reduce the RC delay time, many FDO (Fluorine doped Silicate Glass) having low dielectric constant is used as the interlayer insulating film. .
상기 FSG는 종래 USG(Undoped Silicate Glass)나 TEOS(Tetra Ethyl Ortho Silicate)에 비해 유전율 특성이 좋으나 FSG 막 내에 포함되어 있는 불소(F) 성분이 배리어 메탈(barrier metal)에 침투하거나 상부의 메탈층에 침투하여 금속 배선의 특성을 저하시키는 단점이 있다.The FSG has better dielectric constant than conventional Undoped Silicate Glass (USG) or Tetra Ethyl Ortho Silicate (TEOS), but the fluorine (F) component contained in the FSG film penetrates the barrier metal or is formed on the upper metal layer. It penetrates and deteriorates the characteristics of the metal wiring.
특히, 텅스텐 플러그 형성한 다음, CMP 수행한 후에 텅스텐 산화막이 존재할 경우 상기 텅스텐 산화막은 FSG의 F 성분과 반응하여 상부의 금속 배선과의 접촉을 저하시켜 접촉 저항의 증가 및 단선을 유발하게 된다.In particular, when a tungsten oxide film is present after the formation of the tungsten plug and the CMP is performed, the tungsten oxide film reacts with the F component of the FSG to lower the contact with the upper metal wiring, thereby causing an increase in contact resistance and disconnection.
이는 소자가 고집적화됨에 따라 비아 홀의 크기가 미세해짐에 따른 결과이다.This is a result of the size of via holes becoming finer as the device becomes more integrated.
이하, 도면을 참조하여 종래 기술에 따른 반도체 소자의 금속 배선 형성 방법을 상세히 설명한다.Hereinafter, a metal wire forming method of a semiconductor device according to the prior art will be described in detail with reference to the accompanying drawings.
도 1a 내지 1c는 종래 기술에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the related art.
도 1a에 도시한 바와 같이, 기판의 베이스(101) 상에 제 1 절연막(102)을 형성하고 상기 제 1 절연막(102) 상에 제 1 금속배선(103)을 스퍼터링 공정을 이용하여 전면에 증착한 다음, 선택적으로 패터닝하여 형성한다.As shown in FIG. 1A, a first insulating film 102 is formed on a base 101 of a substrate, and a first metal wiring 103 is deposited on the entire surface of the first insulating film 102 using a sputtering process. And then selectively patterned to form.
이어, 상기 제 1 금속배선(103)을 포함한 기판 전면에 화학기상증착법을 이용하여 FSG막(104a)과 TEOS(Tetra Ethyl Ortho Silicate)막(104b)을 차례로 증착하여 제 2 절연막(104)을 형성한다. 여기서, 상기와 같이 절연막을 FSG막(104)과 TEOS막(104b)의 이중막으로 구성하는 이유는 RC 딜레이 시간을 줄이기 위한 것이다.Subsequently, an FSG film 104a and a TEOS (Tetra Ethyl Ortho Silicate) film 104b are sequentially deposited on the entire surface of the substrate including the first metal wiring 103 by chemical vapor deposition to form a second insulating film 104. do. Here, the reason why the insulating film is composed of the double film of the FSG film 104 and the TEOS film 104b as described above is to reduce the RC delay time.
이어, 도 1b에 도시한 바와 같이 상기 제 1 금속배선(103)의 소정 영역이 드러나도록 상기 FSG막(104a)과 TEOS막(104b)을 식각하여 비아 홀(via hole)(105)을 형성한다.Subsequently, as shown in FIG. 1B, the FSG film 104a and the TEOS film 104b are etched to form a via hole 105 so that a predetermined region of the first metal wiring 103 is exposed. .
상기 비아 홀(105)을 포함한 기판 전면 상에 타이타늄과 타아타늄 질화물로 구성되는 확산방지막(106)을 증착한 후, 기판 전면에 WF6가스를 이용한 물리기상증착법(Physical Vapor Deposition)으로 상기 비아 홀(105)을 충분히 채우도록 텅스텐 플러그(107)를 형성한다.After depositing a diffusion barrier film 106 composed of titanium and itanium nitride on the entire surface of the substrate including the via hole 105, the vias were deposited by physical vapor deposition using WF 6 gas on the entire surface of the substrate. The tungsten plug 107 is formed to fill the hole 105 sufficiently.
마지막으로 도 1c에 도시한 바와 같이, 상기 제 2 절연막(104) 상에 증착되어 있는 텅스텐 층(107) 및 확산방지막(106)을 제 2 절연막(104)이 드러나도록 CMP공정을 통하여 제거하고 상기 텅스텐 플러그(107)에 상응하는 부분에 제 2 금속배선(108)을 형성한다. 이후, 상기 제 2 금속배선(108)을 포함한 기판 전면상에 제 2 절연막(104)과 같은 FSG막(109a)과 TEOS막(109b)으로 구성되는 제 3 절연막(109)을 형성한다.Finally, as shown in FIG. 1C, the tungsten layer 107 and the diffusion barrier layer 106 deposited on the second insulating layer 104 are removed through the CMP process so that the second insulating layer 104 is exposed. The second metal wiring 108 is formed in a portion corresponding to the tungsten plug 107. Thereafter, a third insulating film 109 including the FSG film 109a and the TEOS film 109b such as the second insulating film 104 is formed on the entire surface of the substrate including the second metal wiring 108.
이와 같은 공정을 반복 수행함으로써 다층 배선을 구현하게 된다.By repeating such a process, a multilayer wiring is realized.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로써, 다층 배선 구조에서 콘택(contact)이나 비아(via)의 플러그와 금속배선 간의 접촉 특성을 향상시켜 콘택 및 비아와 금속 배선간의 접촉 저항을 개선시킬 뿐만 아니라 안정적인 금속배선을 형성할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 목적이 있다.The present invention has been made to solve the above problems, improves the contact characteristics between the contact (via) or the plug of the via (via) and the metal wiring in the multilayer wiring structure to improve the contact resistance between the contact and the via and the metal wiring It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device which can not only improve but also form a stable metal wiring.
도 1a 내지 1c는 종래 기술에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 공정단면도.1A to 1C are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the related art.
도 2a 내지 2d는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 공정단면도.2A through 2D are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
201 : 기판 202 : 제 1 절연막201: substrate 202: first insulating film
203 : 제 1 금속배선 204 : 제 2 절연막203: first metal wiring 204: second insulating film
206 : 확산 방지막 207 : 텅스텐 플러그206: diffusion barrier 207: tungsten plug
208 : 텅스텐 산화물208: Tungsten Oxide
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성 방법은 기판 상에 제 1 절연막을 형성하는 공정과, 상기 제 1 절연막 상의 소정 영역에 제 1 금속 배선을 형성하는 공정과, 상기 제 1 금속배선을 포함한 기판 전면에 제 2 절연막을 형성하는 공정과, 상기 제 1 금속배선의 소정 부위가 드러나도록 상기 제 1 절연막을 선택적으로 식각하여 비아 홀을 형성하는 공정과, 상기 비아 홀을 포함한 기판 전면에 확산 방지막을 형성하는 공정과, 상기 비아 홀 내에 충분히 채워지도록 텅스텐을 매립하여 텅스텐 플러그를 형성하는 공정과, 상기 텅스텐 플러그를 포함한 기판 전면에 세정 공정을 통하여 텅스텐 산화물을 제거하는 공정과, 상기 텅스텐 플러그에 상응하는 영역에 제 2 금속배선을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The metal wiring forming method of the semiconductor device of the present invention for achieving the above object comprises the steps of forming a first insulating film on a substrate, forming a first metal wiring in a predetermined region on the first insulating film, Forming a second insulating film on the entire surface of the substrate including the first metal wiring, selectively etching the first insulating film so that a predetermined portion of the first metal wiring is exposed, and forming a via hole; Forming a diffusion barrier film on the entire surface of the substrate, forming a tungsten plug by embedding tungsten to be sufficiently filled in the via hole, and removing tungsten oxide through a cleaning process on the entire surface of the substrate including the tungsten plug; And forming a second metal wiring in a region corresponding to the tungsten plug. And a gong.
여기서, 상기 세정 공정은 제 2 금속배선의 형성 전 금속막을 증착하는 장비에, 탈가스를 진행하는 챔버를 장착하여 탈가스 챔버 내에서 수소 환원 가스를 넣어 텅스텐 산화물을 제거하거나 RF(Radio Frequency) 프리클린 챔버를 장착하여 수소 환원 가스를 넣어 플라즈마 처리로 텅스텐 산화물을 제거하는 것을 특징으로 한다.Here, the cleaning process is a device for depositing a metal film before the formation of the second metal wiring, a chamber for degassing is added to the hydrogen reduction gas in the degassing chamber to remove tungsten oxide or RF (Radio Frequency) free It is characterized in that the tungsten oxide is removed by plasma treatment by installing a clean chamber and putting a hydrogen reducing gas.
본 발명에 따른 반도체 소자의 금속배선 형성 방법은 텅스텐 플러깅(pluging)과 CMP 후에 기판 상에 잔류하는 텅스텐 산화물을 환원 가스 또는 플라즈마 처리로 제거할 수 있게 된다.The metallization method of the semiconductor device according to the present invention can remove the tungsten oxide remaining on the substrate after tungsten plugging and CMP by reducing gas or plasma treatment.
이하, 도면을 참조하여 본 발명의 반도체 소자의 금속배선 형성 방법을 상세히 설명하기로 한다.Hereinafter, a method of forming metal wirings of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 2d는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.
먼저, 도 2a에 도시한 바와 같이, 반도체 소자를 구성하기 위한 여러 가지 요소가 형성된 반도체 기판(201) 상에 제 1 절연막(202)을 형성하고, 상기 제 1 절연막(202)을 포함한 기판 전면상에 스퍼터링 공정을 이용하여 금속층을 증착한 다음, 선택적으로 패터닝하여 제 1 금속배선(203)을 형성한다.First, as shown in FIG. 2A, a first insulating film 202 is formed on a semiconductor substrate 201 in which various elements for constituting a semiconductor element are formed, and on the substrate front surface including the first insulating film 202. The metal layer is deposited using a sputtering process, and then selectively patterned to form the first metal wiring 203.
이어, 상기 제 1 금속배선(203)을 포함한 기판 전면상에 화학기상증착법을 이용하여 FSG막(204a)과 TEOS막(204b)을 차례로 증착하여 제 2 절연막(204)을 형성한다.Subsequently, the second insulating film 204 is formed by sequentially depositing the FSG film 204a and the TEOS film 204b on the entire surface of the substrate including the first metal wiring 203 by chemical vapor deposition.
상기 제 1 금속배선(203)의 소정 부위가 드러나도록 상기 FSG막(204a)과 TEOS막(204b)으로 구성되는 제 2 절연막(204)을 식각하여 비아 홀(205)을 형성한다. 이후, 상기 비아 홀(205)을 포함한 기판 전면상에 타이타늄과 같은 금속박막층을 형성한 후 열처리하여 타이탸늄/타이타늄 질화물의 이중층 구조를 갖는 확산 방지막(206)을 형성한다.The via hole 205 is formed by etching the second insulating film 204 including the FSG film 204a and the TEOS film 204b so that a predetermined portion of the first metal wiring 203 is exposed. Thereafter, a metal thin film layer such as titanium is formed on the entire surface of the substrate including the via hole 205 and then heat-treated to form a diffusion barrier 206 having a double layer structure of titanium / titanium nitride.
여기서, 상기 열처리는 급속 열처리 공정(RTP : Rapid Thermal Process)을 이용한다.Here, the heat treatment uses a rapid thermal process (RTP).
이어, 도 2b에 도시한 바와 같이, 상기 확산 방지막(206) 전면에 상기 비아 홀(205)을 충분히 채우도록 텅스텐 금속층(207)을 증착한 다음, 상기 제 2 절연막(204)이 드러나도록 상기 텅스텐 금속층(207) 및 확산방지막(206)을 CMP(Chemical Mechanical Polishing) 공정을 이용하여 연마한다.Subsequently, as shown in FIG. 2B, a tungsten metal layer 207 is deposited on the entire surface of the diffusion barrier 206 to sufficiently fill the via hole 205, and then the tungsten is exposed to expose the second insulating layer 204. The metal layer 207 and the diffusion barrier 206 are polished using a chemical mechanical polishing (CMP) process.
이 때, 상기 텅스텐 금속층(207)의 증착은 WF6가스를 사용한 물리적 기상증착법을 이용한다. 또한, 상기 확산 방지막(206)은 상기 WF6가스의 불소(F) 성분의 침투를 막아주는 역할을 한다.At this time, the deposition of the tungsten metal layer 207 uses a physical vapor deposition method using a WF 6 gas. In addition, the diffusion barrier 206 serves to prevent penetration of the fluorine (F) component of the WF 6 gas.
한편, 상기 FSG막(204a)과 TEOS막(204b)으로 구성되는 제 2 절연막(204)은 후속의 금속 배선의 열처리과정을 거치게 되면서, TEOS 막(204b) 내에 함유되어 있는 OH 성분이 FSG막(204a) 내부로 침투하여 FSG막(204a) 내의 불소(F)와 실리콘(Si)의 결합을 끊게 된다. 이 때, 결합에서 이탈한 불소(F) 성분은 상기 텅스텐 금속층의 CMP 공정 후 잔류하게 되는 텅스텐 산화물(도 2c의 208)로 집중하게 되어 텅스텐과 불소(F)의 화합물을 형성하게 되어 후술하는 금속배선에 영향을 미치게 된다.On the other hand, the second insulating film 204 composed of the FSG film 204a and the TEOS film 204b is subjected to a heat treatment process of a subsequent metal wiring, and the OH component contained in the TEOS film 204b is contained in the FSG film ( It penetrates into the inside of 204a and breaks the bond between fluorine (F) and silicon (Si) in the FSG film 204a. At this time, the fluorine (F) component separated from the bond is concentrated to the tungsten oxide (208 in Fig. 2c) remaining after the CMP process of the tungsten metal layer to form a compound of tungsten and fluorine (F) to be described later This will affect the wiring.
또한, 상기 텅스텐과 불소(F)의 화합물은 상기 타이타늄/타이타늄 질화물로 이루어진 확산 방지막(206)과 반응하여 타이타늄 플로라이드(TiF)를 형성한다. 이 타이타늄 플로라이드는 자체적으로 체적을 팽창시켜 비아 홀 내의 텅스텐 플러그(207)와 그 상부에 형성되는 금속배선을 뜯어내어 비아 홀과 금속배선의 접촉면에 공동(void)을 형성하거나 접촉의 저하로 인한 저항의 증가 및 단선을 유발하게 된다.In addition, the compound of tungsten and fluorine (F) reacts with the diffusion barrier 206 made of titanium / titanium nitride to form titanium fluoride (TiF). The titanium fluoride itself expands in volume to tear off the tungsten plug 207 in the via hole and the metal wiring formed thereon to form voids in the contact surface between the via hole and the metal wiring or due to a decrease in contact. It causes an increase in resistance and disconnection.
본 발명은 상기와 같은 텅스텐 산화물로 인해 야기되는 문제점을 제거하는데 특징이 있으며 그 과정은 다음과 같다.The present invention is characterized in eliminating the problems caused by the tungsten oxide as described above and the process is as follows.
도 2c에 도시한 바와 같이, 상기 텅스텐 플러그(207)를 포함한 기판 전면에 얇게 형성되어 있는 텅스텐 산화물(208)을 제거하기 위해 환원 가스를 불어넣어 주거나 플라즈마 처리를 한다.As shown in FIG. 2C, a reducing gas is blown or a plasma treatment is performed to remove the tungsten oxide 208 thinly formed on the entire surface of the substrate including the tungsten plug 207.
상기 환원 가스를 이용한 방법은 후술하는 금속배선을 증착 하기 전에 금속막을 증착하는 장비에 탈가스를 진행해 주는 챔버(chamber)를 장착한 다음, 탈가스 챔버 내에서 수소 환원 가스를 넣어 텅스텐 산화물을 제거하는 방법이다.The method using the reducing gas is equipped with a chamber for degassing the equipment for depositing a metal film before depositing the metal wiring to be described later, and then to remove the tungsten oxide by putting a hydrogen reducing gas in the degassing chamber. Way.
이 때, 챔버 내의 온도는 100∼400℃가 적당하며, 챔버 내의 가스 분위기는 헬륨(He), 아르곤(Ar) 또는 질소(N2) 가스 내에 5∼10% 정도의 수소 가스를 첨가하는 것이 바람직하다.At this time, the temperature in the chamber is suitable 100 ~ 400 ℃, the gas atmosphere in the chamber is preferably added to the hydrogen gas of about 5 to 10% in helium (He), argon (Ar) or nitrogen (N 2 ) gas. Do.
한편, 플라즈마를 이용한 방법은 금속배선을 증착하는 스퍼터링(sputtering) 장비 내에 텅스텐 산화물의 제거를 위한 RF(Radio Frequency) 프리클린(preclean) 챔버를 장착한 후, 수소 환원 가스를 불어 넣은 다음 플라즈마 처리로 텅스텐 산화물을 제거하는 방법이다.On the other hand, the plasma-based method is equipped with a RF (Radio Frequency) preclean chamber for removing tungsten oxide in a sputtering equipment for depositing metal wiring, and then blows hydrogen reduction gas into the plasma treatment. It is a method of removing tungsten oxide.
이 방법에서의 챔버 내 가스 분위기는 헬륨 또는 아르곤 가스 내에 5∼10% 정도의 수소 가스를 넣거나 또는 헬륨 가스 내에 5∼10% 정도의 수소 가스와 3∼5% 정도의 아르곤 가스를 넣은 것이며, 상기 혼합가스를 플라즈마 상태로 활성화하여 상기 텅스텐 산화물을 제거한다.The gas atmosphere in the chamber in this method is about 5 to 10% hydrogen gas in helium or argon gas or about 5 to 10% hydrogen gas and about 3 to 5% argon gas in helium gas. The tungsten oxide is removed by activating the mixed gas in a plasma state.
이어, 도 2d에 도시한 바와 같이, 상기 텅스텐 산화물이 제거된 상태에서 상기 텅스텐 플러그(207)를 포함한 기판 전면상에 제 2 금속배선 물질을 증착한 후 선택적으로 패터닝하여 제 2 금속배선(209)을 형성한다. 그 다음, 상기 제 2 금속배선(209)을 포함한 기판 전면상에 상기 제 2 절연막(204)과 마찬가지로 FSG막(210a)과 TEOS막(210b)으로 구성되는 제 3 절연막(210)을 형성하면 본 발명의 금속 배선 형성 방법은 완료된다.Subsequently, as shown in FIG. 2D, a second metal wiring material is deposited on the entire surface of the substrate including the tungsten plug 207 in the state where the tungsten oxide is removed, and then selectively patterned to form the second metal wiring 209. To form. Next, when the third insulating film 210 including the FSG film 210a and the TEOS film 210b is formed on the entire surface of the substrate including the second metal wiring 209, the second insulating film 204 is formed. The metal wiring formation method of this invention is completed.
상술한 바와 같은 본 발명의 반도체 소자의 금속배선 형성 방법은 다음과 같은 효과가 있다.The metal wiring forming method of the semiconductor device of the present invention as described above has the following effects.
텅스텐 플러깅과 CMP 후의 금속배선 증착 전에 환원가스 또는 플라즈마 처리를 통하여 잔류하는 텅스텐 산화물 제거함으로써 금속배선과 비아 홀의 접촉을 향상시켜 접촉 저항의 향상, 반도체 소자의 속도 증가 및 수율을 증대시킬 수 있다.By removing residual tungsten oxide through reducing gas or plasma treatment prior to tungsten plugging and deposition of metal wires after CMP, the contact between metal wires and via holes can be improved to improve contact resistance, increase speed of semiconductor devices, and increase yield.
Claims (7)
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| KR100442964B1 (en) * | 2001-12-31 | 2004-08-04 | 주식회사 하이닉스반도체 | Metal-Line formation Method of Semiconductor Device |
| KR100602088B1 (en) * | 2004-06-22 | 2006-07-14 | 동부일렉트로닉스 주식회사 | Formation method of metal line of semiconductor device |
| KR100766704B1 (en) * | 2005-09-28 | 2007-10-11 | 매그나칩 반도체 유한회사 | Method for fabricating semiconductor device |
| KR200452051Y1 (en) * | 2009-03-19 | 2011-01-28 | 여형구 | Fomentation heat dissipation system |
| CN113380693A (en) * | 2020-03-10 | 2021-09-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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| KR0163546B1 (en) * | 1995-12-18 | 1999-02-01 | 김광호 | Method of fabricating semiconductor device |
| KR100197535B1 (en) * | 1996-06-27 | 1999-06-15 | 김영환 | Forming method for metal wiring in semiconductor device |
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| KR100259692B1 (en) * | 1995-04-27 | 2000-06-15 | 가네꼬 히사시 | Semiconductor device manufacturing method having contact structure |
| KR0163546B1 (en) * | 1995-12-18 | 1999-02-01 | 김광호 | Method of fabricating semiconductor device |
| KR100197535B1 (en) * | 1996-06-27 | 1999-06-15 | 김영환 | Forming method for metal wiring in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100442964B1 (en) * | 2001-12-31 | 2004-08-04 | 주식회사 하이닉스반도체 | Metal-Line formation Method of Semiconductor Device |
| KR100602088B1 (en) * | 2004-06-22 | 2006-07-14 | 동부일렉트로닉스 주식회사 | Formation method of metal line of semiconductor device |
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| KR200452051Y1 (en) * | 2009-03-19 | 2011-01-28 | 여형구 | Fomentation heat dissipation system |
| CN113380693A (en) * | 2020-03-10 | 2021-09-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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