KR20010001601A - 반도체 장치 및 그 제조방법 - Google Patents
반도체 장치 및 그 제조방법 Download PDFInfo
- Publication number
- KR20010001601A KR20010001601A KR1019990020942A KR19990020942A KR20010001601A KR 20010001601 A KR20010001601 A KR 20010001601A KR 1019990020942 A KR1019990020942 A KR 1019990020942A KR 19990020942 A KR19990020942 A KR 19990020942A KR 20010001601 A KR20010001601 A KR 20010001601A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- pcb substrate
- chip
- semiconductor
- hole
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 160
- 238000004519 manufacturing process Methods 0.000 title description 10
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 239000003822 epoxy resin Substances 0.000 claims abstract description 19
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 19
- 229910000679 solder Inorganic materials 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 230000008054 signal transmission Effects 0.000 claims description 2
- 239000004593 Epoxy Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (8)
- 제1 반도체칩과;상기 제1 반도체칩의 일면에 한쪽으로 위치되도록 플립 칩 본딩에 의해 실장되는 제2 반도체칩과;상기 제2 반도체칩이 위치될 수 있는 관통홀이 형성되고, 이 관통홀의 외측부에 상기 제1 반도체칩이 플립 칩 본딩에 의해 실장되는 PCB 기판과;상기 제1 반도체칩과 제2 반도체칩 그리고 PCB 기판 간에 상호 신호 전달이 되도록 하는 도전체와;상기 도전체를 외부의 환경으로부터 보호하기 위하여 감싼 에폭시 수지와;상기 제1 반도체칩과 제2 반도체칩의 신호를 PCB 기판을 통하여 외부로 입출력하도록 상기 PCB 기판의 저면에 융착된 솔더볼을 포함하여서 된 반도체 장치.
- 제 1 항에 있어서,상기 PCB 기판에 형성되는 관통홀의 내측벽과, 제1 반도체칩에 실장되는 제2 반도체칩과의 사이 간격은 2mm 이내의 간격으로 유지되도록 된 반도체 장치.
- 제1 반도체칩의 일면에 제2 반도체칩을 한쪽으로 위치하도록 플립 칩 본딩에 의해 실장하는 단계와;PCB 기판의 관통홀에 제2 반도체칩이 위치하도록 제2 반도체칩이 실장되어 있는 제1 반도체칩을 플립 칩 본딩에 의해 실장하는 단계와;상기 제1 반도체칩에 실장된 제2 반도체칩의 플립 칩 본딩부와 PCB 기판에 실장되는 제1 반도체칩의 플립 칩 본딩부를 에폭시 수지로 한 번 디스펜싱하는 것에 의해서 동시에 봉지하는 단계와;상기 제1 반도체칩과 제2 반도체칩의 신호를 상기 PCB 기판을 통하여 외부로 입출력하도록 상기 PCB 기판의 저면에 솔더볼을 융착하는 단계를, 포함하여서 이루어지는 반도체 장치의 제조방법.
- 제 3 항에 있어서,상기 PCB 기판의 관통홀에 위치하는 제2 반도체칩은 상기 관통홀의 내측벽과 2mm 이내의 간격이 유지되도록 하는 반도체 장치의 제조방법.
- 제 4 항에 있어서,상기 간격은 관통홀의 내측벽을 제2 반도체칩 측으로 연장하여서 유지되도록 하는 반도체 장치의 제조방법.
- 관통홀이 형성된 PCB 기판에 제1 반도체칩을 플립 칩 본딩에 의해 실장하는 단계와,상기 PCB 기판의 관통홀을 통해 상기 제1 반도체칩의 일면에 제2 반도체칩을 상기 관통홀의 내측으로 위치하도록 플립 칩 본딩에 의해 실장하는 단계와;상기 PCB 기판에 실장된 제1 반도체칩의 플립 칩 본딩부와 상기 제1 반도체칩에 실장된 제2 반도체칩의 플립 칩 본딩부를 에폭시 수지로 한 번 디스펜싱하는 것에 의해서 동시에 봉지하는 단계와;상기 제1 반도체칩과 제2 반도체칩의 신호를 상기 PCB 기판을 통하여 외부로 입출력하도록 상기 PCB 기판의 저면에 솔더볼을 융착하는 단계를, 포함하여서 이루어지는 반도체 장치의 제조방법.
- 제 6 항에 있어서,상기 PCB 기판의 관통홀을 통해 제1 반도체칩에 실장되는 제2 반도체칩은 상기 관통홀의 내측벽과 2mm 이내의 간격이 유지되도록 실장하는 반도체 장치의 제조방법.
- 제 7 항에 있어서,상기 간격은 제2 반도체칩을 PCB 기판에 형성되는 관통홀의 내측벽 쪽으로 밀착해서 실장함으로서 유지되도록 하는 반도체 장치의 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019990020942A KR100364979B1 (ko) | 1999-06-07 | 1999-06-07 | 반도체 장치 및 그 제조방법 |
Applications Claiming Priority (1)
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KR1019990020942A KR100364979B1 (ko) | 1999-06-07 | 1999-06-07 | 반도체 장치 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
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KR20010001601A true KR20010001601A (ko) | 2001-01-05 |
KR100364979B1 KR100364979B1 (ko) | 2002-12-16 |
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KR1019990020942A KR100364979B1 (ko) | 1999-06-07 | 1999-06-07 | 반도체 장치 및 그 제조방법 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100673378B1 (ko) * | 1999-12-17 | 2007-01-23 | 삼성전자주식회사 | 칩 스케일 적층 칩 패키지와 그 제조 방법 |
KR100840788B1 (ko) * | 2006-12-05 | 2008-06-23 | 삼성전자주식회사 | 칩 적층 패키지 및 그 제조 방법 |
-
1999
- 1999-06-07 KR KR1019990020942A patent/KR100364979B1/ko not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100673378B1 (ko) * | 1999-12-17 | 2007-01-23 | 삼성전자주식회사 | 칩 스케일 적층 칩 패키지와 그 제조 방법 |
KR100840788B1 (ko) * | 2006-12-05 | 2008-06-23 | 삼성전자주식회사 | 칩 적층 패키지 및 그 제조 방법 |
Also Published As
Publication number | Publication date |
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KR100364979B1 (ko) | 2002-12-16 |
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