KR20000075883A - 집적 회로 칩과 코일을 동시 실장시킨 집적 회로 패키지 및 그 제조 방법 - Google Patents

집적 회로 칩과 코일을 동시 실장시킨 집적 회로 패키지 및 그 제조 방법 Download PDF

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Publication number
KR20000075883A
KR20000075883A KR1019997007962A KR19997007962A KR20000075883A KR 20000075883 A KR20000075883 A KR 20000075883A KR 1019997007962 A KR1019997007962 A KR 1019997007962A KR 19997007962 A KR19997007962 A KR 19997007962A KR 20000075883 A KR20000075883 A KR 20000075883A
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KR
South Korea
Prior art keywords
package
coil
chip
substrate layer
lead
Prior art date
Application number
KR1019997007962A
Other languages
English (en)
Korean (ko)
Inventor
죠셉 디. 페르난데즈
Original Assignee
씨. 필립 채프맨
마이크로칩 테크놀로지 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 씨. 필립 채프맨, 마이크로칩 테크놀로지 인코포레이티드 filed Critical 씨. 필립 채프맨
Publication of KR20000075883A publication Critical patent/KR20000075883A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1019997007962A 1998-01-09 1999-01-08 집적 회로 칩과 코일을 동시 실장시킨 집적 회로 패키지 및 그 제조 방법 KR20000075883A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US506098A 1998-01-09 1998-01-09
US9/005,060 1998-01-09

Publications (1)

Publication Number Publication Date
KR20000075883A true KR20000075883A (ko) 2000-12-26

Family

ID=21713950

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019997007962A KR20000075883A (ko) 1998-01-09 1999-01-08 집적 회로 칩과 코일을 동시 실장시킨 집적 회로 패키지 및 그 제조 방법

Country Status (3)

Country Link
JP (1) JP2001515661A (fr)
KR (1) KR20000075883A (fr)
WO (1) WO1999035691A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101038490B1 (ko) * 2004-02-23 2011-06-01 삼성테크윈 주식회사 Ｒｆｉｄ용 안테나 내장형 반도체 패키지

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2796760B1 (fr) * 1999-07-23 2002-02-01 Gemplus Card Int Etiquette electronique et procede pour sa fabrication
JP4012733B2 (ja) 1999-09-20 2007-11-21 フラクトゥス・ソシエダッド・アノニマ マルチレベルアンテナ
US6424263B1 (en) * 2000-12-01 2002-07-23 Microchip Technology Incorporated Radio frequency identification tag on a single layer substrate
EP1563570A1 (fr) 2002-11-07 2005-08-17 Fractus, S.A. Boitier de circuit integre incluant une antenne miniature
EP1562272B1 (fr) * 2004-01-14 2016-09-07 Dehn + Söhne Gmbh + Co. Kg Ensemble pour le contrôle et l'enregistrement de l'état d'un dispositif de protection contre les surtensions, en particulier pour installation dans des réseaux à basse tension ou systèmes d'information.
EP1771919A1 (fr) 2004-07-23 2007-04-11 Fractus, S.A. Antenne dans un boitier a interaction electromagnetique reduite avec des elements integres sur la puce
WO2006059732A1 (fr) 2004-12-03 2006-06-08 Hallys Corporation Dispositif de collage d’élément d’interposition
EP1876877B1 (fr) 2005-04-06 2010-08-25 Hallys Corporation Appareil de fabrication de composant electronique
KR100746635B1 (ko) 2006-03-21 2007-08-06 삼성전기주식회사 Ｒｆｉｄ 시스템의 태그 및 그 제조 방법
US9818694B2 (en) * 2015-11-16 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Active atomic reservoir for enhancing electromigration reliability in integrated circuits
US10950540B2 (en) 2015-11-16 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Enhancing integrated circuit density with active atomic reservoir
US9929087B2 (en) 2015-11-16 2018-03-27 Taiwan Semiconductor Manufacturing Co., Ltd Enhancing integrated circuit density with active atomic reservoir
CN110010509B (zh) * 2018-01-05 2023-10-20 光宝新加坡有限公司 双引线架磁耦合封装结构及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04325293A (ja) * 1991-04-25 1992-11-13 Mitsubishi Electric Corp 非接触ｉｃカード
JP3305843B2 (ja) * 1993-12-20 2002-07-24 株式会社東芝 半導体装置
FR2721733B1 (fr) * 1994-06-22 1996-08-23 Gemplus Card Int Procédé de fabrication d'une carte sans contact par surmoulage et carte sans contact obtenue par un tel procédé.
KR100355209B1 (ko) * 1994-09-22 2003-02-11 로무 가부시키가이샤 비접촉형ic카드및그제조방법
JPH091970A (ja) * 1995-06-20 1997-01-07 Hitachi Chem Co Ltd Ｉｃカード及びその製造法
FR2743649B1 (fr) * 1996-01-17 1998-04-03 Gemplus Card Int Module electronique sans contact, carte etiquette electronique l'incorporant, et leurs procedes de fabrication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101038490B1 (ko) * 2004-02-23 2011-06-01 삼성테크윈 주식회사 Ｒｆｉｄ용 안테나 내장형 반도체 패키지

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Publication number Publication date
WO1999035691A1 (fr) 1999-07-15
JP2001515661A (ja) 2001-09-18

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