KR20000055319A - Circuit for driving lower word line - Google Patents

Circuit for driving lower word line Download PDF

Info

Publication number
KR20000055319A
KR20000055319A KR1019990003885A KR19990003885A KR20000055319A KR 20000055319 A KR20000055319 A KR 20000055319A KR 1019990003885 A KR1019990003885 A KR 1019990003885A KR 19990003885 A KR19990003885 A KR 19990003885A KR 20000055319 A KR20000055319 A KR 20000055319A
Authority
KR
South Korea
Prior art keywords
word line
nmos transistor
lower word
signal
level
Prior art date
Application number
KR1019990003885A
Other languages
Korean (ko)
Inventor
정정수
Original Assignee
김영환
현대반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체 주식회사 filed Critical 김영환
Priority to KR1019990003885A priority Critical patent/KR20000055319A/en
Publication of KR20000055319A publication Critical patent/KR20000055319A/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE: An apparatus for driving a sub wordline is provided to reduce a layout area by using a low voltage NMOS transistor for a driver, to improve driving capability and speed and to increase the reliability of access timing. CONSTITUTION: An apparatus for driving a sub wordline is composed of a low voltage NMOS(LN) and an NMOS transistor(MN). A main wordline driving signal(MWL) and a sub wordline decoding signal are supplied to the gate and drain of the low voltage NMOS(LN) respectively. A main wordline driving signal(MWLB) is supplied to the gate of the NMOS transistor(MN). The source of the NMOS transistor(MN) is grounded. The drain of the NMOS transistor(MN) outputs a sub wordline driving signal(SWL) in common with the source of the low voltage NMOS(LN).

Description

하부워드라인구동장치{Circuit for driving lower word line}Circuit for driving lower word line}

본 발명은 하부워드라인구동장치에 관한 것으로서, 특히 구동용 트랜지스터로 Low Vt NMOS트랜지스터를 사용한 것이 특징인 하부워드라인구동장치에 관한 것이다.The present invention relates to a lower word line driving apparatus, and more particularly, to a lower word line driving apparatus characterized by using a low Vt NMOS transistor as a driving transistor.

도 1은 종래의 NMOS승압형 하부워드라인구동장치의 회로도 및 타이밍도이다.1 is a circuit diagram and a timing diagram of a conventional NMOS boosted lower word line driver.

상기 종래의 NMOS형 하부워드라인구동장치는 제 1, 제 2 및 제 3 NMOS트랜지스터(MN1,MN2,MN3)를 가진다.The conventional NMOS lower word line driver has first, second and third NMOS transistors MN1, MN2 and MN3.

상기 제 1 NMOS트랜지스터(MN1)의 게이트에는 기준전압(Vboot)이 인가되고 드레인에는 메인워드라인구동신호(MWL)가 인가된다.The reference voltage Vboot is applied to the gate of the first NMOS transistor MN1 and the main word line driving signal MWL is applied to the drain.

상기 제 2 NMOS트랜지스터(MN2)의 게이트는 상기 제 1 NMOS트랜지스터(MN1)의 소오스와 연결되고 소오스에는 하부워드라인 디코딩신호(FX)가 인가된다.A gate of the second NMOS transistor MN2 is connected to a source of the first NMOS transistor MN1, and a lower word line decoding signal FX is applied to the source.

상기 제 3 NMOS트랜지스터(MN3)의 게이트에는 반전된메인워드라인구동신호(MWLB)가 인가되고 소오스는 접지와 연결되며 드레인은 상기 제 2 NMOS트랜지스터(MN2)의 드레인과 공통으로 하부워드라인구동신호(SWL)를 출력한다. 반전된메인워드라인구동신호(MWLB)는 메인워드라인구동신호(MWL)의 반전된 신호이고, 반전된메인워드라인구동신호(MWLB)과 메인워드라인구동신호(MWLB)은 워드라인 페어를 이룬다.An inverted main word line drive signal MWLB is applied to the gate of the third NMOS transistor MN3, a source is connected to ground, and a drain is a lower word line drive signal in common with the drain of the second NMOS transistor MN2. Outputs (SWL). The inverted main word line drive signal MWLB is an inverted signal of the main word line drive signal MWL, and the inverted main word line drive signal MWLB and the main word line drive signal MWLB form a word line pair. .

상기 종래의 NMOS승압형 하부워드라인구동장치는 다음과 같이 동작한다.The conventional NMOS boosted lower word line driver operates as follows.

시간 t0 에서:At time t0:

메인워드라인구동신호(MWL)가 'VSS'래밸 일 때 반전된 메인워드라인구동신호(MWLB)는 'VCC'래밸로 인가된다.When the main word line drive signal MWL is 'VSS' level, the inverted main word line drive signal MWLB is applied to the 'VCC' level.

그러면 상기 제 1 NMOS트랜지스터(MN1)는 그 게이트에 기준전압이 인가되고 있으므로 '온' 되고, 제 2 NMOS트랜지스터(MN2)는 그 게이트에 VSS가 인가되고 있으므로 '오프' 되고, 상기 제 3 NMOS트랜지스터(MN3)는 '온'되어 'VSS' 래밸이 하부워드라인구동신호(SWL)로 출력된다.Then, the first NMOS transistor MN1 is 'on' because a reference voltage is applied to the gate thereof, and the second NMOS transistor MN2 is 'off' because VSS is applied to the gate thereof, and the third NMOS transistor MN1 is turned off. MN3 is 'ON' so that the 'VSS' level is output as the lower word line drive signal SWL.

시간 t1에서 ;At time t1;

메인워드라인구동신호(MWL)가 'VCC' 래밸로 변화되면 반전된 메인워드라인구동신호(MWLB)는 'VSS'래밸로 변화되고, 하부워드라인 디코딩신호(FX)가 'VPP' 래밸로 인가된다.When the main word line drive signal (MWL) is changed to the 'VCC' level, the inverted main word line drive signal (MWLB) is changed to the 'VSS' level, and the lower word line decode signal (FX) is applied to the 'VPP' level. do.

그러면 상기 제 1 NMOS트랜지스터(MN1)가 온 되어 제 2 NMOS트랜지스터(MN2)가 '온' 되고, 상기 제 3 NMOS트랜지스터(MN3)는 '오프'되어 하부워드라인 디코딩신호(FX)의 'VPP'래밸이 하부워드라인구동신호(SWL)로 출력된다.Then, the first NMOS transistor MN1 is turned on, and the second NMOS transistor MN2 is turned on, and the third NMOS transistor MN3 is turned off to be VPP of the lower word line decoding signal FX. The level is output as the lower word line drive signal SWL.

시간 t2에서 ;At time t2;

메인워드라인구동신호(MWL)가 'VCC' 래밸 일 때 반전된 메인워드라인구동신호(MWLB)는 'VSS'래밸로 인가되고, 하부워드라인디코딩신호(FX)가 'VSS' 래밸로 인가된다.When the main word line drive signal MWL is the 'VCC' level, the inverted main word line drive signal MWLB is applied to the 'VSS' level and the lower word line decoding signal FX is applied to the 'VSS' level. .

그러면 상기 제 1 NMOS트랜지스터(MN1)와 제 2 NMOS트랜지스터(MN2)는 '온' 되고, 상기 제 3 NMOS트랜지스터(MN3)는 '오프'되어 하부워드라인디코딩신호(FX)의 'VSS'래밸이 하부워드라인구동신호(SWL)로 출력된다.Then, the first NMOS transistor MN1 and the second NMOS transistor MN2 are 'on', and the third NMOS transistor MN3 is 'off' so that the 'VSS' level of the lower word line decoding signal FX is obtained. The lower word line driving signal SWL is output.

상기 종래의 NMOS승압형 하부워드라인구동장치의 동작을 물리적인면에서 보면 메인워드라인구동신호(MWL)가 'VCC' 래밸이 되면 제 1 NMOS트랜지스터(MN1)이 '온'되어 제 2 NMOS트랜지스터(MN2)의 게이트의 레밸이 상승하고 그 레밸이 기준전압(Vboot)+Vt가 되면 제 1 NMOS트랜지스터(MN1)이 '오프'되고 제 2 NMOS트랜지스터(MN2)의 게이트는 부동(Floating)상태에 있게 되고, 하부워드라인디코딩신호(FX)가 'VPP' 레밸로 되면 상기 제 2 NMOS트랜지스터(MN2)의 게이트도 기준전압(Vboot)+Vt이상으로 부동(Floating)상태가 되어 제 2 NMOS트랜지스터(MN2)의 Vt 전압강하없이 상기 인가되는 하부워드라인디코딩신호(FX)의 'VPP' 레밸을 하부워드라인구동신호(SWL)로 출력할 수 있게 된다.Referring to the operation of the conventional NMOS step-up lower word line driving device in physical terms, when the main word line driving signal MWL becomes 'VCC' level, the first NMOS transistor MN1 is 'on' and the second NMOS transistor ( When the level of the gate of MN2 rises and the level reaches the reference voltage Vboot + Vt, the first NMOS transistor MN1 is 'off' and the gate of the second NMOS transistor MN2 is in a floating state. When the lower word line decoding signal FX reaches the 'VPP' level, the gate of the second NMOS transistor MN2 also floats above the reference voltage Vboot + Vt, thereby causing the second NMOS transistor MN2. It is possible to output the 'VPP' level of the applied lower word line decoding signal FX as the lower word line driving signal SWL without a voltage drop of Vt.

도 2는 다른 예의 종래 CMOS형 하부워드라인 구동장치의 회로도 및 타이밍도이다.2 is a circuit diagram and a timing diagram of another conventional CMOS type lower word line driver.

상기 종래의 CMOS형 하부워드라인 구동장치는 제 1, 제 2 NMOS트랜지스터(MN1,MN2,) 및 제 1 PMOS트랜지스터(MP1)를 가진다.The conventional CMOS type lower word line driver has first and second NMOS transistors MN1 and MN2 and a first PMOS transistor MP1.

제 1 PMOS트랜지스터(MP1)의 게이트에는 반전된메인워드라인 구동신호(MWLB)가 인가되고 소오스에는 하부워드라인 디코딩신호(FX)가 인가되며 드레인은 하부워드라인구동신호(SWL)를 출력한다.The inverted main word line driving signal MWLB is applied to the gate of the first PMOS transistor MP1, the lower word line decoding signal FX is applied to the source, and the drain outputs the lower word line driving signal SWL.

제 1 NMOS트랜지스터(MN1)의 게이트에는 반전된메인워드라인 구동신호(MWLB)가 인가되고 소오스는 접지와 연결되며 드레인은 제 1 PMOS트랜지스터(MP1)의 드레인과 공통으로 하부워드라인구동신호(SWL)를 출력한다.The inverted main word line driving signal MWLB is applied to the gate of the first NMOS transistor MN1, the source is connected to ground, and the drain is the lower word line driving signal SWL in common with the drain of the first PMOS transistor MP1. )

제 2 NMOS트랜지스터(MN2)의 게이트는 메인워드라인구동신호(MWL)가 인가되고 소오스에는 소오스에는 하부워드라인디코딩신호(FX)가 인가되며 드레인은 제 1 PMOS트랜지스터(MP1)의 드레인과 공통으로 하부워드라인구동신호(SWL)를 출력한다.The main word line driving signal MWL is applied to the gate of the second NMOS transistor MN2, the lower word line decoding signal FX is applied to the source, and the drain is common with the drain of the first PMOS transistor MP1. The lower word line driving signal SWL is output.

종래의 CMOS형 하부워드라인구동장치는 다음과 같이 구동된다.The conventional CMOS type lower word line driver is driven as follows.

t0 ∼ t1 ;t0 to t1;

메인워드라인구동신호(MWL)가 'VSS'래밸 일 때 반전된 메인워드라인구동신호(MWLB)는 'VPP'래밸로 인가된다.When the main word line drive signal MWL is 'VSS' level, the inverted main word line drive signal MWLB is applied to the 'VPP' level.

그러면 상기 제 1 NMOS트랜지스터(MN1)는 '온' 되고 상기 제 1 PMOS트랜지스터(MP1) 및 제 2 NMOS트랜지스터(MN2)는 '오프'되어 'VSS'래밸이 하부워드라인구동신호(SWL)로 출력된다.Then, the first NMOS transistor MN1 is 'on' and the first PMOS transistor MP1 and the second NMOS transistor MN2 are 'off' so that the 'VSS' level is output as the lower word line driving signal SWL. do.

t1 ∼ t2 ;t1 to t2;

메인워드라인구동신호(MWL)가 '하이'래밸 일 때 반전된 메인워드라인구동신호(MWLB)는 'VSS'래밸로 인가되고, 하부워드라인 디코딩신호(FX)가 'VPP'래밸로 인가된다.When the main word line drive signal MWL is high, the inverted main word line drive signal MWLB is applied to the VSS level, and the lower word line decoding signal FX is applied to the VPP level. .

그러면 상기 제 1 PMOS트랜지스터(MP1)와 제 2 NMOS트랜지스터(MN2)는 '온' 되고, 상기 제 1 NMOS트랜지스터(MN1)는 '오프'되어 하부워드라인디코딩신호(FX)의 'VPP'래밸이 하부워드라인구동신호(SWL)로 출력된다.Then, the first PMOS transistor MP1 and the second NMOS transistor MN2 are 'on', and the first NMOS transistor MN1 is 'off' so that the 'VPP' level of the lower word line decoding signal FX is obtained. The lower word line driving signal SWL is output.

t2 ∼ t3 ;t2 to t3;

메인워드라인구동신호(MWL)가 '하이'래밸 일 때 반전된 메인워드라인 구동신호(MWLB)는 'VSS'래밸로 인가되고, 하부워드라인디코딩신호(FX)가 'VSS'래밸로 인가된다.When the main word line drive signal MWL is high, the inverted main word line drive signal MWLB is applied to the VSS level, and the lower word line decoding signal FX is applied to the VSS level. .

그러면 상기 제 1 PMOS트랜지스터(MP1)와 제 2 NMOS트랜지스터(MN2)는 '온' 되고, 상기 제 1 NMOS트랜지스터(MN1)는 '오프'되어 하부워드라인디코딩신호(FX)의 'VSS'래밸이 하부워드라인구동신호(SWL)로 출력된다.Then, the first PMOS transistor MP1 and the second NMOS transistor MN2 are 'on', and the first NMOS transistor MN1 is 'off' so that the 'VSS' level of the lower word line decoding signal FX is obtained. The lower word line driving signal SWL is output.

그러나, 상기 종래의 NMOS승압형 하부워드라인구동장치는 워드라인을 구동시키기위하여 승압을 하여야하므로 Access timing의 지연과 신뢰성이 떨어지며, CMOS형 하부워드라인 구동장치는 CMOS트랜지스터와 NMOS트랜지스터를 같이 사용하므로 웰(WELL)의 분리로 인한 레이아웃면적의 증가와 구동능력의 저하를 가져오는 문제점을 가진다.However, the conventional NMOS step-up lower word line driver has to be stepped up to drive a word line, so the delay and reliability of access timing are inferior, and the CMOS type lower word line driver uses a CMOS transistor and an NMOS transistor together. There is a problem that the layout area is increased and the driving ability is lowered due to separation of the well.

본 발명은 상술한 종래 장치의 문제점을 해결하기 위하여 안출된 것으로서, Low Vt NMOS트랜지스터를 구동용 드라이버에 사용하여 레이아웃면적을 줄이고 구동능력 및 속도를 개선 할 수 있으며 Access timing의 신뢰성을 향상시키는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional apparatus described above, and uses a Low Vt NMOS transistor in a driver for driving to reduce layout area, improve driving capability and speed, and improve access timing reliability.

도 1 종래의 NMOS승압형 하부워드라인구동장치의 회로도 및 타이밍도1 is a circuit diagram and a timing diagram of a conventional NMOS boosted lower word line driver.

도 2 종래의 CMOS형 하부워드라인구동장치의 회로도 및 타이밍도2 is a circuit diagram and a timing diagram of a conventional CMOS type lower word line driver.

도 3 본 발명에 따른 하부워드라인구동장치의 회로도 및 타이밍도3 is a circuit diagram and a timing diagram of a lower word line driving apparatus according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

MWL : 메인워드라인구동신호MWL: Main word line drive signal

MWLB : 반전된메인워드라인구동신호MWLB: Inverted main word line drive signal

FX : 하부워드라인디코딩신호FX: Lower word line decoding signal

SWL : 하부워드라인구동신호SWL: Lower word line drive signal

이하 도면을 참고하여 본 발명에 따른 하부워드라인구동장치의 구성과 동작을 설명한다.Hereinafter, the configuration and operation of the lower word line driving apparatus according to the present invention will be described with reference to the drawings.

도 3은 본 발명에 따른 하부워드라인구동장치의 회로도 및 타이밍도이다.3 is a circuit diagram and a timing diagram of the lower word line driving apparatus according to the present invention.

상기 본 발명에 따른 하부워드라인구동장치는 게이트에는 메인워드라인구동신호(MWL)가 인가되고 드레인에는 하부워드라인디코딩신호(FX)가 인가되는 Low Vt NMOS트랜지스터(LN)와,The lower word line driver according to the present invention includes a low Vt NMOS transistor (LN) to which a main word line drive signal (MWL) is applied to a gate and a lower word line decoding signal (FX) is applied to a drain;

게이트에는 반전된 메인워드라인구동신호(MWLB)가 인가되고 소오스는 접지와 연결되며 드레인은 상기 Low Vt NMOS트랜지스터(LN)의 소오스와 공통으로 하부워드라인구동신호(SWL)를 출력하는 NMOS트랜지스터(MN)로 구성된다.An inverted main word line drive signal MWLB is applied to a gate, a source is connected to ground, and a drain thereof outputs a lower word line drive signal SWL in common with the source of the Low Vt NMOS transistor LN. MN).

상기 본 발명에 따른 하부워드라인구동장치는 다음과 같이 동작한다.The lower word line driving apparatus according to the present invention operates as follows.

t0 ∼ t1 ;t0 to t1;

메인워드라인구동신호(MWL)가 '로우'래밸 일 때 반전된 메인워드라인구동신호(MWLB)는 '하이'래밸로 인가된다.When the main word line drive signal MWL is 'low' level, the inverted main word line drive signal MWLB is applied to the 'high' level.

그러면 상기 Low Vt NMOS트랜지스터(LN)는 '오프' 되고 NMOS트랜지스터(MN)는 '온' 되어 'VSS'래밸이 하부워드라인구동신호(SWL)로 출력된다.Then, the Low Vt NMOS transistor LN is 'off' and the NMOS transistor MN is 'on' so that the 'VSS' level is output as the lower word line driving signal SWL.

t1 ∼ t2 ;t1 to t2;

메인워드라인구동신호(MWL)가 '하이'래밸로 변화되고 반전된 메인워드라인구동신호(MWLB)는 '로우'래밸로 변화되고, 하부워드라인 디코딩신호(FX)가 'VPP'래밸로 인가되면, Low Vt NMOS트랜지스터(LN)는 '온' 되고 NMOS트랜지스터(MN)는 '오프' 되어 하부워드라인 디코딩신호(FX)의 'VPP'래밸이 하부워드라인구동신호(SWL)로 출력된다.The main word line drive signal (MWL) is changed to 'high' level and the inverted main word line drive signal (MWLB) is changed to 'low' level and the lower word line decode signal (FX) is applied to 'VPP' level. When the low Vt NMOS transistor LN is 'on' and the NMOS transistor MN is 'off', the 'VPP' level of the lower word line decoding signal FX is output as the lower word line driving signal SWL.

t2 ∼ ;t2-;

메인워드라인구동신호(MWL)가 '하이'래밸 일 때 반전된 메인워드라인 구동신호(MWLB)는 'VSS'래밸로 인가되고, 하부워드라인 디코딩신호(FX)가 'VSS'래밸로 변화되면, Low Vt NMOS트랜지스터(LN)는 '온' 되고 NMOS트랜지스터(MN)는 '오프' 되어 하부워드라인 디코딩신호(FX)의 'VSS'래밸이 하부워드라인구동신호(SWL)로 출력된다.When the main word line driving signal MWL is high, the inverted main word line driving signal MWLB is applied to the VSS level, and the lower word line decoding signal FX is changed to the VSS level. The low Vt NMOS transistor LN is 'on' and the NMOS transistor MN is 'off' so that the 'VSS' level of the lower word line decoding signal FX is output as the lower word line driving signal SWL.

또한 메인워드라인구동신호(MWL)와 하부워드라인 디코딩신호(FX)가 모두 '하이'가 되어 하부워드라인구동신호(SWL)로 '하이'래밸이 출력될 때 생기는 전압강하는 Low Vt NMOS트랜지스터(LN)를 사용하였기에 크지않으며 메인워드라인구동신호(MWL)와 하부워드라인 디코딩신호(FX)의 구동전압을 Low Vt NMOS트랜지스터(LN)의 구동전압만큼약간만 상승된 래밸을 공급하여 극복할 수 있다.In addition, when the main word line driving signal (MWL) and the lower word line decoding signal (FX) are both 'high', the voltage drop generated when the 'high' level is output to the lower word line driving signal (SWL) is a low Vt NMOS transistor. (LN) is not large, and the driving voltage of the main word line driving signal (MWL) and the lower word line decoding signal (FX) can be overcome by supplying a level that is raised slightly by the driving voltage of the Low Vt NMOS transistor (LN). have.

또한 대기상태에서는 Low Vt NMOS트랜지스터(LN)가 일반적인 NMOS트랜지스터와 비교하여 더많은 누설전류(leakage)가 많은 것은 메인워드라인구동신호(MWL)의 '로우'래밸을 접지래밸보다 더낮은 VBB(Backbias)래밸로 만들어주어 누설전류(leakage)를 줄일 수 있다.Also, the low Vt NMOS transistor (LN) has a higher leakage current compared to the general NMOS transistor in the standby state, so that the 'low' level of the main word line drive signal (MWL) is lower than the ground level. Ravel can be used to reduce leakage.

따라서, 본 발명에 따른 하부워드라인 구동장치는 Low Vt NMOS트랜지스터를 드라이버에 사용하여 CMOS형 하부워드라인 구동장치의 단점인 넓은 레이아웃면적 구동능력 및 속도를 개선 할 수 있으며 NMOS형 하부워드라인 구동장치의 단점인 Access timing의 지연, 속도, 레이아웃면적 및 신뢰성을 향상시킬 수 있다.Therefore, the lower word line driving apparatus according to the present invention can improve the driving capacity and speed of a large layout area, which is a disadvantage of the CMOS lower word line driving apparatus by using a low Vt NMOS transistor as a driver, and the NMOS lower word line driving apparatus. It can improve the delay, speed, layout area and reliability of Access timing.

Claims (1)

게이트에는 메인워드라인구동신호(MWL)가 인가되고 드레인에는 하부워드라인디코딩신호(FX)가 인가되는 Low Vt NMOS트랜지스터(LN)와,A low Vt NMOS transistor LN to which a main word line driving signal MWL is applied to a gate and a lower word line decoding signal FX to a drain; 게이트에는 반전된 메인워드라인구동신호(MWLB)가 인가되고 소오스는 접지와 연결되며 드레인은 상기 Low Vt NMOS트랜지스터(LN)의 소오스와 연결되어 이 접속점으로부터 하부워드라인구동신호(SWL)를 출력하는 NMOS트랜지스터(MN)로 구성된 것이 특징인 하부워드라인구동장치.The inverted main word line drive signal MWLB is applied to the gate, the source is connected to ground, and the drain is connected to the source of the Low Vt NMOS transistor LN to output the lower word line drive signal SWL from this connection point. Lower word line drive device characterized by consisting of NMOS transistor (MN).
KR1019990003885A 1999-02-05 1999-02-05 Circuit for driving lower word line KR20000055319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990003885A KR20000055319A (en) 1999-02-05 1999-02-05 Circuit for driving lower word line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990003885A KR20000055319A (en) 1999-02-05 1999-02-05 Circuit for driving lower word line

Publications (1)

Publication Number Publication Date
KR20000055319A true KR20000055319A (en) 2000-09-05

Family

ID=19573446

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990003885A KR20000055319A (en) 1999-02-05 1999-02-05 Circuit for driving lower word line

Country Status (1)

Country Link
KR (1) KR20000055319A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120790A (en) * 1992-10-02 1994-04-28 Nec Ic Microcomput Syst Ltd Standby flag circuit
KR970051271A (en) * 1995-12-29 1997-07-29 김주용 Buro decoder circuit
KR970051195A (en) * 1995-12-08 1997-07-29 김주용 Lower word line driver circuit and semiconductor memory device using same
KR19980021468A (en) * 1996-09-17 1998-06-25 문정환 Semiconductor memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120790A (en) * 1992-10-02 1994-04-28 Nec Ic Microcomput Syst Ltd Standby flag circuit
KR970051195A (en) * 1995-12-08 1997-07-29 김주용 Lower word line driver circuit and semiconductor memory device using same
KR970051271A (en) * 1995-12-29 1997-07-29 김주용 Buro decoder circuit
KR19980021468A (en) * 1996-09-17 1998-06-25 문정환 Semiconductor memory device

Similar Documents

Publication Publication Date Title
US6269047B1 (en) Semiconductor memory device
KR100363142B1 (en) Semiconductor Integrated Circuits with Three-State Logic Circuits
US20040001386A1 (en) Deep power down control circuit
KR0121131B1 (en) Driving circuit in semiconductor memory device
KR100471737B1 (en) Output circuits, circuits to reduce leakage currents, methods for selectively switching transistors and semiconductor memory
KR970012749A (en) Subwordline Decoder of Semiconductor Memory Devices
KR100220939B1 (en) Word line driving method of memory device
KR20010058893A (en) Wordline driving circuit for semiconductor memory device
KR100303364B1 (en) Sub word line driving circuit
KR960043149A (en) Semiconductor device for reducing standby power consumption
KR100385463B1 (en) A word line control circuit of semiconductor memory device
KR20000055319A (en) Circuit for driving lower word line
KR970012756A (en) A semiconductor memory device including a divided decoder circuit composed of NMOS transistors
KR20060010030A (en) Semiconductor device for low power dissipation
JP3554638B2 (en) Semiconductor circuit
US6252429B1 (en) Method and apparatus for improving device matching and switching point tolerance in silicon-on-insulator cross-coupled circuits
KR970071824A (en) Word line driver circuit
KR100407986B1 (en) word line driving circuit
KR100281282B1 (en) Selective Wordline Bias Device in Leakage Current Vulnerable Areas
KR100186345B1 (en) Level shift circuit
KR100250928B1 (en) Sub row decoder circuit
KR100214275B1 (en) Word line driving circuit and data output buffer
KR100232893B1 (en) Row decoder for semiconductor memory device
KR960001861B1 (en) High speed row decoder
KR0144496B1 (en) Word line driver apparatus

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
E902 Notification of reason for refusal
E601 Decision to refuse application