JPWO2015118601A1 - 表示装置 - Google Patents
表示装置 Download PDFInfo
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- JPWO2015118601A1 JPWO2015118601A1 JP2015560868A JP2015560868A JPWO2015118601A1 JP WO2015118601 A1 JPWO2015118601 A1 JP WO2015118601A1 JP 2015560868 A JP2015560868 A JP 2015560868A JP 2015560868 A JP2015560868 A JP 2015560868A JP WO2015118601 A1 JPWO2015118601 A1 JP WO2015118601A1
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- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
- Electroluminescent Light Sources (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
本発明者は、例えば図2に示すような画素回路において、画素回路に供給される低電圧側の電源(図2のVEL)が0Vでも負の電圧でもなく正の電圧(例えば2、3V程度)とすべきであることを見出した。
以下、適宜図面を参照しながら、実施の形態を詳細に説明する。但し、必要以上に詳細な説明は省略する場合がある。例えば、既によく知られた事項の詳細説明や実質的に同一の構成に対する重複説明を省略する場合がある。これは、以下の説明が不必要に冗長になるのを避け、当業者の理解を容易にするためである。
図1は、実施の形態における表示装置の構成例を示すブロック図である。図2は、実施の形態における画素回路の構成例を示す回路図である。
図2の画素回路60は、駆動トランジスタ61と、スイッチトランジスタ62〜65と、発光素子66と、容量素子67とを備えている。また、Data線76は、データ線駆動回路5から輝度電圧を供給するためのデータ線である。基準電圧電源線68は、電源部4から基準電圧VREFを供給するための電源線である。基準電圧VREFは、初期化期間に容量素子67の第1電極の電位として設定される。初期化期間については後述する。第1電源線69は、電源部4から第1電圧VTFTを供給するための電源線である。第2電源線70は、電源部4から第2電圧VELを供給するための電源線である。初期化電源線71は初期化電圧VINIを供給するための電源線である。初期化電圧VINIは、初期化期間に容量素子67の第2電極に設定される。
次に電源部4の構成について説明する。図3は、実施の形態における電源部の回路例と、画素回路60をと示す回路図である。同図では、電源部4の回路構成のうち、主として第1電圧VTFTおよび第2電圧VELを生成する回路部分を示している。同図では、複数の画素回路60のうちの1つのみ代表として簡略化し図示している。
VTFT電源410(つまり第1電源回路)は、入力電圧Vinをチョッピングすることにより第1電源線69に第1電圧VTFTを出力する同期整流型の電源回路である。このVTFT電源410は、第1ハイサイドスイッチ411、第1ローサイドスイッチ412、第1インダクタ413、第1制御回路414、第1出力キャパシタ419を備える。
VEL電源420には、上記の入力電圧Vinではなく、入力電圧Vinよりも低い電圧の第1電圧VTFTが入力される。
次に、図3に示した電源装置の動作および図1に示した表示装置の動作について説明する。
図4Aは、VTFT電源410のスイッチングのデューティ比と出力電圧の関係を示す説明図である。図4Aにおいて横軸は時間軸、縦軸は電圧であり、チョッピングされた入力電圧(つまり第1インダクタ413の一端に入力されるパルス状の入力電圧)と、出力電圧である第1電圧VTFTとを模式的に図示してある。
VEL電源420の動作については、基本的にVTFT電源410と同様であるので、異なる点を中心に説明する。VEL電源420では、入力電圧である第1電圧VTFT、出力電圧である第2電圧、デューティβには次の関係がある。
次に、表示パネルにおける、既に触れたしきい値電圧補償動作を含む表示動作について説明する。
図5に示す時刻t0〜時刻t1の期間T21は、スイッチトランジスタ64のみを導通状態であり、図2の節点Bの電位を初期化電源線71の初期化電圧VINIに設定するための期間である。
図5に示す時刻t1〜時刻t2の期間T22は、駆動トランジスタ61のしきい値電圧補償を行うためのドレイン電流を流すのに必要な初期電圧を容量素子67に保持させ、駆動トランジスタ61のソースゲート間に印加するための初期化期間である。
図5に示す時刻t2〜時刻t3の期間T23は、スイッチトランジスタ64とスイッチトランジスタ65とが同時に導通状態とならないようにするための期間である。
次に、図5の時刻t3〜時刻t4の期間T24は、複数の画素回路60における駆動トランジスタ61のしきい値電圧のばらつきを補償するしきい値設定期間である。つまり、複数の画素回路60における駆動トランジスタ61のしきい値電圧にばらつきがあっても、個々の駆動トランジスタ61のしきい値電圧に相当する電圧を対応する容量素子67に設定する期間である。
図5に示す時刻t4〜時刻t5の期間T25は、しきい値補償動作を終了させるための期間である。
時刻t5〜時刻t6の期間T26は、スイッチトランジスタ63を非導通状態(オフ状態)にすることで、Data線76を介して供給されたデータ信号電圧と基準電圧電源線68の基準電圧VREFとが同時に節点Aに印加されるのを防止する期間である。
時刻t6〜時刻t7の期間T27は、Data線76から表示階調に応じた輝度電圧を画素回路60にスイッチトランジスタ62を介して取り込み、容量素子67に書き込む書込期間である。
時刻t7〜時刻t8の期間T28は、スイッチトランジスタ62を確実に非導通にさせるための期間である。
次に、時刻t8〜時刻t9の期間T29は、発光期間である。
刻t9〜時刻t0の期間T30は、すべてのスイッチを非導通状態として、節点Aおよび節点Bの電位を、期間T21で必要な電圧に近い電圧まで変化させるための期間である。
本実施の形態における表示装置によれば、第2電圧を生成する第2電源回路であるVEL電源420が入力電圧Vinよりも低い電圧の第1電源VTFTをチョッピングするので、入力電圧Vinをチョッピングすることと比べて、スイッチング素子の遷移損失を軽減させることで、ディーティ比が極端に小さくなることによるスイッチング動作の不安定化を回避することができ、第2電圧を安定化することができる。
図6は、変形例における画素回路60の構成例を示す図である。表示装置1は、図2に示した画素回路60の代わりに図6に示す画素回路60を備える構成としてもよい。図6の画素回路60は、図1と比べて、スイッチトランジスタ63、スイッチトランジスタ64およびスイッチトランジスタ65が削除されている点が異なる。このように画素回路60の構成を単純化してもよい。
2 制御部
3 走査線駆動回路
4 電源部
5 データ線駆動回路
6 表示パネル
60 画素回路
61 駆動トランジスタ
62、63、64、65 スイッチトランジスタ
66 発光素子
67 容量素子
68 基準電圧電源線
69 第1電源線
70 第2電源線
71 初期化電源線
72 Scan線
73 Ref線
74 Init線
75 Enable線
76 Data線
401 入力電源線
409 入力キャパシタ
410 VTFT電源
411 第1ハイサイドスイッチ
412 第1ローサイドスイッチ
413 第1インダクタ
414 第1制御回路
419 第1出力キャパシタ
420 VEL電源
421 第2ハイサイドスイッチ
422 第2ローサイドスイッチ
423 第2インダクタ
424 第2制御回路
429 第2出力キャパシタ
Vin 入力電圧
VTFT 第1電圧
VEL 第2電圧
Claims (4)
- 第1電圧に維持される第1電源線と、前記第1電圧より低い正の第2電圧に維持される第2電源線とから電力供給を受ける行列状に配置された複数の画素回路と、
入力電圧をチョッピングすることにより前記第1電源線に前記第1電圧を出力する同期整流型の第1電源回路と、
前記第1電圧をチョッピングすることにより前記第2電源線に前記第2電圧を出力する同期整流型の第2電源回路と
を備え、
前記第1電源回路は、
前記入力電圧が印加される入力電源線と接地線の間に直列に接続された第1ハイサイドスイッチおよび第1ローサイドスイッチと、
一端が前記第1ハイサイドスイッチと前記第1ローサイドスイッチとの接続点に接続され、他端が前記第1電源線に接続された第1インダクタと、
前記第1ハイサイドスイッチおよび前記第1ローサイドスイッチのオンおよびオフを制御する第1コントローラと
を備え、
前記第2電源回路は、
前記第1電源線と前記接地線の間に直列に接続された第2ハイサイドスイッチおよび第2ローサイドスイッチと、
一端が前記第2ハイサイドスイッチと前記第2ローサイドスイッチとの接続点に接続され、他端が前記第2電源線に接続された第2インダクタと、
前記第2ハイサイドスイッチおよび前記第2ローサイドスイッチのオンおよびオフを制御する第2コントローラと
を備える表示装置。 - 前記複数の画素回路のそれぞれは、
供給される電流量に応じた明るさで発光する発光素子と、
前記発光素子に電流を供給する駆動トランジスタと
を備え、
前記駆動トランジスタおよび前記発光素子は、前記第1電源線と前記第2電源線との間に直列に接続される
請求項1に記載の表示装置。 - 前記表示装置は、さらに
前記入力電源線と前記接地線との間に接続された入力キャパシタと、
前記第1電源線と前記接地線との間に接続された第1出力キャパシタと、
前記第2電源線と前記接地線との間に接続された第2出力キャパシタと
を備える
請求項1または2に記載の表示装置。 - 前記複数の画素回路のそれぞれは、前記駆動トランジスタのゲートに接続された容量素子を備え、
前記表示装置は、前記複数の画素回路の表示を制御する制御部を備え、
前記制御部は、
前記容量素子に、当該容量素子が接続された前記駆動トランジスタの実際のしきい値電圧に相当する電圧を保持させるしきい値補償動作を行い、
実際のしきい値電圧に相当する電圧が保持された前記容量素子に、輝度を表す電圧を上乗せする書き込み動作を行う
請求項2に記載の表示装置。
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