JPS6342141A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6342141A JPS6342141A JP61186406A JP18640686A JPS6342141A JP S6342141 A JPS6342141 A JP S6342141A JP 61186406 A JP61186406 A JP 61186406A JP 18640686 A JP18640686 A JP 18640686A JP S6342141 A JPS6342141 A JP S6342141A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- defective
- chips
- inspecting
- inspection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000007689 inspection Methods 0.000 claims abstract description 26
- 230000002950 deficient Effects 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000007261 regionalization Effects 0.000 abstract description 10
- 230000007547 defect Effects 0.000 abstract description 9
- 238000004148 unit process Methods 0.000 abstract 1
- 238000001514 detection method Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半導体基板
上に多数個の半導体チップをチップ単位で形成あるいは
検査する工程（例えば、パターン形成や電気的特性検査
等）の工数削減法に関する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a process of forming or inspecting a large number of semiconductor chips on a semiconductor substrate chip by chip (for example, pattern formation or electrical Concerning methods for reducing man-hours for physical characteristic testing, etc.).
従来、半導体装置製造の前工程（拡散工程）に於ては、
各種のパターン形成や検査工程を必要とするが、これら
パターン形成、検査では半導体基板上に設けられる全チ
ップに対して、作業（パターン形成や検査等）を実行す
ることが通常である。Conventionally, in the pre-process (diffusion process) of semiconductor device manufacturing,
Various pattern formation and inspection processes are required, and in these pattern formation and inspection, operations (pattern formation, inspection, etc.) are usually performed on all chips provided on a semiconductor substrate.
上述した従来の半導体装置の製造方法では、チップ単位
で作業する工程で、その工程に先行する検査工程での情
報を利用せず、先行する工程で既に不良と判定されたチ
ップに対しても、パターン形成や電気的特性検査を実行
するという無駄な工数をかけるという欠点がある。In the conventional semiconductor device manufacturing method described above, information obtained in the inspection process preceding the process is not used in the process of working on a chip-by-chip basis, even for chips that have already been determined to be defective in the previous process. This method has the disadvantage of requiring unnecessary man-hours for pattern formation and electrical characteristic testing.
上述した従来の半導体装置製造方法に対し本発明は、各
検査工程での結果を記録する工程を含むことにより、先
行する検査情報を有効に利用し、チップ単位での作業工
程（例えばステッパーによるパターン形成工程や、電気
的特性検査等）では不良き判定されているチップを飛ば
して作業を行うという独創的内容を存する。In contrast to the conventional semiconductor device manufacturing method described above, the present invention includes a step of recording the results of each inspection step, thereby effectively utilizing the preceding inspection information, The process is unique in that chips that are determined to be defective are skipped during the process (forming process, electrical characteristic inspection, etc.).
本発明の半導体装置製造方法はチップ単位での検査工程
での結果を記録する工程とこの記録情報を利用して前記
検査工程に引き続く後工程の内、チップ単位での作業工
程（例えばステッパーによるパターン形成工程、７４気
的特性検査工程等）では不良チップを飛ばして作業する
という製造技術を存している。The semiconductor device manufacturing method of the present invention includes a process of recording the results of the inspection process on a chip basis, and using this recorded information to perform a work process on a chip basis (for example, patterning with a stepper) in the post-process following the inspection process. There is a manufacturing technology in which defective chips are skipped during the manufacturing process (forming process, 74-dimensional characteristic testing process, etc.).
次に本発明について図面を参照して説明する第１図は本
発明の一実施例の半導体基板の平面図である。Next, the present invention will be explained with reference to the drawings. FIG. 1 is a plan view of a semiconductor substrate according to an embodiment of the present invention.
良品チップ２と不良チップ３が半導体基板１上に存在す
る。A good chip 2 and a defective chip 3 exist on a semiconductor substrate 1.
第２図は第１図での不良チップ３の拡大平面図である。FIG. 2 is an enlarged plan view of the defective chip 3 in FIG. 1.
不良検出検査工程記録パターン５をチップ３上に設け、
不良検出検査工程番号（本説明図では３）上にレーザー
あるいは打刻針によりマーキングすることにより、本チ
ップが不良であることと、その不良検出検査工程を記録
する。この記録情報を行工程では光学的に検知し、この
チップへのパターン形成作業や電気的特性検査作業を施
こさずに飛ばして、次の良品チップへの作業を行う。A defect detection inspection process recording pattern 5 is provided on the chip 3,
By marking the defect detection inspection step number (3 in this explanatory drawing) with a laser or an engraving needle, it is recorded that the present chip is defective and the defect detection inspection step. This recorded information is optically detected in the line process, and the chip is skipped without pattern formation or electrical characteristic inspection, and work is performed on the next good chip.
この不良検出検査工程記録パターンをチップ最近のスク
ライブ領域４へ設けることや、工程番号ではなく単に不
良情報を記録することはなんらさしつかえない。There is nothing wrong with providing this defect detection inspection process recording pattern in the scribe area 4 closest to the chip, or simply recording defect information instead of the process number.
第３図は本発明の実施例２の半導体基板の平面図である
。FIG. 3 is a plan view of a semiconductor substrate according to Example 2 of the present invention.
半導体基板１上の良品チップ２や不良チップ３は半導体
基板上の位置を行番号と列番号で区分される。各チップ
の検査情報は磁気テープや磁気ディスクに記録すること
により、直接半導体チップ上には記録する必要がないの
で、記録操作による半導体基板の汚染や機械的強度の劣
化等は起らないという利点がこの実施例ではある。The positions of the good chips 2 and defective chips 3 on the semiconductor substrate 1 are classified by row numbers and column numbers. The inspection information for each chip is recorded on a magnetic tape or magnetic disk, so there is no need to record it directly on the semiconductor chip, so there is no contamination of the semiconductor substrate or deterioration of mechanical strength due to recording operations, which is an advantage. is in this example.
以上説明したように本発明は、チップ単位での検査情報
（例えば、パターン形成後のパターン検査情報）を記録
し、それに引き続く後工程の内、チップ単位での作業工
程（例えば、ステッパーによるパターン形成や電気的特
性検査等）では不良チップには作業を施こさず、良品チ
ップにのみ作業を施こすことにより、作業工数の削減が
図られるという効果がある。As explained above, the present invention records inspection information for each chip (for example, pattern inspection information after pattern formation), and performs a work process for each chip (for example, pattern formation by a stepper) in the subsequent post-process. (electrical characteristic inspection, etc.), the work is performed only on good chips without performing work on defective chips, which has the effect of reducing the number of work steps.
更には各検査工程での不良チップの半導体基板上の位置
が記、録されているので、工程能力改善や、不良原因調
査の活動に多大の効果がある。現在の半導体装置製造法
では不良チップの発生率は５％から多いものでは７０％
程度に達する為、本発明の利用により工数削減率は５０
％にまで及ぶものである。又、製造工程途中での不良は
最終段階での電気的特性検査で良、不良の判定が困難と
なることが多く、市場へ品質の劣悪な半導体装置を出荷
してしまうという問題があるが、パターン形成を行なわ
ないことにより積極的に不良チップとしてしまうので、
品質の向上にも多大の効果がある。Furthermore, since the position of a defective chip on the semiconductor substrate in each inspection process is recorded, it is highly effective in improving process performance and investigating the cause of defects. With current semiconductor device manufacturing methods, the incidence of defective chips ranges from 5% to 70%.
The reduction in man-hours by using the present invention is 50%.
%. In addition, it is often difficult to determine whether a defective product is good or defective during the final stage of the electrical characteristic test when a defective product occurs during the manufacturing process, and there is a problem in that semiconductor devices of inferior quality are shipped to the market. By not performing pattern formation, it will actively become a defective chip.
It also has a great effect on improving quality.
第１図は本発明の実施例１の半導体基板の平面図、第２
図は検査情報記録法を示すチップ平面図、第３図は本発
明の実施例２の半導体基板の平面図である。
１・・・半導体基板、２・・・良品チップ、３・・・不
良チップ、４・・・スクライブ線、５・・・不良検出検
査工程記録パターン。
￥ １ 防
＋２ てFIG. 1 is a plan view of a semiconductor substrate of Example 1 of the present invention, and FIG.
The figure is a plan view of a chip showing an inspection information recording method, and FIG. 3 is a plan view of a semiconductor substrate according to a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Good chip, 3... Defective chip, 4... Scribe line, 5... Defect detection inspection process recording pattern. ￥ 1 Defense +2
Claims (1)
と、チップ単位でのチップ形成工程を含む半導体基板上
に複数のチップを形成する製造方法において前記検査結
果に基づき、引き続く後工程の内チップ単位でのチップ
形成、検査工程では良品チップにのみ作業を施こすこと
を特徴とする半導体装置の製造方法。In a manufacturing method for forming a plurality of chips on a semiconductor substrate, which includes a process of inspecting each chip, a process of recording the inspection results, and a process of forming a chip on a per-chip basis, based on the inspection results, one of the subsequent processes is performed. A method for manufacturing a semiconductor device, characterized in that in a chip formation and inspection process, work is performed only on non-defective chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61186406A JPS6342141A (en) | 1986-08-07 | 1986-08-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61186406A JPS6342141A (en) | 1986-08-07 | 1986-08-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6342141A true JPS6342141A (en) | 1988-02-23 |
Family
ID=16187852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61186406A Pending JPS6342141A (en) | 1986-08-07 | 1986-08-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6342141A (en) |
-
1986
- 1986-08-07 JP JP61186406A patent/JPS6342141A/en active Pending
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