JPS63253706A - Differential circuit - Google Patents
Differential circuitInfo
- Publication number
- JPS63253706A JPS63253706A JP8825387A JP8825387A JPS63253706A JP S63253706 A JPS63253706 A JP S63253706A JP 8825387 A JP8825387 A JP 8825387A JP 8825387 A JP8825387 A JP 8825387A JP S63253706 A JPS63253706 A JP S63253706A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- differential circuit
- differential
- voltage
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920006395 saturated elastomer Polymers 0.000 abstract description 10
- 230000007704 transition Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 13
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- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は差動回路に関し、特に、ＭＯＳトランジスタを
用いた差動回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential circuit, and particularly to a differential circuit using MOS transistors.
第５図は、従来の差動回路の一例の回路図、第６図は第
５図の回路の各部の電圧波形を示す図である。FIG. 5 is a circuit diagram of an example of a conventional differential circuit, and FIG. 6 is a diagram showing voltage waveforms at various parts of the circuit of FIG.
この差動回路４は、ソースが共通接続され、差動対をな
す２つのＭＯＳトランジスタＭ、、Ｍ。This differential circuit 4 includes two MOS transistors M, , M whose sources are commonly connected and form a differential pair.
と、カレントミラー負荷を構成するＭＯＳトランジスタ
Ｍ３．Ｍ４と、定電流源３とからなっており、電源電位
ＶｆｆＤと接地電位ＧＮＤとの間で動作する。また、Ｍ
ＯＳトランジスタＭ、のゲートには、基準電圧源２から
発生する基準電圧ｖ噌が印加されており、ＭＯＳトラン
ジスタＭ２のゲートには入力電圧Ｖｌｌｌが入力されて
いる。and a MOS transistor M3. which constitutes a current mirror load. M4 and a constant current source 3, and operates between power supply potential VffD and ground potential GND. Also, M
A reference voltage v generated from a reference voltage source 2 is applied to the gate of the OS transistor M, and an input voltage Vll is input to the gate of the MOS transistor M2.
次に、この回路の動作を説明する。Next, the operation of this circuit will be explained.
時刻ｔ４までは入力電圧Ｖ ＩＮ ＞ ＞基準電圧Ｖ−
の関係にあるため、差動対をなす２つのトランジスタＭ
、、Ｍ２のうちトランジスタＭ２が完全にオンしており
、出力電圧Ｖ−はグランド側に飽和し、ローレベルとな
っている。次に時刻ｔ４において、入力端子Ｖ ＩＮの
レベルが反転して入力電圧Ｖ ＩＮ ＜ ＜基準電圧ｖ
Ｆ、Ｉとなると、出力電圧Ｖユは非飽和領域に戻り始め
、時刻ｔ６において、出力電圧Ｖ−ｖは電源電圧側に飽
和してハイレベルとなる。Until time t4, input voltage V IN>>Reference voltage V-
Therefore, the two transistors M forming a differential pair
,, Of the transistors M2, the transistor M2 is completely turned on, and the output voltage V- is saturated to the ground side and is at a low level. Next, at time t4, the level of the input terminal V IN is inverted so that the input voltage V IN <<reference voltage v
When F and I are reached, the output voltage VY begins to return to the non-saturation region, and at time t6, the output voltage V-v is saturated to the power supply voltage side and becomes a high level.
（発明が解決しようとする問題点〕
上述した従来の差動回路４は、基準電圧Ｖｈｌと入力電
圧Ｖ Ｉｍとの関係が、Ｖ ＋ｗ ＞ ＞ Ｖ Ｈ、あ
るいはＶ ＩＮ ＜ ＜ Ｖ ｈｔのときに差動回路が
深く飽和し、この状態から、入力電圧Ｖ ＋ｗのレベル
が反転する場合、非飽和領域に移行するまでに時間を要
するために、出力電圧ｖｗＴがこれに追従して切り替わ
るまでに時間がかかり、出力の応答が遅いという欠点が
ある。(Problems to be Solved by the Invention) In the conventional differential circuit 4 described above, when the relationship between the reference voltage Vhl and the input voltage V Im is V + w >> V H or V IN << V ht. When the differential circuit is deeply saturated and the level of the input voltage V+w is reversed from this state, it takes time to transition to the non-saturation region, so it takes time for the output voltage vwT to follow this and switch. The disadvantage is that it takes a long time and the output response is slow.
（問題点を解決するための手段〕
本発明の差動回路は、２つのＭＯＳトランジスタのそれ
ぞれのドレイン間に接続され、制御信号によってオン／
オフが制御されるスイッチ回路を有している。(Means for Solving the Problems) The differential circuit of the present invention is connected between the respective drains of two MOS transistors, and is turned on/off by a control signal.
It has a switch circuit whose off-state is controlled.
（作用）
差動回路に入力信号が入力される直前、あるいは、入力
信号が入力された直後に、前述したスイッチ回路をオン
させ、差動対をなすＭＯＳトランジスタのドレイン電位
をほぼ等電位とすることにより、差動回路が深く飽和し
ている場合でも、瞬時に非飽和領域に移行させることが
でき、この結果、出力が入力に対して高速に追従できる
差動回路が得られる。(Function) Immediately before or after an input signal is input to the differential circuit, the above-mentioned switch circuit is turned on to make the drain potentials of the MOS transistors forming the differential pair almost equal to each other. As a result, even if the differential circuit is deeply saturated, it can be instantly shifted to a non-saturated region, and as a result, a differential circuit can be obtained in which the output can follow the input at high speed.
（実施例） 本発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の差動回路の一実施例の回路図、第２図
はこの実施例の各部の電圧波形を示す図、第３図は第１
図の差動回路を用いたコンパレータの回路図、第４図は
コンパレータの各部の電圧波形を示す図である。FIG. 1 is a circuit diagram of one embodiment of the differential circuit of the present invention, FIG. 2 is a diagram showing voltage waveforms at various parts of this embodiment, and FIG.
FIG. 4 is a circuit diagram of a comparator using the differential circuit shown in the figure, and FIG. 4 is a diagram showing voltage waveforms at various parts of the comparator.
第１図の実施例の差動回路１は、従来例の回路において
、差動対をなすＭＯＳトランジスタＭ、、Ｍ、のドレイ
ン間にドレイン・ソース経路が接続され、ゲートにオン
／オフ制御電圧ＶＣが印加されているリセット用ＰＭＯ
ＳトランジスタＭ５を設けたものである。In the differential circuit 1 of the embodiment shown in FIG. 1, in the conventional circuit, a drain-source path is connected between the drains of MOS transistors M, , M, forming a differential pair, and an on/off control voltage is applied to the gate. Reset PMO to which VC is applied
An S transistor M5 is provided.
、 次に、本実施例の動作を説明する。, Next, the operation of this embodiment will be explained.
時刻ｔ１までは、入力電圧Ｖ ＋ｖｓ ＞ ＞基準電圧
Ｖ Ｆ、、の関係にあるため、差動対をなす２つのトラ
ンジスタＭ、、Ｍ２のうちトランジスタＭ２が完全にオ
ンして右り、出力電圧ｖ＃Ｔはグランド側に飽和し、ロ
ーレベルとなっている。このとき、制御信号Ｖｃは電源
電圧レベルであり、リセット用ＭＯＳトランジスタＭ５
はオフしている。次に時刻１．において、入力端子Ｖ…
のレベルが反転して入力電圧Ｖ ｕｓ ＜ ＜基準電圧
Ｖ−となり、出力電圧Ｖａｔは非飽和領域に戻り始める
。次に、時刻ｔ２において、制御信号Ｖｃをグランドレ
ベルとして、リセット用ＰＭＯＳトランジスタＭ５をオ
ンさせる。すると、差動対をなす２つのトランジスタＭ
、、Ｍ２のドレイン電位がほぼ等電位となり、差動回路
１は強制的に非飽和領域に入る。Until time t1, the relationship is that input voltage V + vs >> reference voltage V F, so transistor M2 of the two transistors M, , M2 forming the differential pair is completely turned on and the output voltage increases. v#T is saturated on the ground side and is at a low level. At this time, the control signal Vc is at the power supply voltage level, and the reset MOS transistor M5
is off. Next, time 1. At the input terminal V...
The level of is reversed to become input voltage V us << reference voltage V-, and output voltage Vat begins to return to the non-saturation region. Next, at time t2, the control signal Vc is set to the ground level and the reset PMOS transistor M5 is turned on. Then, the two transistors M forming a differential pair
, , the drain potentials of M2 become approximately equal potentials, and the differential circuit 1 is forced to enter the non-saturation region.
次に、時刻ｔ３において、制御電圧ＶＣを再び電源電圧
Ｖｏｏに立上げる。すると、リセット用ＰＭＯ５）ラン
ジスタＭ５はオフし、入力電圧Ｖ ａｍ ＜ ＜基準電
圧■ｈＩの関係にしたがって、出力電圧ｖ＃ｎは電源側
で飽和し、ハイレベル信号が得られる。Next, at time t3, control voltage VC is raised to power supply voltage Voo again. Then, the reset PMO 5) transistor M5 is turned off, and according to the relationship: input voltage V am <<reference voltage hI, the output voltage v#n is saturated on the power supply side, and a high level signal is obtained.
第３図のコンパレータ５は、逐次比較形Ａ／Ｄコンバー
タ等に用いられるもので、第１図の差動回路１の定電流
源３を、ゲートにバイアス電圧ＶＢが印加されているＭ
ＯＳトランジスタＭ６で構成し、さらにＭＯＳ）ランジ
スタＭ？、ＭＢおよびＭＯＳトランジスタＭ９．ＭＩ６
からなる増幅回路を付加したものである。この回路は、
上述した実施例と同様に、時刻ｔ１において入力電圧Ｖ
ｍのレベルが反転し、時刻ｔ２において制御信号がロー
レベルとなることによって、時刻ｔ３に差動回路１の出
力ｖＡがハイレベルとなり、この出力ＶＡは、ＭＯＳト
ランジスタＭフ、Ｍｅからなる第１の増幅回路で増幅さ
れ、さらに、ＭＯＳトランジスタＭ９．Ｍ２Ｏからなる
ＣＭＯＳインバータで、はぼ電源電圧レベルに増幅され
、コンパレータ５の出力Ｖｗｔが得られる。逐次比較型
Ａ／Ｄ変換器のような周期的にコンパレータの出力を必
要とする回路において、入力に対して高速に追従可能な
コンパレータを有することは、回路全体の高速化につな
かる。The comparator 5 shown in FIG. 3 is used in a successive approximation type A/D converter, etc., and connects the constant current source 3 of the differential circuit 1 shown in FIG.
Consists of OS transistor M6, and further MOS) transistor M? , MB and MOS transistor M9. MI6
An amplifier circuit consisting of the following is added. This circuit is
Similarly to the embodiment described above, the input voltage V at time t1
The level of the differential circuit 1 is inverted and the control signal becomes low level at time t2, so that the output vA of the differential circuit 1 becomes high level at time t3. MOS transistor M9. A CMOS inverter made of M2O amplifies it to almost the power supply voltage level, and the output Vwt of the comparator 5 is obtained. In a circuit that periodically requires a comparator output, such as a successive approximation type A/D converter, having a comparator that can follow the input at high speed leads to speeding up of the entire circuit.
また、本発明は、例えば、ダイナミックレンジをこえる
入力信号が加えられたときに、リセット用ＭＯＳトラン
ジスタをオンさせ、差動増幅回路を非飽和領域（直線領
域）に戻し、次のアナログ入力にできるだけ早く追従さ
せる場合等にも有効である。Further, the present invention turns on the reset MOS transistor when an input signal exceeding the dynamic range is applied, returns the differential amplifier circuit to the non-saturation region (linear region), and inputs as much as possible to the next analog input. This is also effective for quick tracking.
以上説明したように本発明は、差動回路に外部からの制
御信号により動作するスイッチ回路を設け、差動回路に
入力信号か入力される直前、あるいは入力信号が入力さ
れた直後に、スイッチ回路をオンさせることにより、差
動回路が飽和領域にあっても、瞬時に非飽和領域へ移行
させることができ、高速に入力信号に追従可能な差動回
路が得られるという効果がある。As explained above, the present invention provides a differential circuit with a switch circuit operated by an external control signal, and immediately after an input signal is input to the differential circuit, or immediately after the input signal is input, the switch circuit By turning on the differential circuit, even if the differential circuit is in the saturated region, it can be instantly shifted to the non-saturated region, and there is an effect that a differential circuit that can follow the input signal at high speed can be obtained.
第１図は本発明の差動回路の一実施例の回路図、第２図
は第１図の回路の各部の電圧波形を示す図、第３図は第
１図の差動回路を用いたコンパレータの回路図、第４図
は第３図のコンパレータの各部の電圧波形を示す図、第
５（２）は差動回路の従来例の回路図、第６図は第５図
の回路の各部の電圧波形を示す図である。
１．４・・・差動回路、
２・・・基準電圧源、
３・・・定電流源、
５・・・コンパレータ、
Ｍ、ＮＭ、、・・・ＭＯＳトランジスタ、ＶＣ・・・制
御電圧、
Ｖ Ｐｅｔ・・・基準電圧、
Ｖ ＩＮ・・・入力電圧、
■岨・・・出力電圧、
■よ・・・差動回路出力、
■８・・・バイアス電圧、
ＶＤＤ・・・電源電圧、
ＧＮＤ・・・接地電位、
ｔ、ｘｔ６ ・・・時刻。
＼、−二
第１図
第２図
第４図
！５図Fig. 1 is a circuit diagram of one embodiment of the differential circuit of the present invention, Fig. 2 is a diagram showing voltage waveforms at various parts of the circuit of Fig. 1, and Fig. 3 is a circuit diagram of an embodiment of the differential circuit of the present invention. Circuit diagram of the comparator, Figure 4 is a diagram showing voltage waveforms at various parts of the comparator in Figure 3, Figure 5 (2) is a circuit diagram of a conventional example of a differential circuit, and Figure 6 is a diagram showing each part of the circuit in Figure 5. It is a figure which shows the voltage waveform of. 1.4...Differential circuit, 2...Reference voltage source, 3...Constant current source, 5...Comparator, M, NM,...MOS transistor, VC...Control voltage, V Pet...Reference voltage, V IN...Input voltage, ■岨...Output voltage, ■Yo...Differential circuit output, ■8...Bias voltage, VDD...Power supply voltage, GND ...Ground potential, t, xt6 ...Time. \, -2 Figure 1 Figure 2 Figure 4! Figure 5
Claims (1)
トランジスタと、それぞれのドレインと電源との間に接
続された負荷回路を有する差動回路において、 前記ＭＯＳトランジスタのそれぞれのドレイン間に接続
され、制御信号によってオン／オフが制御されるスイッ
チ回路を有することを特徴とする差動回路。 ２、前記スイッチ回路は、ゲートにオン／オフ制御信号
が入力されるＭＯＳトランジスタである特許請求の範囲
第１項に記載の差動回路。[Claims] 1. Two MOSs whose sources are commonly connected and form a differential pair.
A differential circuit having transistors and a load circuit connected between each drain and a power supply, comprising a switch circuit connected between each drain of the MOS transistor and whose on/off is controlled by a control signal. A differential circuit characterized by: 2. The differential circuit according to claim 1, wherein the switch circuit is a MOS transistor whose gate receives an on/off control signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8825387A JPS63253706A (en) | 1987-04-09 | 1987-04-09 | Differential circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8825387A JPS63253706A (en) | 1987-04-09 | 1987-04-09 | Differential circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63253706A true JPS63253706A (en) | 1988-10-20 |
Family
ID=13937700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8825387A Pending JPS63253706A (en) | 1987-04-09 | 1987-04-09 | Differential circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63253706A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5285168A (en) * | 1991-09-18 | 1994-02-08 | Hitachi, Ltd. | Operational amplifier for stably driving a low impedance load of low power consumption |
| US5373473A (en) * | 1992-09-01 | 1994-12-13 | Mitsubishi Denki Kabushiki Kaisha | Amplifier circuit and semiconductor memory device employing the same |
| US5497122A (en) * | 1995-01-20 | 1996-03-05 | Crystal Semiconductor | Low power class-AB integrated circuit amplifier |
| US5825244A (en) * | 1995-01-20 | 1998-10-20 | Crystal Semiconductor | Low power class AB integrated circuit amplifier having improved linearity when driving high impedance loads |
-
1987
- 1987-04-09 JP JP8825387A patent/JPS63253706A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5285168A (en) * | 1991-09-18 | 1994-02-08 | Hitachi, Ltd. | Operational amplifier for stably driving a low impedance load of low power consumption |
| US5373473A (en) * | 1992-09-01 | 1994-12-13 | Mitsubishi Denki Kabushiki Kaisha | Amplifier circuit and semiconductor memory device employing the same |
| US5497122A (en) * | 1995-01-20 | 1996-03-05 | Crystal Semiconductor | Low power class-AB integrated circuit amplifier |
| US5825244A (en) * | 1995-01-20 | 1998-10-20 | Crystal Semiconductor | Low power class AB integrated circuit amplifier having improved linearity when driving high impedance loads |
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