JPS6311770Y2 - - Google Patents
Info
- Publication number
- JPS6311770Y2 JPS6311770Y2 JP17079078U JP17079078U JPS6311770Y2 JP S6311770 Y2 JPS6311770 Y2 JP S6311770Y2 JP 17079078 U JP17079078 U JP 17079078U JP 17079078 U JP17079078 U JP 17079078U JP S6311770 Y2 JPS6311770 Y2 JP S6311770Y2
- Authority
- JP
- Japan
- Prior art keywords
- pll
- time constant
- output
- lock detection
- reduction filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000001052 transient effect Effects 0.000 claims description 14
- 238000001514 detection method Methods 0.000 claims description 11
- 230000010355 oscillation Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000000630 rising effect Effects 0.000 description 3
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
- Circuits Of Receivers In General (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【考案の詳細な説明】
本考案は局部発振回路を位相同期ループPLL
で構成し、電子的に同調を行なう受信機に係り、
特にミユーテイング回路の改良を目的とするもの
である。
局部発振回路をPLLで構成した受信機は、一
般に第1図のように構成され、PLL1を構成す
るプログラマブル分周器2の分周比Nを分周比設
定手段3により変更し、電圧制御発振器4から所
定の局部発振周波数foを発生させ選局を行なうも
のであり、基準周波数発振器5の発振周波数を局
間周波数に設定することにより、局部発振周波数
foが局間周波数ステツプで得られ、デイジタル的
に選局を行なう。
ところで、このようなPLL1では、プログラ
マブル分周器2の分周比Nが変更され、電圧制御
発振器4から新たな周波数が発生される際、第2
図に示すような過渡応答状態を経た後、PLL1
がロツクされ新しい周波数が安定に発生される
が、この過渡応答時間は選局時間の短縮を計る点
からすれば短い方が良く、過渡応答時間が低減濾
波器6の時定数に依存していることから、低減濾
波器6の時定数を小さくし過渡応答時間を短くす
ると、今度はPLL1がロツクした時の安定度が
悪化し、受信性能が劣ることになり、好ましくな
い。
そこで、従来は第3図のようにPLL1がロツ
クされる迄の期間は過渡応答時間を短くするよう
低減濾波器6の時定数を小さくし、PLL1がロ
ツクされるとロツク検出で低減濾波器6の時定数
を大きくするよう低減濾波器6の時定数の切換え
が行なわれている。
又PLL1がロツクされていない期間、即ち過
渡応答状態では、放送が受信されない為この間ス
ピーカー7から雑音が発生されるのを防止するよ
う音声経路を遮断するミユーテイング回路8が設
けられ、PLL1のロツク検出でミユーテイング
を解除するよう構成されている。
而して、前述のようにPLL1のロツク検出
で、、低減濾波器6の時定数の切換えとミユーテ
イング解除を同時に行なうと、時定数切換えに伴
なう障害が発生することが分つた。即ち、時定数
が切換えられる事によりPLL1のロツクが外れ、
低減濾波器6の出力電圧が変動し、第4図に示す
ように小さな第2過渡応答T2が生じ、この時既
にミユーテイングが解除されている為、スピーカ
ー7より過渡応答時の雑音が発生され聞き苦しか
つた。
従つて、本考案はこの点に鑑み成されたもの
で、ミユーテイング解除を低減濾波器の時定数切
換え後に行ない、時定数切換えに伴なう障害を除
去したことを特徴とする受信機を提供するもので
ある。
以下、本考案の実施例を図面に基づき説明す
る。尚、第1図と同一構成要素は同一符号にて示
す。
第5図は本考案の受信機の要部を示す図で、9
は電圧制御発振器4の分周出力fvと、基準周波数
発振器5の基準周波数fsが入力に加えられ、出力
U,Dに入力信号の位相差に応じた出力信号を発
生する周知のデイジタル位相比較器で、PLL1
がロツクした時、両出力ともHレベルになり、ロ
ツクが外れた時、一方の出力がLレベルになる特
性を有している。10は位相比較器9の出力を入
力とし、位相比較器9の出力に応じ低減濾波器6
を制御するよう出力が低減濾波器6に接続された
チヤージポンプで、C−MOSで構成されている。
低減濾波器6はアクテイブ型に構成され、PLL
1のロツク時と非ロツク時で時定数が変更される
ようリレー接点11が設けられており、出力が電
圧制御発振器4に導かれている。12はPLL1
のロツク検出回路で、位相比較器9の出力を入力
としたNANDゲート13と、積分回路14及び
積分回路14の出力で導通が制御されるトランジ
スタ15で構成されており、PLL1のロツクが
外れると位相比較器9の出力U,Dの一方がLベ
ルになることにより、NANDゲート13の出力
がHレベルとなりトランジスタ15が導通し、コ
レクタはLレベルであるが、PLL1がロツクし
位相比較器9の出力U,Dが共にHレベルになる
と、NANDゲート13の出力がLベルになるこ
とにより、トランジスタ15が不導通となり、コ
レクタにHレベルのロツク信号を発生する。16
はロツク信号の立上りで動作し、ロツクパルスを
発生するワンシヨツトマルチバイブレーター、1
7は該ワンシヨツトマルチバイブレーター16の
出力の立上りによりセツトされ、選局開始キー1
8の操作でリセツトされるフリツプフロツプ19
と、セツト出力Qによるトランジスタ20の導通
で励磁されるリレー21で構成された時定数切換
回路で、リレー21の励磁により低減濾波器6の
リレー接点11を切換える。
22はミユーテイング制御回路で、セツト端子
に前記選局開始キー18が接続され、リセツト端
子にフリツプフロツプ19のQ出力とワンシヨツ
トマルチバイブレーター16の出力とを二入力と
するANDゲート22の出力が接続されたフリツ
プフロツプ24で構成され、セツト出力Qがミユ
ーテイング信号としてミユーテイング回路8に加
えられている。
次に、斯る構成よりなる本考案の動作につき説
明する。
現在受信中の局から他の局を受信する場合、選
局開始キー18の操作で分周比設定手段3の値を
1づつ順次変更することにより、放送している局
を選局するが、先ず受信状態から選局開始キー1
8を操作し分周比設定手段3の値がNからN+1
に変更された場合につき説明する。
選局開始キー18が操作され、スタートパルス
が発生されると、分周比設定手段3の値が変更さ
れることにより、同時にプログラマブル分周器2
の分周比Nが変更され、PLL1が動作されるが、
この時選局開始キー18の操作で時定数切換回路
17のプリツプフロツプ19がリセツトされ、ミ
ユーテイング制御回路22のフリツプフロツプ2
4がセツトされることにより、受信状態で励磁さ
れていたリレー21の消磁で、リレー接点11が
開放され、低減濾波器6の時定数が小さく切換え
られると共にミユーテイング信号が発生し、音声
経路を遮断する。そして、PLL1が過渡応答状
態を経たロツクされると、位相比較器9の両出力
U,Dが共にHレベルになることにより、ロツク
検出回路12からロツク信号が発生されワンシヨ
ツトマルチバイブレーター16からの第1のロツ
クパルスP1が発生されると、このロツクパルス
の立上りに応答して時定数切換回路17のフリツ
プフロツプ19がセツトされ、リレー21が励磁
され、リレー接点11を閉じることにより低減濾
波器6の時定数を大に設定する。
この際、時定数の変化により低減濾波器6の出
力は、第6図に示すように多少過渡応答時に変化
する〔第2過渡応答T2〕。そこで、電圧制御発振
器4の発振周波数が変動するので、PLL1のロ
ツクが外れ、デイジタル位相比較器9の一方の出
力がLレベルとなり、ロツク検出回路12の出力
がLレベルとなる。ところで、この第2過渡応答
T2が終了すると、PLL1がロツクし位相比較器
9の出力U,Dが共にHレベルになり、NAND
ゲート13の出力がLレベルになることにより、
トランジスタ15が不導通となり、コレクタにH
レベルのロツク信号を発生する。従つて、このH
レベルのロツク信号に基づきワンシヨツトマルチ
バイブレーター16より第2のロツクパルスP2
が発生される。
この時、第1のロツクパルスP1によりフリツ
プフロツプ19はセツトされ、Q出力がHレベル
となつており、又ANDゲート22に第2のロツ
クパルスP2のHレベルのロツク信号が印加され
ることになるので、ANDゲート22よりリセツ
ト信号がフリツプフロツプ24に印加される。従
つて、ミユーテイング信号が解除され、この時放
送を受信していればスピーカー7より再生され
る。斯くして、時定数切換時発生される雑音が遮
断される。
上述の如く本考案の受信機は、局部発振回路を
PLLで構成し、PLLのロツク及びロツク外れに
より、低減濾波器の時定数を切換えるよう構成す
ると共にミユーテイング解除を時定数の切換え後
に発生する第2のロツクパルスにて行うよう構成
したので、時定数切換に伴なう雑音発生を確実に
防止することが出来る。 [Detailed explanation of the invention] This invention uses a local oscillation circuit as a phase-locked loop PLL.
Concerning a receiver that is configured with and that performs electronic tuning,
In particular, the purpose is to improve muting circuits. A receiver in which the local oscillation circuit is configured with a PLL is generally configured as shown in FIG. Tuning is performed by generating a predetermined local oscillation frequency fo from the oscillator 4, and by setting the oscillation frequency of the reference frequency oscillator 5 to the inter-station frequency, the local oscillation frequency can be adjusted.
fo is obtained by interstation frequency steps, and channel selection is performed digitally. By the way, in such a PLL 1 , when the frequency division ratio N of the programmable frequency divider 2 is changed and a new frequency is generated from the voltage controlled oscillator 4, the second
After passing through the transient response state shown in the figure, PLL 1
is locked and a new frequency is stably generated. However, from the point of view of shortening the channel selection time, it is better to shorten the transient response time, and the transient response time depends on the time constant of the reduction filter 6. Therefore, if the time constant of the reducing filter 6 is made small to shorten the transient response time, the stability when the PLL 1 is locked will deteriorate, and the receiving performance will be deteriorated, which is not preferable. Therefore, conventionally, as shown in Fig. 3, the time constant of the reduction filter 6 is made small to shorten the transient response time until PLL 1 is locked, and when PLL 1 is locked, the reduction filter 6 is activated upon lock detection. The time constant of the reduction filter 6 is switched to increase the time constant of the filter 6. In addition, during the period when PLL 1 is not locked, that is, in the transient response state, broadcasting is not received, so a muting circuit 8 is provided to cut off the audio path to prevent noise from being generated from the speaker 7 during this period. It is configured to release muting upon lock detection. Therefore, it has been found that if the time constant of the reduction filter 6 is switched and the muting is canceled at the same time when the PLL 1 locks as described above, a failure occurs due to the time constant switch. In other words, by switching the time constant, PLL 1 is unlocked.
The output voltage of the reduction filter 6 fluctuates, and a small second transient response T2 occurs as shown in FIG. 4, and since muting has already been released at this time, noise during the transient response is generated from the speaker 7. It was hard to hear. Therefore, the present invention has been developed in view of this point, and provides a receiver characterized in that mutating is canceled after the time constant of the reduction filter is switched, thereby eliminating the disturbance accompanying the time constant switching. It is something. Hereinafter, embodiments of the present invention will be described based on the drawings. Note that the same components as in FIG. 1 are indicated by the same symbols. Figure 5 is a diagram showing the main parts of the receiver of the present invention.
is a well-known digital phase comparator to which the divided output fv of the voltage controlled oscillator 4 and the reference frequency fs of the reference frequency oscillator 5 are applied to the inputs, and output signals corresponding to the phase difference of the input signals are generated at the outputs U and D. So, PLL 1
When the lock is locked, both outputs go to H level, and when the lock is released, one output goes to L level. 10 receives the output of the phase comparator 9 as an input, and operates a reduction filter 6 according to the output of the phase comparator 9.
This is a charge pump whose output is connected to a reduction filter 6 to control it, and is composed of C-MOS.
The reduction filter 6 is configured as an active type, and the PLL
A relay contact 11 is provided so that the time constant can be changed depending on whether the lock is locked or not, and the output is led to the voltage controlled oscillator 4. 12 is PLL 1
This lock detection circuit consists of a NAND gate 13 that receives the output of the phase comparator 9 as an input, an integrating circuit 14, and a transistor 15 whose conduction is controlled by the output of the integrating circuit 14, and the PLL 1 is unlocked. When one of the outputs U and D of the phase comparator 9 becomes L level, the output of the NAND gate 13 becomes H level and the transistor 15 becomes conductive, and the collector is at L level, but PLL 1 is locked and the phase comparison is performed. When the outputs U and D of the device 9 both go to H level, the output of the NAND gate 13 goes to L level, so that the transistor 15 becomes non-conductive and generates an H level lock signal at the collector. 16
1 is a one-shot multivibrator that operates on the rising edge of a lock signal and generates a lock pulse.
7 is set by the rising edge of the output of the one-shot multivibrator 16, and the channel selection start key 1 is pressed.
Flip-flop 19 reset by operation 8
The time constant switching circuit is composed of a relay 21 which is excited by the conduction of the transistor 20 by the set output Q, and the relay contact 11 of the reduction filter 6 is switched by the relay 21 being excited. Reference numeral 22 denotes a muting control circuit, to whose set terminal the tuning start key 18 is connected, and to its reset terminal the output of an AND gate 22 whose two inputs are the Q output of the flip-flop 19 and the output of the one-shot multivibrator 16. The set output Q is applied to the muting circuit 8 as a muting signal. Next, the operation of the present invention having such a configuration will be explained. When receiving another station from the station currently being received, the currently broadcasting station is selected by sequentially changing the value of the frequency division ratio setting means 3 by 1 by operating the selection start key 18. First, from the receiving state, press the channel selection start key 1
8 to change the value of division ratio setting means 3 from N to N+1.
We will explain in case the changes have been made. When the channel selection start key 18 is operated and a start pulse is generated, the value of the frequency division ratio setting means 3 is changed, and at the same time the programmable frequency divider 2
The frequency division ratio N of is changed and PLL 1 is operated, but
At this time, by operating the tuning start key 18, the flip-flop 19 of the time constant switching circuit 17 is reset, and the flip-flop 2 of the muting control circuit 22 is reset.
4 is set, the relay 21, which was energized in the receiving state, is demagnetized, the relay contact 11 is opened, the time constant of the reduction filter 6 is switched to a smaller value, and a muting signal is generated, cutting off the audio path. do. When PLL 1 is locked after passing through a transient response state, both outputs U and D of phase comparator 9 become H level, and a lock signal is generated from lock detection circuit 12 and output from one-shot multivibrator 16. When the first lock pulse P1 is generated, the flip-flop 19 of the time constant switching circuit 17 is set in response to the rising edge of this lock pulse, the relay 21 is energized, and the relay contact 11 is closed, thereby reducing the filter 6. Set the time constant to a large value. At this time, due to the change in the time constant, the output of the reduction filter 6 changes somewhat during the transient response [second transient response T 2 ], as shown in FIG. Then, since the oscillation frequency of the voltage controlled oscillator 4 changes, the PLL 1 becomes unlocked, one output of the digital phase comparator 9 becomes L level, and the output of the lock detection circuit 12 becomes L level. By the way, this second transient response
When T 2 ends, PLL 1 locks and outputs U and D of phase comparator 9 both go to H level, and NAND
As the output of gate 13 becomes L level,
Transistor 15 becomes non-conductive, and the collector becomes H.
Generates a level lock signal. Therefore, this H
A second lock pulse P 2 is generated from the one-shot multivibrator 16 based on the level lock signal.
is generated. At this time, the flip-flop 19 is set by the first lock pulse P1 , the Q output is at H level, and the H level lock signal of the second lock pulse P2 is applied to the AND gate 22. Therefore, a reset signal is applied from the AND gate 22 to the flip-flop 24. Therefore, the muting signal is canceled, and if a broadcast is being received at this time, it will be reproduced from the speaker 7. In this way, the noise generated during time constant switching is blocked. As mentioned above, the receiver of the present invention uses a local oscillation circuit.
It is configured with a PLL, and is configured so that the time constant of the reducing filter is switched depending on locking and unlocking of the PLL, and the muting is canceled by the second lock pulse generated after switching the time constant, so that the time constant can be switched. This makes it possible to reliably prevent noise from occurring.
第1図は本考案に係る受信機の従来の構成を示
す図、第2図は第1図要部の動作波形図、第3図
は第1図要部の構成図、第4図は第1図要部の動
作波形図、第5図は本考案の要部構成図、第6図
は第5図要部の動作波形図である。
1……PLL、6……低減濾波器、9……位相
比較器、10……チヤージポンプ、12……ロツ
ク検出回路、17……時定数切換回路、22……
ミユーテイング制御回路。
Fig. 1 is a diagram showing the conventional configuration of the receiver according to the present invention, Fig. 2 is an operational waveform diagram of the main part of Fig. 1, Fig. 3 is a block diagram of the main part of Fig. 1, and Fig. 4 is a diagram of the main part of Fig. 1. FIG. 1 is an operational waveform diagram of the main part, FIG. 5 is a configuration diagram of the main part of the present invention, and FIG. 6 is an operational waveform diagram of the main part of FIG. 1 ...PLL, 6...Reducing filter, 9...Phase comparator, 10...Charge pump, 12...Lock detection circuit, 17...Time constant switching circuit, 22...
Muting control circuit.
Claims (1)
され、分周比を変更することにより局部発振周波
数を制御する受信機に於いて、PLLがロツクさ
れたことを検出するロツク検出手段と、前記分周
比の変更に伴う前記PLLを構成する低減濾波器
の第1の過渡応答終了後、前記ロツク検出手段に
よる第1のロツク検出出力にて前記PLLを構成
する前記低減濾波器の時定数を切換える時定数切
換手段と、この時定数切換手段の切換に伴う前記
PLLを構成する低減濾波器の第2の過渡応答終
了後、前記ロツク検出手段による第2のロツク検
出出力にて、ミユーテイング制御回路を作動し、
ミユーテイング信号を解除することにより前記時
定数切換時の雑音を防止したことを特徴とする受
信機。 In a receiver in which the local oscillation circuit is composed of a PLL (phase locked loop) and the local oscillation frequency is controlled by changing the frequency division ratio, a lock detection means for detecting that the PLL is locked; After the first transient response of the reduction filter constituting the PLL due to a change in frequency ratio is completed, the time constant of the reduction filter constituting the PLL is switched by the first lock detection output from the lock detection means. A time constant switching means and the above-mentioned
After the second transient response of the reduction filter constituting the PLL is completed, a muting control circuit is activated by the second lock detection output from the lock detection means,
A receiver characterized in that noise at the time of switching the time constant is prevented by canceling the muting signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17079078U JPS6311770Y2 (en) | 1978-12-06 | 1978-12-06 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17079078U JPS6311770Y2 (en) | 1978-12-06 | 1978-12-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5587746U JPS5587746U (en) | 1980-06-17 |
JPS6311770Y2 true JPS6311770Y2 (en) | 1988-04-06 |
Family
ID=29174096
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17079078U Expired JPS6311770Y2 (en) | 1978-12-06 | 1978-12-06 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6311770Y2 (en) |
-
1978
- 1978-12-06 JP JP17079078U patent/JPS6311770Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5587746U (en) | 1980-06-17 |
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