JPS6241505Y2 - - Google Patents
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- Publication number
- JPS6241505Y2 JPS6241505Y2 JP9579181U JP9579181U JPS6241505Y2 JP S6241505 Y2 JPS6241505 Y2 JP S6241505Y2 JP 9579181 U JP9579181 U JP 9579181U JP 9579181 U JP9579181 U JP 9579181U JP S6241505 Y2 JPS6241505 Y2 JP S6241505Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- level
- floating
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000605 extraction Methods 0.000 claims description 25
- 230000001934 delay Effects 0.000 claims description 5
- 239000000284 extract Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 14
- 238000005259 measurement Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 238000011179 visual inspection Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000001502 supplementing effect Effects 0.000 description 1
Landscapes
- Investigating Or Analysing Materials By Optical Means (AREA)
- Picture Signal Circuits (AREA)
- Closed-Circuit Television Systems (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Description
【考案の詳細な説明】
本考案は映像信号処理回路に関する。例えば、
ITVカメラ等を利用した金属表面の視覚計測、目
視検査、画像処理等ではスペースの関係で第１図
側面図に示すように、照明Ｌで斜め方向θから金
属表面MSを照らし、これをITVカメラにより撮
影する場合は、被検金属表面MS上の照度は第２
図に示すように分布するので、ITVカメラの映像
信号はその影響を受けて出力信号に歪を生ずると
いうように、検出器であるITVカメラと光源、又
は被写体面照度の関係で画面上に明暗が生ずる場
合があり、そのために対象抽出点の弁別が困難と
なり、信号処理を行なうにも映像信号のバラツキ
の影響を受けることになる。[Detailed Description of the Invention] The present invention relates to a video signal processing circuit. for example,
For visual measurement, visual inspection, image processing, etc. of metal surfaces using an ITV camera, etc., due to space constraints, the metal surface MS is illuminated from an oblique direction θ with a light L, as shown in the side view of Figure 1, and then the ITV camera illuminates the metal surface MS. When photographing with
As shown in the figure, the video signal of the ITV camera is affected by this, causing distortion in the output signal.The brightness and darkness on the screen may vary depending on the relationship between the ITV camera, which is the detector, the light source, or the illuminance of the subject surface. may occur, which makes it difficult to discriminate the target extraction point, and signal processing is also affected by variations in the video signal.
映像画面１は第３図に示すように、水平走査線
Ｘ−X′とその走査線の集合であるフイールド信
号Ｙ−Y′からなる、理想的には水平走査線Ｘ−
X′が水平ブランキング信号４に対し信号パター
ン５のレベルであり、フイールド信号Ｙ−Y′は
垂直ブランキング信号２に対しフイールド信号３
であれば、画面１はほゞ均一な明るさとなるので
あるが、照度分布や撮像管の感度不均一に基因す
るシエーデイング等のために、第４図Ａ，Ｂに示
すように、Ｘ−X′方向が信号６となつたり、Ｙ
−Y′方向が信号７となると、画面に明暗が生じ
て弁別性は低下し、処理は困難となつてくる。ま
た第５図Ａに示すように、Ｙ部分がかりに信号パ
ターン８とすると、９のように同一形状の被写体
に対しても映像信号特性が異なつて了い、設定レ
ベル１０で比較しようとしても不可能となり、逆
に第５図Ｂに示すようにY′が１１のように信号
レベルが低いと、弁別レベル１２が低下して判別
が困難となる。 As shown in FIG. 3, the video screen 1 consists of a horizontal scanning line X-X' and a field signal Y-Y' which is a set of the scanning lines.
X' is the level of signal pattern 5 with respect to horizontal blanking signal 4, and field signal Y-Y' is the level of field signal 3 with respect to vertical blanking signal 2.
In this case, screen 1 would have approximately uniform brightness, but due to shading caused by illuminance distribution and uneven sensitivity of the image pickup tube, the ' direction becomes signal 6, Y
When the -Y' direction becomes signal 7, brightness and darkness occur on the screen, the discrimination is reduced, and processing becomes difficult. Furthermore, as shown in FIG. 5A, if the signal pattern 8 is applied to the Y portion, the video signal characteristics will be different even for subjects with the same shape as shown in 9, and it will be impossible to compare them at the setting level 10. On the other hand, when the signal level is low, such as Y' being 11 as shown in FIG. 5B, the discrimination level 12 is lowered and discrimination becomes difficult.
本考案はこのような事情に鑑みて提案されたも
ので、照度分布やシエーデイングの影響を除去す
る画像処理回路を提供することを目的とし、映像
信号中の同期信号を除去する搬送波除去回路の出
力信号から輝度信号の低域成分を抽出する浮動値
抽出回路、この浮動値抽出回路により抽出された
信号のレベルを補正するゲイン補正回路、このゲ
イン補正回路により補正された信号を１走査線分
だけ遅延させる1H遅延回路、およびこの1H遅延
回路の出力信号と映像信号とを入力し映像信号の
歪波形に対する浮動設定値を出力する歪除去演算
回路よりなる浮動値設定機能回路と、前記搬送波
除去回路の出力信号のレベルを補正するゲイン補
正回路、このゲイン補正回路により補正された信
号から歪波形のピーク値を１走査線毎に検出する
ピークホールド回路、このピークホールド回路に
より得られた前記ピーク値に応じて設定レベルを
出力する２値設定用比較レベル抽出回路、および
この２値設定用比較レベル抽出回路の出力信号を
１走査線分だけ遅延させる1H遅延回路よりなる
２値化設定機能回路と、前記浮動値設定機能回路
から得られる前記映像信号の歪波形に対する浮動
設定値の出力信号、および前記２値化設定機能回
路から得られる前記２値設定用比較レベル抽出回
路の出力信号を１走査線分だけ遅延ささせた出力
信号を入力し両者を対比して最適２値化を行なう
２値化回路とを具備してなることを特徴とする。 The present invention was proposed in view of these circumstances, and aims to provide an image processing circuit that removes the effects of illuminance distribution and shading. A floating value extraction circuit that extracts the low frequency component of the luminance signal from the signal, a gain correction circuit that corrects the level of the signal extracted by this floating value extraction circuit, and a signal corrected by this gain correction circuit for one scanning line. a floating value setting function circuit comprising a 1H delay circuit for delaying, a distortion removal calculation circuit that inputs the output signal of the 1H delay circuit and the video signal and outputs a floating setting value for the distorted waveform of the video signal; and the carrier wave removal circuit. a gain correction circuit that corrects the level of the output signal of the gain correction circuit; a peak hold circuit that detects the peak value of the distorted waveform for each scanning line from the signal corrected by the gain correction circuit; and the peak value obtained by the peak hold circuit. a binary setting comparison level extraction circuit that outputs a setting level in accordance with the binary setting comparison level extraction circuit; and a 1H delay circuit that delays the output signal of the binary setting comparison level extraction circuit by one scanning line; , one scan of the output signal of the floating setting value for the distorted waveform of the video signal obtained from the floating value setting function circuit, and the output signal of the comparison level extraction circuit for binary setting obtained from the binarization setting function circuit. The present invention is characterized in that it is equipped with a binarization circuit that inputs an output signal delayed by a line segment, compares the two, and performs optimal binarization.
本考案の一実施例を図面について説明すると、
第６図はその回路構成を示すブロツク線図、第７
図Ａ，Ｂ，Ｃ，Ｄは第６図における各部の出力信
号波形図、第８図は第６図による映像信号波形の
白レベルと黒レベルの関係を示す線図、第９図は
第６図の出力信号Ｂの波形図である。 An embodiment of the present invention will be explained with reference to the drawings.
Figure 6 is a block diagram showing the circuit configuration, Figure 7
Figures A, B, C, and D are output signal waveform diagrams of each part in Figure 6, Figure 8 is a diagram showing the relationship between the white level and black level of the video signal waveform in Figure 6, and Figure 9 is a diagram showing the relationship between the white level and black level of the video signal waveform in Figure 6. 3 is a waveform diagram of output signal B in the figure. FIG.
まず、第６図において、ＡはITVカメラの出力
映像信号、１３は搬送波除去回路、１４はゲイン
補正回路、１５はピークホールド回路、１６は
Ｈ・Ｖ同期分離回路（ピークホールドリセツト出
力）、１７は２値化設定用比較レベル抽出回路、
１８は1H遅延回路、１９は浮動値抽出回路、２
０はゲイン補正回路、２１は1H遅延回路で２２
は歪除去演算回路、２３は２値化回路、Ｂは２値
化回路２３の出力信号である。 First, in FIG. 6, A is the output video signal of the ITV camera, 13 is a carrier removal circuit, 14 is a gain correction circuit, 15 is a peak hold circuit, 16 is an H/V synchronization separation circuit (peak hold reset output), 17 is a comparison level extraction circuit for binarization setting,
18 is a 1H delay circuit, 19 is a floating value extraction circuit, 2
0 is the gain correction circuit, 21 is the 1H delay circuit, and 22
23 is a distortion removal calculation circuit, 23 is a binarization circuit, and B is an output signal of the binarization circuit 23.
このような回路において、１３〜１８は協働し
て２値化設定機能回路を、１９〜２２は協働して
浮動値設定機能回路をそれぞれ構成する。 In such a circuit, 13 to 18 cooperate to form a binarization setting function circuit, and 19 to 22 cooperate to form a floating value setting function circuit.
まず、浮動値設定機能回路は、映像信号中の同
期信号（水平、垂直ブランキング信号４，２）を
除去する搬送波除去回路１３と、水平ブランキン
グ信号が除去されたＸ−X′信号から輝度信号の
低域成分を抽出する浮動値抽出回路１９と、この
浮動値抽出回路１９で得られた信号のレベルを補
正するゲイン補正回路２０（第７図Ａの２５のレ
ベルは補正後のレベルであり、浮動値抽出回路１
９から出力されるレベルはこれより低い）と、補
正された信号を１走査線分だけ遅延させる1H遅
延回路と、１走査線分後の歪信号（Ｘ−X′方向
の映像信号）２４−浮動設定値２５を行なう歪除
去演算回路２２とにより構成されているので、第
７図Ａに示すように入力映像信号Ａの歪波形２４
に対して浮動設定値２５を出力するので、その結
果は後記するように、第７図Ｂに示すように平均
化された改善波形２６が得られる。 First, the floating value setting function circuit includes a carrier wave removal circuit 13 that removes synchronization signals (horizontal and vertical blanking signals 4 and 2) from the video signal, and a carrier wave removal circuit 13 that removes the synchronization signal (horizontal and vertical blanking signals 4 and 2) from the video signal, and a A floating value extraction circuit 19 extracts the low-frequency components of the signal, and a gain correction circuit 20 corrects the level of the signal obtained by the floating value extraction circuit 19 (the level 25 in FIG. 7A is the level after correction). Yes, floating value extraction circuit 1
9), a 1H delay circuit that delays the corrected signal by one scanning line, and a distorted signal after one scanning line (video signal in the X-X' direction) 24- As shown in FIG. 7A, the distorted waveform 24 of the input video signal A is
Since the floating setting value 25 is outputted for , an averaged improved waveform 26 as shown in FIG. 7B is obtained as a result, as will be described later.
すなわち、浮動値抽出回路１９は積分方式、ダ
イオード検波方式等により、浮動設定値２５を抽
出し、ゲイン補正回路２０で補正したのち、1H
遅延回路２１で1H（１走査線）遅延させて、1H
後の映像信号と歪除去演算回路２２で比較され
る。これは、映像信号は1H前後では通常同等の
信号形態を有するものであるから、設定値の完全
同期の作用を行なうことができることによるもの
で、ピークホールドの作用と同様である。 That is, the floating value extraction circuit 19 extracts the floating set value 25 using an integral method, diode detection method, etc., corrects it in the gain correction circuit 20, and then converts it to 1H.
Delayed by 1H (1 scanning line) by delay circuit 21, 1H
It is compared with the subsequent video signal in the distortion removal calculation circuit 22. This is because the video signal usually has the same signal form around 1H, so it is possible to perform the function of perfect synchronization of the setting values, which is similar to the effect of peak hold.
こうして歪除去演算回路２２の出力する改善波
形２６が得られるが、この波形は未だ十分に弁別
性を有する波形としては完全ではなく、Ｙ−
Y′方向の分布の歪が除去されていないものであ
る。そこで、本考案回路においてはさらに２値化
設定機能回路を設けている。この２値化設定機能
回路は、前記搬送波除去回路１３の出力信号のレ
ベルを補正するゲイン補正回路１４と、このゲイ
ン補正回路１４により補正された信号から歪波形
のピーク値を１走査線毎に検出するピークホール
ド回路１５と、このピークホールド回路１５によ
り得られた前記ピーク値に応じて設定レベルを出
力する２値設定用比較レベル抽出回路１７と、こ
の２値設定用比較レベル抽出回路１７の出力信号
を１走査線分だけ遅延させる1H遅延回路１８と
により構成され、1H走査線ごとに、第７図Ｃに
示すように歪波形２７のピークレベル２８を検出
保持し、Ｙ−Y′方向でこれを平均化するように
する。 In this way, an improved waveform 26 output from the distortion removal calculation circuit 22 is obtained, but this waveform is still not perfect as a waveform with sufficient discrimination, and Y-
The distortion of the distribution in the Y′ direction has not been removed. Therefore, in the circuit of the present invention, a binarization setting function circuit is further provided. This binarization setting function circuit includes a gain correction circuit 14 that corrects the level of the output signal of the carrier wave removal circuit 13, and a peak value of the distorted waveform from the signal corrected by the gain correction circuit 14 for each scanning line. A peak hold circuit 15 for detecting, a comparison level extraction circuit 17 for binary setting that outputs a set level according to the peak value obtained by this peak hold circuit 15, and a comparison level extraction circuit 17 for binary setting. It is composed of a 1H delay circuit 18 that delays the output signal by one scanning line, detects and holds the peak level 28 of the distorted waveform 27 for each 1H scanning line as shown in FIG. Let's average this out.
そのためにピークホールド回路１５で歪波形２
７のピークレベルＶ２８を検出し、２値設定用比
較レベル抽出回路１７で演算してピークレベルＶ
の大小に対応した設定レベルを出力する。そし
て、この出力を1H遅延回路１８を経て２値化回
路２３に入力し、こゝで歪除去演算回路２２の出
力と比較し、２値化演算を行なうことにより、ど
のような入力波形でも第７図Ｄの２９に示すよう
な２値化波形として出力する。 For this purpose, the peak hold circuit 15 generates a distorted waveform 2.
7 is detected, and the comparison level extraction circuit 17 for binary setting calculates the peak level V28.
Outputs the setting level corresponding to the size of. Then, this output is input to the binarization circuit 23 via the 1H delay circuit 18, where it is compared with the output of the distortion removal calculation circuit 22, and by performing a binarization calculation, any input waveform can be It is output as a binarized waveform as shown at 29 in Figure 7D.
さらに、上記した２値化設定機能回路の作用を
補充すると、第８図に示すように走査線信号３０
は、白レベル３１と黒レベル３２の情報として単
純に表わすことができるので、白レベル３１に対
する黒レベル３２の変化は同図実線３４に示すよ
うになり、白レベルが低いときは黒レベルはペデ
ツサルレベル３３で特性が一定となり、それ以上
では非線形特性３４を示す。したがつて破線３６
に示す近似特性を利用して、ペデツサルレベル３
３のオフセツトレベルｂ３５を考慮した下記特性
式；
ｙ＝ａ（ｘ−ｂ）（たゞしｂは定数）
を採用することができる。 Furthermore, by supplementing the function of the above-mentioned binarization setting function circuit, the scanning line signal 30 as shown in FIG.
can be expressed simply as information about the white level 31 and the black level 32, so the change in the black level 32 with respect to the white level 31 is shown by the solid line 34 in the same figure, and when the white level is low, the black level is the pedestal level. At 33, the characteristics become constant, and above that, nonlinear characteristics 34 are exhibited. Therefore, the dashed line 36
Using the approximation characteristics shown in pedestal level 3
The following characteristic equation considering the offset level b35 of 3: y=a(x-b) (where b is a constant) can be adopted.
こゝで、オフセツトレベルｂは被写体によるコ
ントラスト差等の特性により異なるが、歪除去演
算回路２２の出力信号２６に対して、第９図に示
すように、２値化設定レベル３８を対比させ、２
値化回路２３で２値化演算を行なうことにより、
２値化波形２９を出力し、画面全体の補正で映像
信号の弁別性の向上と後続する信号処理の単純化
を達成する。 Although the offset level b differs depending on the characteristics such as the contrast difference of the subject, the binarization setting level 38 is compared with the output signal 26 of the distortion removal calculation circuit 22 as shown in FIG. ,2
By performing a binarization operation in the digitization circuit 23,
A binarized waveform 29 is output, and the entire screen is corrected to improve the discriminability of the video signal and to simplify the subsequent signal processing.
したがつて、このような回路によれば、ITVカ
メラ等を利用した計測において、照度分布、シエ
ーデイング等に基因する映像信号の歪波形を最適
２値化により改善して計測の容易化を図ることが
できるので、固体カメラ、撮像管カメラ、視覚用
センサ等ITVを利用する計測全般において画像処
理手段として広くこれを利用することができる。 Therefore, according to such a circuit, it is possible to improve the distorted waveform of a video signal caused by illuminance distribution, shading, etc. by optimal binarization in measurement using an ITV camera, etc., thereby facilitating measurement. Therefore, it can be widely used as an image processing means in general measurements using ITV, such as solid-state cameras, image pickup tube cameras, and visual sensors.
要するに本考案によれば、映像信号を入力しそ
の歪波形の浮動値を抽出する浮動値抽出回路、ゲ
イン補正回路、1H遅延回路、歪除去演算回路よ
りなる浮動値設定機能回路と、上記映像信号を入
力するゲイン補正回路、ピークホールド回路、ピ
ークホールド回路の出力の大小に対応する設定値
を出力する２値設定用比較レベル抽出回路、1H
遅延回路よりなる２値化設定機能回路と、上記浮
動値設定機能回路の出力および上記２値化設定機
能回路の出力を入力し両者を対比して最適２値化
を行なう２値化回路とを具えたことにより、歪波
形の改善を図る映像信号処理回路を得るから、本
考案は産業上極めて有益なものである。 In short, according to the present invention, a floating value setting function circuit consisting of a floating value extraction circuit for inputting a video signal and extracting a floating value of its distorted waveform, a gain correction circuit, a 1H delay circuit, and a distortion removal calculation circuit; Gain correction circuit, peak hold circuit, comparison level extraction circuit for binary setting that outputs the setting value corresponding to the magnitude of the output of the peak hold circuit, 1H
A binarization setting function circuit comprising a delay circuit, and a binarization circuit inputting the output of the floating value setting function circuit and the output of the binarization setting function circuit and comparing the two to perform optimal binarization. The present invention is industrially extremely useful because it provides a video signal processing circuit that improves distorted waveforms.
第１図は公知のITVによる金属表面の目視検査
要領を示す側面図、第２図は第１図による照度分
布図、第３図は第１図における画面と映像信号を
示す説明図、第４図Ａ，Ｂは第３図における走査
信号とフイールド信号の歪を示す線図、第５図
Ａ，Ｂは第４図の部分拡大図、第６図は本考案の
一実施例を示すブロツク線図、第７図Ａ，Ｂ，
Ｃ，Ｄは第６図における各部の出力信号波形図、
第８図は第６図による映像信号波形の白レベルと
黒レベルの関係を示す線図、第９図は第６図の２
値化回路の作用を示す説明図である。
Ａ……入力映像信号、２……出力映像信号、１
３……搬送波除去回路、１４……ゲイン補正回
路、１５……ピークホールド回路、１６……Ｈ・
Ｖ同期分離回路、１７……２値設定用比較レベル
抽出回路、１８……1H遅延回路、１９……浮動
値抽出回路、２０……ゲイン補正回路、２１……
1H遅延回路、２２……歪除去演算回路、２３…
…２値化回路、２４……歪波形、２５……浮動設
定値、２６……２２の出力波形、２７……歪波
形、２８……ピークレベルＶ、２９……２３の出
力波形、３０……走査線信号、３１……白レベ
ル、３２……黒レベル、３３……ペデツサルレベ
ル、３４……非線形特性、３５……オフセツトレ
ベル、ｂ，３６……近似特性、３８……２値化設
定レベル。
Figure 1 is a side view showing the procedure for visual inspection of metal surfaces using a known ITV, Figure 2 is an illuminance distribution diagram based on Figure 1, Figure 3 is an explanatory diagram showing the screen and video signal in Figure 1, and Figure 4 is an explanatory diagram showing the screen and video signal in Figure 1. Figures A and B are diagrams showing the distortion of the scanning signal and field signal in Figure 3, Figures 5A and B are partially enlarged views of Figure 4, and Figure 6 is a block diagram showing an embodiment of the present invention. Figure, Figure 7 A, B,
C and D are output signal waveform diagrams of each part in Fig. 6,
Figure 8 is a diagram showing the relationship between the white level and black level of the video signal waveform according to Figure 6, and Figure 9 is a diagram showing the relationship between the white level and black level of the video signal waveform according to Figure 6.
FIG. 3 is an explanatory diagram showing the operation of the value converting circuit. A...Input video signal, 2...Output video signal, 1
3... Carrier removal circuit, 14... Gain correction circuit, 15... Peak hold circuit, 16... H.
V synchronization separation circuit, 17... Comparison level extraction circuit for binary setting, 18... 1H delay circuit, 19... Floating value extraction circuit, 20... Gain correction circuit, 21...
1H delay circuit, 22...Distortion removal calculation circuit, 23...
... Binarization circuit, 24 ... Distorted waveform, 25 ... Floating setting value, 26 ... Output waveform of 22, 27 ... Distorted waveform, 28 ... Peak level V, 29 ... Output waveform of 23, 30 ... ...Scanning line signal, 31... White level, 32... Black level, 33... Pedestal level, 34... Nonlinear characteristics, 35... Offset level, b, 36... Approximate characteristics, 38... Binarization setting level.
Claims (1)
路の出力信号から輝度信号の低域成分を抽出する
浮動値抽出回路、この浮動値抽出回路により抽出
された信号のレベルを補正するゲイン補正回路、
このゲイン補正回路により補正された信号を１走
査線分だけ遅延させる1H遅延回路、およびこの
1H遅延回路の出力信号と映像信号とを入力し映
像信号の歪波形に対する浮動設定値を出力する歪
除去演算回路よりなる浮動値設定機能回路と、前
記搬送波除去回路の出力信号のレベルを補正する
ゲイン補正回路、このゲイン補正回路により補正
された信号から歪波形のピーク値を１走査線毎に
検出するピークホールド回路、このピークホール
ド回路により得られた前記ピーク値に応じて設定
レベルを出力する２値設定用比較レベル抽出回
路、およびこの２値設定用比較レベル抽出回路の
出力信号を１走査線分だけ遅延させる1H遅延回
路よりなる２値化設定機能回路と、前記浮動値設
定機能回路から得られる前記映像信号の歪波形に
対する浮動設定値の出力信号、および前記２値化
設定機能回路から得られる前記２値設定用比較レ
ベル抽出回路の出力信号を１走査線分だけ遅延さ
せた出力信号を入力し両者を対比して最適２値化
を行なう２値化回路とを具備してなることを特徴
とする映像信号処理回路。 a floating value extraction circuit that extracts a low frequency component of a luminance signal from an output signal of a carrier removal circuit that removes a synchronization signal in a video signal; a gain correction circuit that corrects the level of the signal extracted by the floating value extraction circuit;
A 1H delay circuit that delays the signal corrected by this gain correction circuit by one scanning line;
a floating value setting function circuit consisting of a distortion removal calculation circuit that inputs the output signal of the 1H delay circuit and the video signal and outputs a floating set value for the distorted waveform of the video signal; and a floating value setting function circuit that corrects the level of the output signal of the carrier wave removal circuit. a gain correction circuit; a peak hold circuit that detects the peak value of the distorted waveform for each scanning line from the signal corrected by the gain correction circuit; and a peak hold circuit that outputs a set level according to the peak value obtained by the peak hold circuit. A binary setting function circuit consisting of a comparison level extraction circuit for binary setting, and a 1H delay circuit that delays the output signal of the comparison level extraction circuit for binary setting by one scanning line, and the floating value setting function circuit. An output signal of a floating setting value for the distorted waveform of the obtained video signal and an output signal obtained by delaying the output signal of the comparison level extraction circuit for binary setting obtained from the binary setting function circuit by one scanning line. 1. A video signal processing circuit comprising: a binarization circuit that inputs a signal, compares the two, and performs optimal binarization.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9579181U JPS583680U (en) | 1981-06-27 | 1981-06-27 | Video signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9579181U JPS583680U (en) | 1981-06-27 | 1981-06-27 | Video signal processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS583680U JPS583680U (en) | 1983-01-11 |
| JPS6241505Y2 true JPS6241505Y2 (en) | 1987-10-23 |
Family
ID=29890683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9579181U Granted JPS583680U (en) | 1981-06-27 | 1981-06-27 | Video signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS583680U (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2521680B2 (en) * | 1986-12-08 | 1996-08-07 | 株式会社東芝 | Electronic endoscopic device |
| EP1333273A4 (en) * | 2000-11-10 | 2011-04-06 | Arkray Inc | Measuring method and instrument comprising image sensor |
-
1981
- 1981-06-27 JP JP9579181U patent/JPS583680U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS583680U (en) | 1983-01-11 |
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