JPS6239030A - Semiconductor chip carrier - Google Patents
Semiconductor chip carrierInfo
- Publication number
- JPS6239030A JPS6239030A JP17881885A JP17881885A JPS6239030A JP S6239030 A JPS6239030 A JP S6239030A JP 17881885 A JP17881885 A JP 17881885A JP 17881885 A JP17881885 A JP 17881885A JP S6239030 A JPS6239030 A JP S6239030A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- mounting
- base material
- insulating substrate
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明はビングリッドアレイ（ＰＧ＾）とかり−ドレス
チップキャリア（ＬＣＣ）等の半導体チップキャリアに
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor chip carriers such as bin grid arrays (PG^) and dressed chip carriers (LCC).
［背景技術］
従来より、プリント配線板をチップキャリアとして半導
体チップが直接実装されているが、この半導体チップを
実装するために、プリント配線板にミーリング加工など
の機械的切削加工により実装用凹部が形成されている。[Background Art] Conventionally, semiconductor chips have been directly mounted using printed wiring boards as chip carriers, but in order to mount these semiconductor chips, recesses for mounting are created in the printed wiring board by mechanical cutting such as milling. It is formed.
一方、プリント配線板は絶縁基板が通常、紙、布、〃フ
ス布などを基材とする樹脂板で形成されており、吸湿性
を有して内部に湿気を通すため、この湿気が実装用凹部
内に実装した半導体チップに作用して信頼性を着しく低
下させる恐れがあった。このため実装用凹部の内面に金
属めっきを施すことが行なわれている。On the other hand, in printed wiring boards, the insulating substrate is usually made of a resin board based on paper, cloth, or cloth, which has hygroscopic properties and allows moisture to pass through inside, so this moisture is used for mounting. There was a fear that this would act on the semiconductor chip mounted in the recess and seriously reduce its reliability. For this reason, metal plating is performed on the inner surface of the mounting recess.
しかしながら機械的切削加工により実装用凹部を形成し
た場合には、実装用凹部の底部において切削加工の際の
衝撃で基材と樹脂層が剥離して絶縁層破壊が生じてしま
い、めっき液が絶縁基板内に浸透し、めっき液の酸、ア
ルカリ成分により絶ｋｋ基板の絶縁性が低下したり、電
蝕が発生したり、又半導体チップに悪影響を与えたりす
るという問題があった。However, when the mounting recess is formed by mechanical cutting, the impact during the cutting process causes the base material and the resin layer to peel off at the bottom of the mounting recess, causing breakdown of the insulation layer, which causes the plating solution to become insulating. There are problems in that the plating solution penetrates into the substrate and the insulation properties of the plating substrate deteriorate due to the acid and alkaline components of the plating solution, electrolytic corrosion occurs, and it also has an adverse effect on the semiconductor chip.
［発明の目的１
本発明は上記事情に鑑みて為されたものであり、その目
的とするところは、半導体チップの実装用凹部を８！械
的加工により形成しても実装用凹部の絶Ｍ層破壊が極め
て少なく、金属めっき層を形成する際に、めっき液が絶
縁基板内に浸透することがなく、実装−歓る半導体チッ
プに悪影響を与えることがなく、信頼性を向上させる半
導体チップキャリアを提供することにある。[Objective of the Invention 1 The present invention has been made in view of the above-mentioned circumstances, and its object is to form a concave portion for mounting a semiconductor chip in an 8! Even when formed by mechanical processing, there is extremely little destruction of the M layer in the mounting recess, and when forming a metal plating layer, the plating solution does not penetrate into the insulating substrate, which has no negative impact on the semiconductor chip that is being mounted. The object of the present invention is to provide a semiconductor chip carrier that improves reliability without causing any damage.
［発明の開示］
本発明の半導体ナツプキャリアは、絶縁基板１の表面に
回路パターン２を設けてプリント配線板３を形成し、プ
リント配線板３の表面に機械的切削加工により半導体チ
ップ４の実装用凹部５を形成しｔこ半導体チップキャリ
アにおい−Ｃ１絶縁塞板１に基材を含まない樹脂Ｎ６を
設けて実装用凹部５に基材を含まない樹脂Ｎ６を露出さ
せ、この実装用凹部５内に／に属めっき／［７を設けて
成るものであり、この構成により上記目的を達成できた
ものである。即ち、Ｗｉ機械的切削加工より実装用凹部
５を形成する際に、実装用凹部に基材を含まないυ（脂
／１６を露出させるので、従来のように基材とム（脂閤
の密着破壊など起こらず、実装用凹部５の絶縁層破壊が
生じないものであり、従って金属めっきＮＪ７を形成す
る際にめっき液が実装用凹部５から絶縁基板１内に浸透
することがなく、基板汚染、絶縁性の低下を抑えること
ができるものである。[Disclosure of the Invention] The semiconductor nap carrier of the present invention includes a circuit pattern 2 provided on the surface of an insulating substrate 1 to form a printed wiring board 3, and a semiconductor chip 4 mounted on the surface of the printed wiring board 3 by mechanical cutting. A recess 5 is formed in the semiconductor chip carrier. A resin N6 not containing a base material is provided on the insulating cover plate 1, and the resin N6 not containing a base material is exposed in the recess 5 for mounting. The above-mentioned object can be achieved with this configuration. That is, when the mounting recess 5 is formed by Wi mechanical cutting, the mounting recess 5 is exposed to υ (fat/16), which does not contain the base material, so that the base material and the MU (grain paste) are not in close contact with each other as in the conventional method. Therefore, when forming the metal plating NJ7, the plating solution does not permeate into the insulating substrate 1 from the mounting recess 5, thereby preventing substrate contamination. , it is possible to suppress a decrease in insulation properties.
以下、本発明を添付の図面に示す実施例に基づいて説明
する。絶Ａｊ基板１は＃４’ｉなどの金属箔を張った紙
フエノール樹脂積層板、紙エポキシ樹脂積層板などの金
属箔張り積層板であり、この絶縁基板１を複数枚のプリ
プレグを積層成形して形成する際に、樹脂板を所要枚数
介在させて絶縁基板１内の表面に近い側１こ基材を含ま
ない樹脂層６を設けている。この絶ｊ＆基板１は両面金
属箔張り積層板であり、穴明は加工して形成したスルホ
ール８にスルホールめっき／！Ｉ９を形成し、両面の金
属箔にエツチングなどを常法の手段を施すことにより回
路パターン２を形成してプリント配線板３を形成してい
る。このプリント配線板３の表面にはミー リング加工
など機械的切削加工によって半導体チップ４の実装用凹
部５を設けている。機械的切削加工は基材を含まない樹
脂層６に達する深さまで行い、実装用凹ｆｆ１Ｓｓの底
部には樹脂／［６を露出させている。この実装用ｉ！１
部５はスルホール８を形成する際に、同時に形成するよ
うにしてもよい。樹脂Ｎ６は基材を含んでいないので、
切削加工における切断ストレスが極めて小さくなり、従
来の如く基材と樹脂間の密着破壊が殆ど起こらず、従っ
て実装用凹部５の絶縁層破壊が生じていない。Hereinafter, the present invention will be described based on embodiments shown in the accompanying drawings. The insulating substrate 1 is a metal foil-covered laminate such as a paper phenol resin laminate or a paper epoxy resin laminate covered with metal foil such as #4'i, and this insulating substrate 1 is formed by laminating and molding a plurality of prepregs. When forming the insulating substrate 1, a required number of resin plates are interposed to provide a resin layer 6 that does not contain a base material on one side of the insulating substrate 1 close to the surface. This board 1 is a double-sided metal foil-covered laminate, and the through holes 8 are formed by processing and through hole plating/! I9 is formed, and a circuit pattern 2 is formed by etching the metal foils on both sides using a conventional method, thereby forming a printed wiring board 3. A recess 5 for mounting a semiconductor chip 4 is provided on the surface of the printed wiring board 3 by mechanical cutting such as milling. The mechanical cutting process is performed to a depth that reaches the resin layer 6 that does not contain the base material, and the resin/[6 is exposed at the bottom of the mounting recess ff1Ss. i for this implementation! 1
The portion 5 may be formed at the same time as the through hole 8 is formed. Since resin N6 does not contain a base material,
The cutting stress during the cutting process is extremely small, and there is almost no damage to the adhesion between the base material and the resin as in the conventional case, and therefore no damage to the insulation layer of the mounting recess 5 occurs.
この実装用ｌ！！１部５に金属めっき層７を設けている
。For this implementation! ! A metal plating layer 7 is provided on the first part 5.
金属めっき屑７は、例えばまず銅めっきを無電解めっき
で施し、次いで電解めっきによっ′Ｃ銅めっき、ニッケ
ルめっき、金めつきをこの順序で施こすことに上り形成
することがでさる。この金属めっきＮ７はスルホール８
のめっ％／ｉ０９を形成する際に同時に形成するように
してもよい。この金属めっき層７を形成する際には、実
装用凹部５は絶縁層破壊が殆ど生じていないので、めっ
忽液の絶縁基板１内への浸透はない。このようにして形
成した半導体チップキャリアＡには、第２図に示すよう
に実装用凹部５にグイスボンディングして半導体チップ
４を搭載し、ワイヤ１０ボンデイングにより回路パター
ン２と電気的に接続し、エポキシＵ（脂などにより樹脂
封止し、絶縁処理を施してバッケーノとしての実装を完
了し実用に供する。尚、第３図に示すようにスルホール
８に端子ビン１１を保持させることによりビングリッド
アレイとして、又スルホール８を接続孔として機能させ
ることによりリードレスチップキャリアとして使用でき
るものである。The metal plating scrap 7 can be formed by first applying copper plating by electroless plating, and then applying copper plating, nickel plating, and gold plating in this order by electrolytic plating. This metal plating N7 is through hole 8
It may also be formed at the same time as the formation of Nomet%/i09. When this metal plating layer 7 is formed, there is almost no breakdown of the insulation layer in the mounting recess 5, so that the plating solution does not penetrate into the insulating substrate 1. As shown in FIG. 2, the semiconductor chip carrier A formed in this manner is mounted with a semiconductor chip 4 by means of adhesive bonding into the mounting recess 5, and electrically connected to the circuit pattern 2 by bonding wires 10. , resin sealing with epoxy U (grease, etc.) and insulation treatment to complete the mounting as a baccane and use it for practical use.Incidentally, as shown in Fig. 3, by holding the terminal pin 11 in the through hole 8, the pin lid It can be used as an array or as a leadless chip carrier by making the through holes 8 function as connection holes.
［発明の効果］
本発明にあっては絶縁基板に基材を含まない樹脂層を設
けて実装用凹部に基材を含まない樹脂層を露出させ、こ
の実装用凹部内に金属めっき層を設けているので、機械
的切削加工により実装用凹部を形成する際に、実装用凹
部に露出させる樹脂層は基材を含んでいないので、従来
のように基材と樹脂間の密着破壊など起こらず、実装用
凹部の絶縁層破壊が生じないものであり、従って金属め
っき層を形成する際にめっき液が実装用凹部から絶縁基
板内に浸透することがなく、基板汚染、絶縁性の低下を
抑えることができ、実装する半導体チ・ンプの信頼性を
向上させることができるものである。[Effects of the Invention] In the present invention, a resin layer not containing a base material is provided on an insulating substrate, the resin layer not containing a base material is exposed in a mounting recess, and a metal plating layer is provided in this mounting recess. Therefore, when the mounting recess is formed by mechanical cutting, the resin layer exposed in the mounting recess does not contain the base material, so there is no damage to the adhesion between the base material and the resin as in conventional methods. , there is no breakdown of the insulation layer in the mounting recess, and therefore, when forming a metal plating layer, the plating solution does not penetrate into the insulating substrate from the mounting recess, suppressing substrate contamination and deterioration of insulation properties. This makes it possible to improve the reliability of the semiconductor chip to be mounted.
第１図は本発明の一実施例を示す断面図、第２図は同上
への半導体チップの実装を示す断面図、第３図は同上の
ビングリッドアレイとしての使用を示す一部省略断面図
であって、Ａは半導体チップキャリア、１は絶縁基板、
２は回路パターン、３はプリント配線板、４は半導体チ
ップ、５は実装用凹部、６は樹脂層、７は金属めっき層
である。
代理人 弁理士 万 １）艮 七
第１図
第２図
第３図FIG. 1 is a sectional view showing one embodiment of the present invention, FIG. 2 is a sectional view showing mounting of a semiconductor chip on the same, and FIG. 3 is a partially omitted sectional view showing use as a bin grid array of the same. , A is a semiconductor chip carrier, 1 is an insulating substrate,
2 is a circuit pattern, 3 is a printed wiring board, 4 is a semiconductor chip, 5 is a mounting recess, 6 is a resin layer, and 7 is a metal plating layer. Agent Patent attorney 1) 7Figure 1 Figure 2 Figure 3
Claims (1)
配線板を形成し、プリント配線板の表面に機械的切削加
工により半導体の実装用凹部を形成した半導体チップキ
ャリアにおいて、絶縁基板に基材を含まない樹脂層を設
けて実装用凹部に基材を含まない樹脂層を露出させ、こ
の実装用凹部内に金属めっき層を設けて成ることを特徴
とする半導体チップキャリア。(1) In a semiconductor chip carrier in which a circuit pattern is provided on the surface of an insulating substrate to form a printed wiring board, and a recess for mounting a semiconductor is formed on the surface of the printed wiring board by mechanical cutting, a base material is placed on the insulating substrate. 1. A semiconductor chip carrier, comprising: providing a resin layer containing no base material, exposing the resin layer containing no base material in a mounting recess, and providing a metal plating layer within the mounting recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17881885A JPS6239030A (en) | 1985-08-14 | 1985-08-14 | Semiconductor chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17881885A JPS6239030A (en) | 1985-08-14 | 1985-08-14 | Semiconductor chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6239030A true JPS6239030A (en) | 1987-02-20 |
Family
ID=16055194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17881885A Pending JPS6239030A (en) | 1985-08-14 | 1985-08-14 | Semiconductor chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6239030A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337512B1 (en) | 1999-03-31 | 2002-01-08 | Abb Research Ltd. | Semiconductor module |
-
1985
- 1985-08-14 JP JP17881885A patent/JPS6239030A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337512B1 (en) | 1999-03-31 | 2002-01-08 | Abb Research Ltd. | Semiconductor module |
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