JPS62219836A - Interference compensation circuit - Google Patents
Interference compensation circuitInfo
- Publication number
- JPS62219836A JPS62219836A JP6085786A JP6085786A JPS62219836A JP S62219836 A JPS62219836 A JP S62219836A JP 6085786 A JP6085786 A JP 6085786A JP 6085786 A JP6085786 A JP 6085786A JP S62219836 A JPS62219836 A JP S62219836A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- control
- output
- interference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 abstract description 10
- 230000001360 synchronised effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Radio Transmission System (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は安定な制御を可能にする干渉補償回路の構成法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of configuring an interference compensation circuit that enables stable control.
（従来の技術）
第１図を用いて従来の技術を説明する。通信用主アンテ
ナ１より受信した希望信号（ここではディジタル信号を
例にとる）は周波数変換回路３によりエＦ帯に変換され
る。一方干渉信号を補助アンテナ２よシ受信し、希望信
号側と共通の局部発振器５の出力信号を用いて周波数変
換器４によりＩＦ帯に変換され、その出力１号の位相お
よび振幅を調整するため可変位相回路７および可変振幅
回路６に通す。希望信号にもれ込んだ干渉成分とほぼ逆
相２等振幅となるよう制御された干渉信号と希望信号と
をＩＦ帯において加算する合成回路８を通すことにより
、希望信号中の干渉成分をほぼ消去することができる。(Prior Art) A conventional technology will be explained using FIG. A desired signal (here, a digital signal is taken as an example) received from the main communication antenna 1 is converted into the E-F band by the frequency conversion circuit 3. On the other hand, the interference signal is received by the auxiliary antenna 2, and is converted into the IF band by the frequency converter 4 using the output signal of the local oscillator 5 common to the desired signal side, and the phase and amplitude of the output No. 1 are adjusted. The signal is passed through a variable phase circuit 7 and a variable amplitude circuit 6. The interference component in the desired signal is almost eliminated by passing it through a synthesis circuit 8 that adds the desired signal and the interference signal, which is controlled to have an equal amplitude of approximately the opposite phase to the interference component leaked into the desired signal, in the IF band. Can be erased.
上記、可変位相回路および可変振幅回路を制御するだめ
に、合成後の希望信号中に残留する干渉成分（誤差）と
干渉信号との相関をとり、その値が最小となるようにフ
ィードバック制御する。その具体的には、第１図の合成
回路８の出力について、同相成分および直交成分の誤差
信号を得るため、復調器９に通し直交位相同期検波し、
さらに識別回路に通す。一方、位相および振幅の制御さ
れた干渉信号を分岐し、その一方を希望信号と共通の局
部発振器１１を用いて、直交位相検波器１０により同相
および直交成分に分解された干渉信号を得、その極性を
得るため識別回路に通す。その干渉信号および誤差信号
について、第２図に示すように相関をとる。すなわち、
誤差信号の同相分（Ｅｘ ）と干渉信号の同相分（Ｄｘ
）の排他的論理和を５によりとった値と誤差信号の直交
分（Ｅｙ ）と干渉信号の直交分（Ｄｙ）の排他的論理
利金２６によりとった値とをアナログ的に加算するため
抵抗回路２９．３０を通し、その出力をループフィルタ
３７に通すことにより可変振幅回路６の制御信号を得る
。また、誤差信号の直交分（Ｅｙ）と干渉信号の同相分
（Ｄｘ）との排他的論理和を２７によりとった値と、誤
差信号の同相ｆＫ Ｅｘ ）と干渉信号の直交分（Ｄｙ
）との排他的反転論理和２８（排他的論理をとる際にど
ちらか一方を反転する必要がある）をとった値とをアナ
ログ的に加算するため抵抗回路３１ 、３２を通し、そ
の出力をループフィルタ詔に通すことにより可変位相回
路７の制御信号を得る。In order to control the variable phase circuit and the variable amplitude circuit, the correlation between the interference component (error) remaining in the desired signal after synthesis and the interference signal is calculated, and feedback control is performed so that the value thereof is minimized. Specifically, in order to obtain error signals of in-phase and quadrature components, the output of the combining circuit 8 shown in FIG.
It is then passed through an identification circuit. On the other hand, the interference signal whose phase and amplitude are controlled is branched, one of which is shared with the desired signal using a local oscillator 11, and an interference signal decomposed into in-phase and quadrature components is obtained by a quadrature phase detector 10. Pass through an identification circuit to obtain polarity. The interference signal and error signal are correlated as shown in FIG. That is,
The in-phase component of the error signal (Ex) and the in-phase component of the interference signal (Dx
) and the value obtained by using the exclusive logical interest 26 of the orthogonal component (Ey) of the error signal and the orthogonal component (Dy) of the interference signal. A control signal for the variable amplitude circuit 6 is obtained by passing the output through the circuits 29 and 30 and the loop filter 37. In addition, the value obtained by calculating the exclusive OR of the orthogonal component (Ey) of the error signal and the in-phase component (Dx) of the interference signal, and the in-phase component fK Ex ) of the error signal and the orthogonal component (Dy) of the interference signal
) and the exclusive inverted OR 28 (it is necessary to invert one of them when taking an exclusive logic) in an analog manner. A control signal for the variable phase circuit 7 is obtained by passing it through a loop filter.
（発明が解決しようとする問題点）
以上は希望信号系の復調器が正常に動作し、希望信号中
に存在する残留の誤差信号が忠実に検出されている場合
には、問題は生じないが、系が非同期状態となった場合
、残留する干渉成分を忠実に誤差信号として検出できな
い。そのため非同期時には、可変振幅回路および可変位
相回路の制御を正しくおこなうことが不可能となるだけ
でなく、逆に希望信号に悪影響を与えるという問題点を
有していた。(Problem to be Solved by the Invention) The above problem does not occur if the demodulator of the desired signal system operates normally and the residual error signal present in the desired signal is faithfully detected. , when the system becomes asynchronous, the remaining interference component cannot be faithfully detected as an error signal. Therefore, when the circuit is out of synchronization, it is not only impossible to control the variable amplitude circuit and the variable phase circuit correctly, but also there is a problem in that it adversely affects the desired signal.
本発明は上記問題点を改善することを目的とする。The present invention aims to improve the above problems.
（問題点を解決するための手段）
上記目的を達成するための本発明の特徴は、希望信号受
信用の主アンテナと、干渉信号受信手段と、該干渉信号
受信手段の出力の位相及び振幅と前記主アンテナの出力
との相対関係を調節する調節回路と、該回路により調節
された主アンテナ及び干渉信号受信手段の出力を合成す
る合成回路と・該合成回路の出力に残留する干渉成分と
干渉信号受信手段からの信号との相関量に従って、前記
調節回路による位相及び振幅の制御量を各々独立に制御
する制御回路とを有する干渉補償回路において、希望信
号の同期／非同期状態を検出する同期／非同期検出回路
がもうけられ、希望信号が同期状態のときは、前記制御
回路は前記相関量が最小となるような制御を行ない、希
望信号が非同期状態のときは、前記制御回路は前記制御
回路による位相及び振幅の制御量が各々一定値となるよ
うな制御を行なう干渉補償回路にある。(Means for Solving the Problems) The features of the present invention for achieving the above object include a main antenna for receiving a desired signal, an interference signal receiving means, and a phase and amplitude of the output of the interference signal receiving means. an adjusting circuit that adjusts the relative relationship with the output of the main antenna; a combining circuit that combines the outputs of the main antenna and the interference signal receiving means adjusted by the circuit; and an interference component remaining in the output of the combining circuit. In the interference compensation circuit, the interference compensation circuit includes a control circuit that independently controls the amount of phase and amplitude controlled by the adjustment circuit according to the amount of correlation with the signal from the signal receiving means. An asynchronous detection circuit is provided, and when the desired signal is in a synchronous state, the control circuit performs control such that the correlation amount is minimized, and when the desired signal is in an asynchronous state, the control circuit performs control according to the control circuit. The interference compensation circuit performs control such that the phase and amplitude control amounts are each constant.
（実施例）
本発明の一実施例を第１図に示す。希望信号の同期状態
を検出する同期／非同期検出回路１３が付加された点と
制御回路の内部（第２図に示す）Ｉｃ。(Example) An example of the present invention is shown in FIG. The point where a synchronous/asynchronous detection circuit 13 for detecting the synchronous state of the desired signal is added and the inside of the control circuit (shown in FIG. 2) Ic.
同期／非同期検出信号を用いて相関検出力信号か、ある
固定値かを選択するアナログスイッチ回路３３を有して
いる点が従来回路と比べ異なる。同期／非同期検出回路
としてはいくつか考案されているが、例えば“特願昭６
０−３８９２５”に示されるような回路の場合の回路構
成を第３図に示す。希望信号として１６ Ｑ Ａ Ｍ変
調信号を例にとり、その動作を説明する。１６ＱＡＭを
復調器で直交位相同期検波することにより同相分および
直交分に分解された４値信号を得る。その４値信号を識
別するために、４ビット以上の出力を有するＡ／Ｄ変換
器５３を用意する。第４図にそのレベルダイヤを示す。This circuit differs from conventional circuits in that it includes an analog switch circuit 33 that uses a synchronous/asynchronous detection signal to select either a correlation detection power signal or a certain fixed value. Several synchronous/asynchronous detection circuits have been devised; for example,
0-38925'' is shown in Figure 3.The operation will be explained by taking a 16QAM modulated signal as an example of the desired signal.The 16QAM is quadrature phase coherent detection using a demodulator By doing this, a 4-value signal decomposed into an in-phase component and a quadrature component is obtained.In order to identify the 4-value signal, an A/D converter 53 having an output of 4 bits or more is prepared. Shows level diamond.
第４図より、Ａ／Ｄ変換器出力の最上位ピッ） （ｐａ
ｔｈｌ）および上位２ビツト目（Ｐａｔｈ２）は４値信
号の識別結果を示している。上位３ビツト目（Ｐａｔｈ
３）は信号点の偏移方向、すなわち誤差の方向を示して
お９、制御回路（第１図の１２）に供給する誤差信号（
Ｅｘ ｒ ＥＹ ）である。上位４ビツト目（Ｐａｔｈ
４）は誤差の大きさを示している。すなわちｐａｔｈ
３とｐａｔｈ４の排他的反転論理和５６をとることによ
り符号間干渉量小のとき“０″、符号量干渉量大のとき
”１゛′となる。第３図では２’＝１６のタイムスロッ
ト中、符号量干渉量大が２タイムスロット以上存在する
場合のみ非同期状態と判定し、それ以下では同期状態と
判定している。検出信号出力端子７０には同期時”１”
、非同期時”０”が出力される。その信号を第２図に示
す。アナログスイッチ切替信号入力端子あに接続し、ア
ナログスイッチ回路３３を制御する。すなわち同期時に
はループフィルタ３７ 、３８の出力を出力端子３９
、４０に接続し、非同期時には固定電圧発生回路３５
、３６の出力を出力端子３９ 、４０に接続する。ここ
で、アナログスイッチ回路としては低速切替であればリ
レー回路、高速であれば半導体アナログスイッチ回路を
用いればよい。また、通常、固定電圧発生回路としては
、可変振幅回路の振幅を最小とするように設定される。From Figure 4, the highest pitch of the A/D converter output) (pa
thl) and the second most significant bit (Path2) indicate the identification result of the four-value signal. Upper 3rd bit (Path
3) indicates the direction of deviation of the signal point, that is, the direction of the error, and the error signal (12) supplied to the control circuit (12 in Fig.
Ex r EY ). Upper 4th bit (Path
4) indicates the magnitude of the error. In other words, path
By taking the exclusive inverted OR 56 of 3 and path 4, it becomes "0" when the amount of intersymbol interference is small, and "1" when the amount of code amount interference is large. In FIG. The state is determined to be asynchronous only when there are two or more time slots with a large code amount interference amount, and the state is determined to be synchronous when it is less than that.The detection signal output terminal 70 is set to "1" when synchronized.
, “0” is output when asynchronous. The signal is shown in FIG. It is connected to the analog switch switching signal input terminal A to control the analog switch circuit 33. That is, during synchronization, the outputs of the loop filters 37 and 38 are sent to the output terminal 39.
, 40, and when asynchronous, the fixed voltage generation circuit 35
, 36 are connected to output terminals 39 and 40. Here, as the analog switch circuit, a relay circuit may be used for low-speed switching, and a semiconductor analog switch circuit may be used for high-speed switching. Further, the fixed voltage generation circuit is usually set to minimize the amplitude of the variable amplitude circuit.
（発明の効果）
以上説明したように、本干渉補償回路では、希望信号の
同期状態により制御の状態を自動的に切替えることが可
能であり、従って、希望信号が非同期の場合通常の制御
を停止し、可変位相回路および可変振幅回路をある一定
値に固定するため制御の安定化にたいへん有効であると
いう利点を有している。(Effects of the Invention) As explained above, in this interference compensation circuit, it is possible to automatically switch the control state depending on the synchronization state of the desired signal, and therefore, normal control can be stopped when the desired signal is asynchronous. However, since the variable phase circuit and the variable amplitude circuit are fixed to a certain constant value, it has the advantage of being very effective in stabilizing control.
第１図は本発明の実施例のブロック図、第２図は制御回
路のブロック図、第３図は同期／非同期検出回路のブロ
ック図、第４図は４値の識別回路（Ａ／Ｄ変換器）のレ
ベルダイヤ説明図である。Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of a control circuit, Fig. 3 is a block diagram of a synchronous/asynchronous detection circuit, and Fig. 4 is a four-value identification circuit (A/D conversion circuit). FIG. 2 is an explanatory diagram of the level diagram of
Claims (1)
テナの出力との相対関係を調節する調節回路と、 該回路により調節された主アンテナ及び干渉信号受信手
段の出力を合成する合成回路と、 該合成回路の出力に残留する干渉成分と干渉信号受信手
段からの信号との相関量に従つて、前記調節回路による
位相及び振幅の制御量を各々独立に制御する制御回路と
を有する干渉補償回路において、 希望信号の同期／非同期状態を検出する同期／非同期検
出回路がもうけられ、 希望信号が同期状態のときは、前記制御回路は前記相関
量が最小となるような制御を行ない、希望信号が非同期
状態のときは、前記制御回路は前記制御回路による位相
及び振幅の制御量が各々一定値となるような制御を行な
うことを特徴とする、干渉補償回路。[Scope of Claims] A main antenna for receiving a desired signal; an interference signal receiving means; an adjustment circuit for adjusting the relative relationship between the phase and amplitude of the output of the interference signal receiving means and the output of the main antenna; a combining circuit that combines the outputs of the main antenna and the interference signal receiving means adjusted by the circuit; and the adjusting circuit according to the amount of correlation between the interference component remaining in the output of the combining circuit and the signal from the interference signal receiving means. In the interference compensation circuit which has a control circuit that independently controls the phase and amplitude control amount by , the control circuit performs control such that the correlation amount is minimized, and when the desired signal is in an asynchronous state, the control circuit performs control such that the phase and amplitude control amounts by the control circuit are each constant values. An interference compensation circuit characterized by performing the following.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6085786A JPS62219836A (en) | 1986-03-20 | 1986-03-20 | Interference compensation circuit |
| US06/921,093 US4736455A (en) | 1985-12-23 | 1986-10-21 | Interference cancellation system |
| CA000521944A CA1257658A (en) | 1985-12-23 | 1986-10-31 | Interference cancellation system |
| DE8686308589T DE3685645T2 (en) | 1985-12-23 | 1986-11-04 | SYSTEM FOR COMPENSATING A RADIO INTERFERENCE SIGNAL. |
| EP86308589A EP0228786B1 (en) | 1985-12-23 | 1986-11-04 | Radio signal interference cancellation system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6085786A JPS62219836A (en) | 1986-03-20 | 1986-03-20 | Interference compensation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62219836A true JPS62219836A (en) | 1987-09-28 |
Family
ID=13154469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6085786A Pending JPS62219836A (en) | 1985-12-23 | 1986-03-20 | Interference compensation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62219836A (en) |
-
1986
- 1986-03-20 JP JP6085786A patent/JPS62219836A/en active Pending
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