JPS6136934A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6136934A JPS6136934A JP15965584A JP15965584A JPS6136934A JP S6136934 A JPS6136934 A JP S6136934A JP 15965584 A JP15965584 A JP 15965584A JP 15965584 A JP15965584 A JP 15965584A JP S6136934 A JPS6136934 A JP S6136934A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semi
- base
- electrode
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- -1 nitrogen ions Chemical class 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は表面安定化層を有する半導体装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a surface stabilizing layer.
従来例の構成とその問題点
プレーナ型半導体装置において、ＰＮ接合の現われる半
導体基板表面は、通常、熱酸化膜で保護される。しかし
、この半導体装置のＰＮ接合に逆電圧を印加すると、熱
酸化膜中に存在する正電荷により、基板と熱酸化膜との
界面付近での空乏層の拡がわが、基板内部よりも小さく
なり電界が界２ぺ。Conventional Structure and Its Problems In a planar semiconductor device, the surface of the semiconductor substrate where the PN junction appears is usually protected with a thermal oxide film. However, when a reverse voltage is applied to the PN junction of this semiconductor device, the expansion of the depletion layer near the interface between the substrate and the thermal oxide film becomes smaller than that inside the substrate due to the positive charges existing in the thermal oxide film. The electric field is field 2pe.
面に集中して界面付近での耐圧の低下を起こす。Concentrates on the surface and causes a drop in withstand pressure near the interface.
さらに熱酸化膜の表面にイオンが存在すると、高温環境
でＰＮ接合に逆電圧を印加する試験において、ＰＮ接合
の耐圧の劣化や漏れ電流の増大等を伴なう不良が発生す
ることが多い。Furthermore, the presence of ions on the surface of the thermal oxide film often causes defects such as deterioration of the withstand voltage of the PN junction and increase in leakage current in tests in which a reverse voltage is applied to the PN junction in a high temperature environment.
そこで、熱酸化膜の代わりに、半絶縁性膜として知られ
る酸素をドープした多結晶シリコン膜を被着し、これに
よって接合の耐圧を向上させ、信頼性を向上させている
。半絶縁性膜はわずかに導電性であるため、その下側の
領域をその上側の材料の電荷からも遮蔽でき、またＰＮ
接合の逆電圧印加時に、半絶縁性膜で電圧を徐々に降下
させることにより、半絶縁性膜の下側の領域における電
界を減少させるため、信頼性を向上させ、耐圧を向上さ
せることができる。さらに実用の半導体装置では、半絶
縁性膜上に絶縁膜、たとえば、シリコン酸化膜を堆積さ
せて半絶縁性膜を保護し、半導体基板の表面安定化を高
めうるようにするのが好ましい。次に、ＮＰＮブレーナ
トランジスタを例に、半絶縁性膜を用いた場合の製造工
程を説明する。Therefore, instead of the thermal oxide film, an oxygen-doped polycrystalline silicon film known as a semi-insulating film is deposited to improve the breakdown voltage of the junction and improve reliability. Because the semi-insulating film is slightly conductive, it can also shield the area underneath it from the charge of the material above it, and the PN
By gradually lowering the voltage across the semi-insulating film when applying a reverse voltage across the junction, the electric field in the area under the semi-insulating film is reduced, which improves reliability and withstand voltage. . Furthermore, in a practical semiconductor device, it is preferable to deposit an insulating film, for example, a silicon oxide film, on the semi-insulating film to protect the semi-insulating film and improve surface stabilization of the semiconductor substrate. Next, a manufacturing process using a semi-insulating film will be explained using an NPN Brainer transistor as an example.
第１図ＡはＮ型シリコン半導体基板１の表面に、熱酸化
によって熱酸化膜を形成し、この熱酸化膜に開口を形成
して、この開口から不純物拡散を行ない、ベース領域２
をＰ型不純物拡散により形成し、次いで、この拡散時に
形成された熱酸化膜をマスクにして、エミッタ領域３を
Ｎ型不純物拡散により形成したものであり、この拡散時
に熱酸化膜４が形成される。In FIG. 1A, a thermal oxide film is formed on the surface of an N-type silicon semiconductor substrate 1 by thermal oxidation, an opening is formed in this thermal oxide film, and impurities are diffused from this opening to form a base region 2.
is formed by diffusing P-type impurities, and then, using the thermal oxide film formed during this diffusion as a mask, the emitter region 3 is formed by diffusing N-type impurities, and a thermal oxide film 4 is formed during this diffusion. Ru.
第１図Ｂは、半導体基板のベース・コレクタ接合付近と
コレクタ領域１との表面の熱酸化膜４を除去して周辺部
に開口を形成したものである。ベース領域２とエミッタ
領域３とのＰＮ接合部の表面に熱酸化膜４を残置したの
は、ＰＮ接合の順電圧印加時にリーク電流による直流電
流増幅率の低下を防ぐためである。In FIG. 1B, the thermal oxide film 4 on the surface of the collector region 1 and near the base-collector junction of the semiconductor substrate is removed to form an opening in the periphery. The reason why the thermal oxide film 4 is left on the surface of the PN junction between the base region 2 and the emitter region 3 is to prevent the direct current amplification factor from decreasing due to leakage current when applying a forward voltage to the PN junction.
第１図Ｃは、半絶縁性膜としての酸素を含んだ多結晶シ
リコン膜５と絶縁膜としてのシリコン酸化膜６とを気相
成長法によって、順次、全面に形成したものである。In FIG. 1C, a polycrystalline silicon film 5 containing oxygen as a semi-insulating film and a silicon oxide film 6 as an insulating film are successively formed over the entire surface by vapor phase growth.
第１図りは、ベースとエミッタ電極部の開口を形成する
ため、絶縁膜６と半絶縁性膜５を選択エツチングしたも
のである。半絶縁性膜が直接、半導体基板に被着すると
半絶縁性膜はシリコンとの選択エツチングが良好に行な
われないため、エツチングの終点が明確ではなく、エツ
チングが足りなかったり、あるいはエツチングしすぎた
るおそれがあり、それを防ぐためにも熱酸化膜を残して
いる。半絶縁性膜５のエツチングには、たとえばＣＦ４
＋０２のプラズマが用いられるが、酸化膜との選択比が
大きいため終点がはっきりとする。In the first diagram, the insulating film 6 and the semi-insulating film 5 are selectively etched to form openings for the base and emitter electrode portions. When a semi-insulating film is directly deposited on a semiconductor substrate, the selective etching of the semi-insulating film with silicon does not occur well, so the end point of the etching is not clear and the etching may be insufficient or over-etched. To prevent this, a thermal oxide film is left behind. For example, CF4 is used for etching the semi-insulating film 5.
Although +02 plasma is used, the end point is clear because it has a high selectivity with respect to the oxide film.
第１図Ｅは、ベース領域２上およびエミッタ領域３上の
電極形成部に開口を形成したものである。In FIG. 1E, openings are formed in the electrode forming portions on the base region 2 and emitter region 3. In FIG.
このように表面安定化層５，６と熱酸化膜４との二段階
のエツチングが必要であり製造上かなり吹雑である。As described above, two-step etching of the surface stabilizing layers 5 and 6 and the thermal oxide film 4 is required, which is quite complicated in manufacturing.
第１図Ｆは、ベース電極７およびエミッタ電極８が被着
形成されたものである。In FIG. 1F, a base electrode 7 and an emitter electrode 8 are formed.
発明の目的
本発明は、上記の難点を解決するためになされたもので
あり、電極取出しの工程を簡略化し、電極の断切れを防
止することが可能な半導体装置の製造方法を提供するも
のである。OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned difficulties, and provides a method for manufacturing a semiconductor device that simplifies the process of taking out the electrodes and can prevent the electrodes from breaking. be.
発明の構成
本発明は、表面にＰＮ接合を現わして有する半導体基板
の全面をおおって、半絶縁性膜および絶縁膜を被着する
工程、前記絶縁膜を選択エツチングする工程イオン注入
によって前記半絶縁性膜を絶縁膜化する工程を備えた半
導体装置の製造方法であり、これにより、半絶縁性膜を
選択エツチングする工程が削減できるとともに電極の断
切れを防止できるため、歩留の向上および信頼性の向上
がはかれるものである。Structure of the Invention The present invention provides a step of depositing a semi-insulating film and an insulating film over the entire surface of a semiconductor substrate having a PN junction exposed on the surface, a step of selectively etching the insulating film, and a step of selectively etching the insulating film by ion implantation. This is a semiconductor device manufacturing method that includes a step of converting an insulating film into an insulating film. This method reduces the step of selectively etching a semi-insulating film and prevents electrode breakage, thereby improving yield and This is intended to improve reliability.
実施例の説明
第２図Ａ〜第２図Ｅは、本発明をＮＰＮ トランジスタ
の製造工程に実施する一例を工程順に図示したものであ
る。DESCRIPTION OF THE EMBODIMENTS FIGS. 2A to 2E illustrate an example of implementing the present invention in the manufacturing process of an NPN transistor in the order of steps.
第２図Ａは、第１図Ａの従来工程に引き続いて、エミッ
タ領域３の形成後、半導体表面の全域に、半絶縁性膜５
と絶縁膜６とを気相成長法によって、順次、全面に形成
したものである。この半絶縁性膜５の被着によって耐圧
を向上させ信頼性を向上させている。半絶縁性膜６の形
成は、減圧ＣＶＤ装置内にモノシランと亜酸化窒素ガス
を混合させることによって、酸素を含む多結晶シリコン
膜を形成し、捷た、絶縁膜６の形成は、亜酸化窒素ガス
の流量を増加して連続的にシリコン酸化膜を形成する工
程によって実現することができる。この半絶縁性膜５は
、半導体基板表面を外部電界から遮蔽するのに充分な程
度導電性とするため、１ｏ７Ωα〜１ｏ１０Ω儂との間
の比抵抗を有するように選択される。FIG. 2A shows that, following the conventional process of FIG. 1A, after the emitter region 3 is formed, a semi-insulating film 5 is applied over the entire semiconductor surface.
and an insulating film 6 are sequentially formed over the entire surface by a vapor phase growth method. The deposition of the semi-insulating film 5 improves the breakdown voltage and reliability. The semi-insulating film 6 is formed by mixing monosilane and nitrous oxide gas in a low-pressure CVD apparatus to form a polycrystalline silicon film containing oxygen. This can be achieved by a process of continuously forming a silicon oxide film by increasing the flow rate of gas. This semi-insulating film 5 is selected to have a specific resistance between 107 Ωα and 1010 Ω2 in order to be sufficiently conductive to shield the semiconductor substrate surface from external electric fields.
第２図Ｂは、ベース・エミッタ接合部付近の絶縁膜６を
選択エツチングしたものである。FIG. 2B shows selective etching of the insulating film 6 near the base-emitter junction.
第２図Ｃは、酸素あるいは窒素をイオン注入して、ベー
ス・エミッタ接合部の半絶縁性膜６を絶縁膜化して、表
面側の絶縁膜６と同質の絶縁膜９を形成したものである
。従ってベース・エミッタ接合部のベース領域２上とエ
ミッタ領域３上の絶縁膜の厚みは等しくなる。これによ
って特性改善のために微細化が進む場合でもアルミニウ
ム蒸着電極の断切れを防止できる。In FIG. 2C, oxygen or nitrogen ions are implanted to transform the semi-insulating film 6 at the base-emitter junction into an insulating film, forming an insulating film 9 of the same quality as the insulating film 6 on the surface side. . Therefore, the thickness of the insulating film on the base region 2 and on the emitter region 3 of the base-emitter junction becomes equal. This makes it possible to prevent the aluminum vapor-deposited electrode from breaking even when miniaturization progresses to improve characteristics.
第２図りは、電極取出しのためにベースとエミッタとの
各電極形成部の開口を形成するために絶縁膜６を選択エ
ツチングしたものである。The second diagram shows the insulating film 6 selectively etched to form openings in the base and emitter electrode forming portions for taking out the electrodes.
第２図Ｅは、ベース電極γおよびエミッタ電極８がアル
ミニウム蒸着により被着形成されたもので、半絶縁性膜
５は通常、５０００八程度の膜厚であり、アルミニウム
電極の５００℃位の熱処理によって合金層１ｏが形成さ
れ半導体基板と良好なオーミックコンタクトが得られる
。In FIG. 2E, the base electrode γ and the emitter electrode 8 are formed by aluminum vapor deposition, and the semi-insulating film 5 is usually about 5,000 degrees thick, and the aluminum electrode is heat-treated at about 500°C. Thus, an alloy layer 1o is formed and good ohmic contact with the semiconductor substrate is obtained.
なお本実施例ではＮＰＮトランジスタに本発明を適用し
たが、ＰＮＰ ）ランジスタ・ダイオードに本発明を適
用しても同様の効果を有することは明らかである。In this embodiment, the present invention is applied to an NPN transistor, but it is clear that the same effect can be obtained even if the present invention is applied to a PNP transistor/diode.
発明の詳細
な説明したように、本発明はＰＮ接合面を有する半導体
装置において、半導体基板表面の全面に半絶縁性膜およ
び絶縁膜を被着し、この絶縁膜を選択エツチングし、イ
オン注入によってベース・エミッタ接合部の半絶縁性膜
を絶縁膜化し、ベースとエミッタとの各電極形成部の開
口を形成するだめに絶縁膜を選択エツチングし、ベース
電極とエミッタ電極を被着形成し、電極の熱処理によっ
て、半導体基板との良好なオーミックコンタクトが得ら
れることによって、半絶縁性膜を選択エツチングする工
程が削減でき、ベース・エミッタ接合部の絶縁膜の厚み
を等しくできることによって、電極の断切れを防止でき
るという利点を有するものである。As described in detail, the present invention provides a semiconductor device having a PN junction surface, in which a semi-insulating film and an insulating film are deposited on the entire surface of a semiconductor substrate, this insulating film is selectively etched, and etching is performed by ion implantation. The semi-insulating film at the base-emitter junction is made into an insulating film, and the insulating film is selectively etched to form openings for the base and emitter electrode formation parts.The base electrode and emitter electrode are deposited and the electrodes The heat treatment enables good ohmic contact with the semiconductor substrate, which eliminates the process of selectively etching the semi-insulating film, and by making the thickness of the insulating film at the base-emitter junction equal, there is no disconnection of the electrode. This has the advantage of being able to prevent
第１図Ａ〜第１図Ｆは従来例を工程順に示した断面図、
第２図Ａ〜第２図Ｅは本発明の一実施例を工程順に示し
た断面図である。
１・・・・・・Ｎ型半導体基板、２・・・・・・Ｐ型不
純物を拡散したべ〜ス領域、３・・・・・・Ｎ型不純物
を拡散したエミッタ領域、４・・・・・・熱酸化膜、５
・・・・・・半絶縁性膜、６・・・・・・絶縁膜、７・
・・・・・ベース電極、８・・・・・・エミッタ電極、
９・・・・・・絶縁化した半絶縁性膜、１０・・・・・
・半絶縁性膜と電極との合金層。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名！！
ｌ！１図Figures 1A to 1F are cross-sectional views showing the conventional example in the order of steps;
FIGS. 2A to 2E are cross-sectional views showing an embodiment of the present invention in the order of steps. 1... N-type semiconductor substrate, 2... Base region with P-type impurities diffused, 3... Emitter region with N-type impurities diffused, 4... ...Thermal oxide film, 5
... Semi-insulating film, 6... Insulating film, 7.
...Base electrode, 8...Emitter electrode,
9... Insulated semi-insulating film, 10...
・Alloy layer of semi-insulating film and electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person! !
l! Figure 1
Claims (1)
半絶縁性膜とその上に絶縁膜とを堆積する工程と、前記
絶縁膜を選択エッチング除去する工程と、イオン注入に
よって前記半絶縁性膜を絶縁膜化する工程とを有する半
導体装置の製造方法。Covering the entire surface of a semiconductor substrate with a PN junction on the surface,
A method for manufacturing a semiconductor device, comprising: depositing a semi-insulating film and an insulating film thereon; removing the insulating film by selective etching; and converting the semi-insulating film into an insulating film by ion implantation. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15965584A JPS6136934A (en) | 1984-07-30 | 1984-07-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15965584A JPS6136934A (en) | 1984-07-30 | 1984-07-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6136934A true JPS6136934A (en) | 1986-02-21 |
Family
ID=15698447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15965584A Pending JPS6136934A (en) | 1984-07-30 | 1984-07-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6136934A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100062599A1 (en) * | 2008-09-05 | 2010-03-11 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
-
1984
- 1984-07-30 JP JP15965584A patent/JPS6136934A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100062599A1 (en) * | 2008-09-05 | 2010-03-11 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
| US8377832B2 (en) * | 2008-09-05 | 2013-02-19 | Mitsubishi Electric Corporation | Method for manufacturing semiconductor device |
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