JPS6061856A - Assigning circuit for right to occupy bus - Google Patents
Assigning circuit for right to occupy busInfo
- Publication number
- JPS6061856A JPS6061856A JP16975683A JP16975683A JPS6061856A JP S6061856 A JPS6061856 A JP S6061856A JP 16975683 A JP16975683 A JP 16975683A JP 16975683 A JP16975683 A JP 16975683A JP S6061856 A JPS6061856 A JP S6061856A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- signal line
- signal
- priority
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Small-Scale Networks (AREA)
Abstract
Description
【発明の詳細な説明】
この発８Ａは複数のボートが接続されるバスにおいて、
各ボートからのバス占有要求に対しあらかじめきめた優
先順位でバス使用の許可を与える回路に関する。[Detailed description of the invention] This departure 8A is a bus to which multiple boats are connected.
This invention relates to a circuit that grants permission to use a bus in a predetermined priority order in response to requests for bus occupancy from each boat.
従来、バスの占有権を決定する回路としてプライオリテ
ィテコ〜ダが用いられているが時々刻々各ボートの優先
順位を変更することは離しかった。Conventionally, a priority lever has been used as a circuit for determining bus occupancy, but it has been difficult to change the priority order of each boat from time to time.
また優先順位を変更しながら、占有権を決定するために
は、回路が複雑となり高価なものとなっていた。Furthermore, in order to determine the exclusive right while changing the priority order, the circuit becomes complicated and expensive.
本発明の目的はＲＯＭを用いた簡単な回路によシ優先順
位を時々刻々変化させうる廉価なバス占有権割当回路を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an inexpensive bus occupancy allocating circuit that can change priority levels from time to time using a simple circuit using ROM.
本発明によれば複数のホードが接続されているバスに対
し、各々のボートが独立に要求するバス占有要求信号を
受けバス占有権割当信号を発生するバス占有権割当回路
において前記バスの基本周期に同期して優先番号を発生
する手段と、Ａｉｌ記バス占有要求信号と前記優先番号
から各ボートにバス占有権が与えられたか否かを示す占
有イ６割肖信号を発生し、出力づ−る手段とを備えたこ
とを特徴とするバス占有権割当回路が得られる。According to the present invention, in a bus occupancy allocation circuit that receives a bus occupancy request signal independently requested by each boat to a bus to which a plurality of hosts are connected, and generates a bus occupancy allocation signal, the basic period of the bus is determined. means for generating a priority number in synchronization with the bus occupancy request signal and the priority number, and generates and outputs an occupancy 60% signal indicating whether or not bus occupancy has been granted to each boat. According to the present invention, there is provided a bus occupancy right allocating circuit characterized in that the bus occupancy right allocating circuit is provided with a means for assigning bus occupancy rights.
次に、この発明について図面を参照して説明する。第１
図は本発明の実施例を示すブロック図である。信号線１
１０を通してクロックが入力され信号線１２０全通して
各ポートからのバス占有要求信号が入力される。カラン
タ１０は信号線１１０信号線１３Ｏのカラント値をアド
レスしてアクセスされ信号線１４０に優先番号が、信号
線１４１アされる。信号線１４０の優先番号と信号線１
２０に人力される。各ポートの占有要求信号とをアドレ
スとして、Ｔ（，０Ｍ３０がアクセスされ、各ホードの
占有イ衣割当信号が信号線１５０に読み出され、レジス
タ４０で信号線１１０のクロックに同期して保持され信
号線１６０全通しで出力される。この結果時間と共に変
化する優先番号によって占有権割当信号が変化すること
が伴る。以降説明を簡単にするために、バスに接続され
るポート数を８に限定する。この時信号線１２０は８本
からなシ、各ポートから独立にバス占有要求が出され、
信号線１６０ も８本からなシ、各ポートへ個別にバス
占有権が割シ当てられる。Next, the present invention will be explained with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of the present invention. Signal line 1
A clock is input through 10, and a bus occupancy request signal from each port is input through all signal lines 120. The quanta 10 is accessed by addressing the currant value of the signal line 110 and the signal line 13O, and the priority number is assigned to the signal line 140 and the signal line 141. Priority number of signal line 140 and signal line 1
20 will be man-powered. T(,0M30 is accessed using the occupancy request signal of each port as an address, and the occupancy assignment signal of each host is read out to the signal line 150, and held in the register 40 in synchronization with the clock of the signal line 110. It is output through the entire signal line 160.As a result, the exclusive right assignment signal changes depending on the priority number that changes over time.Hereafter, to simplify the explanation, the number of ports connected to the bus will be set to 8. At this time, the number of signal lines 120 is eight, and bus occupation requests are issued independently from each port.
There are also eight signal lines 160, and bus occupancy rights are individually assigned to each port.
第２図は優先割当方法を説明するだめの一例を示す図で
ある。横方向はポート番号であシ、縦方向は、優先番号
を示しており、図の要素は優先１１Ｆ１位を示している
。優先順位は例えばＯが最も高く番号が大きくなる程低
くなるものとする。さらに優先番号Ｏはボート番号Ｏの
優先順位が最も高くボート番号が大きくなるに従い優先
順位が低くなることを示している。几０Ｍ３０の内容と
して優先番号で決定される優先順位に従い信号線１２０
を通して入力されるバス占有要求信号のプライオリティ
デコード結果の値が格納される。優先番号０の場合、ボ
ート番号０からのバス占有要求があれば、ボート番号Ｏ
にバス占有割当を行ない、ボート番号Ｏ〜１迄のバス占
有要求がなくボート番号ｉ ＋１ のバス占有要求があ
る時ポート番号１−１−１にバス占有割当を行なう。FIG. 2 is a diagram illustrating an example of a priority assignment method. The horizontal direction shows the port number, the vertical direction shows the priority number, and the element in the figure shows the priority 11F1. For example, O is the highest priority, and the higher the number, the lower the priority. Further, the priority number O indicates that the priority of the boat number O is the highest and the priority becomes lower as the boat number becomes larger. The signal line 120 is routed according to the priority determined by the priority number as the content of 几0M30.
The value of the priority decode result of the bus occupancy request signal inputted through the bus occupancy request signal is stored. In the case of priority number 0, if there is a bus occupancy request from boat number 0, boat number O
When there is no bus occupancy request for port numbers O to 1 and there is a bus occupancy request for boat number i +1, bus occupancy is allocated to port number 1-1-1.
ＲＯＭ２０００〜７番地にＯ〜７の優先番号と、クリア
信号＋１１と、８番地にクリア信号１ｏ１をかくと、８
つのポイントが巡回的に最優先権をもった優先割当て回
路を構成することが出来る。If you write the priority numbers O to 7 in ROM addresses 2000 to 7, the clear signal +11, and the clear signal 1o1 to address 8, the result is 8.
A priority allocation circuit can be constructed in which one point has the highest priority cyclically.
またＲＯＭ２０のＯ〜７番地に０の優先番号を８〜１４
番地に１〜７の優先番号を１５５番地クリア信号を格納
することによシポートｏの最優先権頻度を大きくする等
各ポート毎に優先頻度を変えることが容易である。Also, set priority numbers 0 to 8 to 14 in addresses O to 7 of ROM20.
By storing the priority numbers 1 to 7 and the address 155 clear signal in the addresses, it is easy to change the priority frequency for each port, such as increasing the highest priority frequency of port o.
第３図は別の優先割当方法を説明するだめの図である。FIG. 3 is a diagram for explaining another priority assignment method.
ポート０〜３の優先順位は、ボート番号が小さい程高く
ホード４〜７では均等で巡回的に行ないたくポート０〜
３とポート４〜７とは優先度が決定されていない場合、
図に示した優先順位割当を用いることが出来る。更にＲ
ＯＭ２０に格納される優先番号の順序と頻度によシバス
占有権割当を変化させることが可能である。The priority of ports 0 to 3 is higher as the boat number is smaller, and in hoards 4 to 7, it is even and cyclical.
3 and ports 4 to 7 have no priority determined,
The priority assignment shown in the figure can be used. Further R
It is possible to change the Sibus exclusive right assignment depending on the order and frequency of priority numbers stored in the OM 20.
また、例えば几０Ｍ３０で優先番号０の場合常にポート
Ｏにバス占有権割当を行なうことによシ、定期的にバス
を使用するポートからバス占有要求を出さなくてもバス
を利用出来、リフレッシュメモリをディスプレイや浸算
回路等に接続した時のメモリリフレッシ−サイクルやデ
ィスプレイ用データリードサイクルが簡単に与えられる
。For example, if priority number 0 is 0M30, by always assigning bus occupancy to port O, the bus can be used without issuing a bus occupancy request from the port that regularly uses the bus, and the refresh memory When connected to a display, dipping circuit, etc., a memory refresh cycle and display data read cycle can be easily performed.
本発明のバス占有権割当回路を用いれば、バスに接続さ
れる複数のポートへのバス占有優先権を時間と共に変化
させ、その頻度を任意に設定することが簡単な回路によ
シ実現できる。By using the bus occupancy allocation circuit of the present invention, it is possible to change the bus occupancy priority to a plurality of ports connected to a bus over time and set the frequency as desired using a simple circuit.
第１図は本発明の実施例を示すブロック図、第２図は優
先割当方法を説明するだめの一例を示す図、第３図は別
の優先割当方法を説明するだめの図において、１０は力
ｊンタ、２０．３０はＲＯＭ。
４０はレジスタである。
第２図
第３図FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of a method for explaining a priority assignment method, and FIG. 3 is a diagram for explaining another priority assignment method. 20.30 is ROM. 40 is a register. Figure 2 Figure 3
Claims (1)
トが独立に要求するバス占有要求信号を受けバス占有権
割当信号を発生するバス占有権割当回路において前記バ
スの基本周期に同期して時間とともに予じめ設定された
優先番号を順次発生する手段と、前記バス占有要求信号
と前記優先番号とから各ボートにバス占有権が与えられ
たか否かを示す占有権割当信号を発生し、出力する手段
とを備えたことを特徴とするｌバス占有権割当回路。In a bus occupancy allocation circuit that receives a bus occupancy request signal independently requested by each boat for a bus to which a plurality of boats are connected, and generates a bus occupancy allocation signal, the bus occupancy allocation circuit generates a bus occupancy allocation signal in synchronization with the basic cycle of the bus. means for sequentially generating preset priority numbers; and generating and outputting an exclusive right assignment signal indicating whether bus exclusive right has been given to each boat from the bus occupation request signal and the priority number; 1. An l-bus exclusive right allocation circuit, characterized in that it comprises means for.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16975683A JPS6061856A (en) | 1983-09-14 | 1983-09-14 | Assigning circuit for right to occupy bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16975683A JPS6061856A (en) | 1983-09-14 | 1983-09-14 | Assigning circuit for right to occupy bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6061856A true JPS6061856A (en) | 1985-04-09 |
Family
ID=15892262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16975683A Pending JPS6061856A (en) | 1983-09-14 | 1983-09-14 | Assigning circuit for right to occupy bus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6061856A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6282842A (en) * | 1985-10-08 | 1987-04-16 | Nec Corp | Transmission right control circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5152252A (en) * | 1974-11-01 | 1976-05-08 | Hitachi Ltd | Deetachanerusochino nyushutsuryokusochikinitsusentakukairo |
| JPS576925A (en) * | 1980-06-16 | 1982-01-13 | Hitachi Ltd | Priority selecting circuit |
-
1983
- 1983-09-14 JP JP16975683A patent/JPS6061856A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5152252A (en) * | 1974-11-01 | 1976-05-08 | Hitachi Ltd | Deetachanerusochino nyushutsuryokusochikinitsusentakukairo |
| JPS576925A (en) * | 1980-06-16 | 1982-01-13 | Hitachi Ltd | Priority selecting circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6282842A (en) * | 1985-10-08 | 1987-04-16 | Nec Corp | Transmission right control circuit |
| JPH0525416B2 (en) * | 1985-10-08 | 1993-04-12 | Nippon Electric Co |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0883254A (en) | Method and system for efficient allocation of bus in multimedia computer system | |
| KR100663248B1 (en) | Simultaneous addressing using single-port rams | |
| US5796961A (en) | Heuristic bus access arbiter | |
| GB2190771A (en) | Memory device | |
| US5541923A (en) | Data transfer method and apparatus | |
| US6374244B1 (en) | Data transfer device | |
| JPS6061856A (en) | Assigning circuit for right to occupy bus | |
| JP4839155B2 (en) | Access arbitration device and access arbitration method | |
| JP2011133940A (en) | Access arbitration apparatus, integrated circuit device, electronic apparatus, access arbitration method, and program | |
| US9489139B2 (en) | Command processing apparatus, method and integrated circuit apparatus | |
| JP2005346715A (en) | Multiport random access memory | |
| JPS5926033B2 (en) | reader | |
| JPH10228446A (en) | Bus arbitration system | |
| JP3618249B2 (en) | Data transfer device | |
| GB2199678A (en) | Pixel data memory | |
| JP2900699B2 (en) | Display control device | |
| JPH0731523B2 (en) | Programmable controller device | |
| US6865635B1 (en) | Access scheme for a collective resource using a plurality of states | |
| JPS5837688A (en) | Reflesh memory access system | |
| SU1628064A1 (en) | Addressing device | |
| JPH0525331B2 (en) | ||
| JP3910165B2 (en) | High speed processor | |
| SU559465A1 (en) | Device for selection of information channels | |
| JP2590695B2 (en) | Time division switch circuit | |
| JPH04195190A (en) | Address converter for display memory |