JPS604238A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS604238A JPS604238A JP11216183A JP11216183A JPS604238A JP S604238 A JPS604238 A JP S604238A JP 11216183 A JP11216183 A JP 11216183A JP 11216183 A JP11216183 A JP 11216183A JP S604238 A JPS604238 A JP S604238A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- circuit
- points
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Relating To Insulation (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は特に回路部品実装後における印刷配線基板の回
路チェックを容易化するだめの機能回路をもつ半導体集
積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention particularly relates to a semiconductor integrated circuit device having a functional circuit that facilitates circuit checking of a printed wiring board after circuit components are mounted.
一般に、ゲートアレイ等のセミカスタムLSIは、LS
I設計者が所望する機能(Function )に応じ
た回路をLSI内部に組込むことにより、所望する論理
機能構成のLSIを得ることができる。In general, semi-custom LSIs such as gate arrays are
By incorporating into the LSI a circuit according to the function desired by the designer, an LSI having a desired logical function configuration can be obtained.
この種LSIには、一般に、複数の出力1,7号各々の
状態が、複数の入力信号の組合わせによって定まる複雑
な論理機能イ“1・η成をなす。従ってこのようなLS
Iを実装してなる印刷配線基板をインサーキットテスタ
によりチェックする際、実装LSIの入力端子(入力ビ
ン)に単に成る1棟の入力信号を与えてもその信号から
各出力端の正否を判断することはできず、入力信号の7
−クニンスを作成して基板上における回路チェックを行
なわなければならないことから、基板上の部品取付ミス
、半田伺不良、ノやターンの短絡、断線等による回路の
正否を検査する際、その検査には多くの労力並びに時間
を要し、能率の良い検査が実施できないという不都合が
生じていた。Generally speaking, in this type of LSI, the states of each of the plurality of outputs 1 and 7 form a complex logical function i.e.
When checking a printed wiring board on which I is mounted using an in-circuit tester, even if a single input signal is simply applied to the input terminal (input bin) of the mounted LSI, the correctness of each output terminal can be determined from that signal. 7 of the input signal.
- Since it is necessary to create a circuit board and check the circuit on the board, it is necessary to check whether the circuit is correct or not due to component mounting errors, poor solder contact, short circuits or disconnections, etc. on the board. This method requires a lot of labor and time, resulting in the inconvenience that efficient testing cannot be carried out.
本発明は上記実情に鑑みなされたもので、回路部品実装
後における印刷配線基板の回路チェツクを容易かつ迅速
に行なうことのできる機能をもだせた半導体集積回路装
置を提供することを目的とする。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device having a function of easily and quickly checking the circuit of a printed wiring board after circuit components are mounted.
本発明はチップ内部において、機能回路部の出力信号、
又は特定の入力信号を選択的に対応出力ピンに出力する
ゲート回路を各出力ピンそれぞれに対応して設け、これ
ら谷ゲート回路を特定の入力ピン信号により同時選択的
に切換える構成として、各出力ビンに、予め対応付けさ
れた入力信号を選択的に供給できるようにしたものであ
る。これにより、上記選択切換機能をもつLSI例えば
ゲートアレイLSIを印刷配線基板に実装した後、該基
板の回路チェックを行なう際、上記ゲートアレイの入力
端(入力ピン)に与えられた入力信号をチップ内部の機
能回路部をバイパスした状態で選択的に出力端(出力ビ
ン)出力できるため、」二記載板上における回路チェッ
クを容易に行なうことができる。The present invention provides an output signal of a functional circuit section within a chip,
Alternatively, a gate circuit that selectively outputs a specific input signal to the corresponding output pin may be provided corresponding to each output pin, and these valley gate circuits may be simultaneously and selectively switched by a specific input pin signal. It is possible to selectively supply input signals associated with each other in advance. As a result, after mounting an LSI having the above selection switching function, such as a gate array LSI, on a printed wiring board, when checking the circuit of the board, the input signal applied to the input end (input pin) of the gate array can be transferred to the chip. Since it is possible to selectively output the output terminal (output bin) while bypassing the internal functional circuit section, it is possible to easily check the circuit on the "2" board.
以下図面を参照して本プら明の一実施例を説明する。図
中、10はゲートアレイ等のLSIチップ、11はこの
LSIチッチッ10内に設けられた所定の機能回路部(
Function Logic )である。An embodiment of the present invention will be described below with reference to the drawings. In the figure, 10 is an LSI chip such as a gate array, and 11 is a predetermined functional circuit section (
Function Logic).
121HI 22+・・・、12nは上記4幾能回路部
1ノの各入力点11+I2+・・・、 In と対応接
続される入力ビン、I J 1+ 132 + ・・’
+ I Jnは同各出力点01+02、・・・、Onと
対応接続される出力ビンであり、ここでは説明を容易に
するため、入力点数と出力点数とを同数(n)として示
している。141 。121HI 22+..., 12n are input bins correspondingly connected to each input point 11+I2+..., In of the above-mentioned 4 geometric circuit sections 1, IJ 1+ 132+...'
+ I Jn is an output bin correspondingly connected to each of the same output points 01+02, . 141.
142、・・、14nは上記出力点Oし0□、・・・+
Onに対応して設けられたアンド・オア回路、15は
このアンド・オア回路141,142.・・・、14n
の選択制御信号(SC)が印加される特定の制御信号入
力ピン、16はインバータである。上記アンド・オア回
路741.14□、・・、14nはそれぞれ上記制御信
号入力ピン15の信号(SC)状態に従い、機能回路部
11の予め対応付けされた出力点(01+ 021・・
・、On)の信号、又は入力点(■l+I2+”’+I
n)の信号をiすζ択的にLSISフチ1θの出力ビン
13し132.・・・、13nに同時出力するもので、
ここでは上記選択制御信号(SC)が高レベル状態にあ
る(低レベル信号が入力されない)際に、機能回路部1
1の出力点(0,、,0□、・・・+ ’J) n )
M号をそれぞれ対応する出力ビン13..132.・
・・、13nに与え、上記選択制御1.1号(SC)が
低レベル状態にある際に、機能回路部1ノの入力点(I
、、I2+・・・、In)信号を機能回路部11をバイ
パスした状態で対応付けされた出力ビン13..132
.・・・、13nVCJ4える。142,..., 14n are the above output points O and 0□,...+
An AND-OR circuit 15 is provided corresponding to the ON signal. ..., 14n
The specific control signal input pin 16 to which the selection control signal (SC) of is applied is an inverter. The AND-OR circuits 741.14□, . . . , 14n each output the pre-corresponding output points (01+021, . . .
・, On) signal or input point (■l+I2+"'+I
n) signal i is selectively output to the LSIS edge 1θ output bin 13 and 132 . ..., which simultaneously outputs to 13n,
Here, when the selection control signal (SC) is in a high level state (no low level signal is input), the functional circuit section 1
1 output point (0,,,0□,...+'J) n)
Output bins 13 . .. 132.・
..., 13n, and when the selection control No. 1.1 (SC) is in a low level state, the input point (I
, , I2+ . . . , In) signals are output from the output bins 13 . .. 132
.. ..., 13nVCJ4.
ここで図面を参照して一実施例の動作を説明する。図示
LSI千ノア”1oを実装してなる印刷配線基板のイン
サーキットテスタによる回路チェ、り時に赴い−C1上
記LSIチップ1oの制御信号入力ビン15にf=Iら
信号が印加されず、該入力ビン15の(Fj号状態がゾ
ルアップ抵抗(R)の作用で高レベルとなっている際は
、アンド・オア回路141+ 142 +・・・、14
nが機能回路部11の各出力点01+ 021・・・、
Onの1−号”をゼく択し、該信号をそれぞれ対応する
出力ビン131.1.?2゜・・・、13nに出力する
。従ってこの際1rよ従来と同様に、成る1つの出力ビ
ンl 3i (i=1 、2 。The operation of one embodiment will now be described with reference to the drawings. When performing a circuit check using an in-circuit tester on a printed wiring board on which the illustrated LSI chip 1o is mounted, a signal such as f=I is not applied to the control signal input bin 15 of the LSI chip 1o, and the input When the (Fj state of bin 15 is at a high level due to the action of the sol-up resistor (R), the AND-OR circuits 141+ 142 +..., 14
n is each output point 01+021... of the functional circuit section 11,
"1-" of "On" is selected, and the signals are output to the corresponding output bins 131.1.?2°..., 13n.Therefore, in this case, as in the past, one output consisting of 1r is selected. Bin l 3i (i=1, 2.
・・・、n)の信号状態が単純に成る1つの入カビ°ン
12iの信号状態のみによっては定寸C)ず、入力ビン
121,12□、・・・、12nに印加されるイ、τリ
シ)組合わせによって定する。1Qllら、l−、iJ
L各出カビ□ン131+J 321 ・・・+13n各
々の1、−7号状j7.j? ir、t l!lJj
if二回路部1ノの論理機能及び各人力点1.、I2.
・・・。. . , n) are simply applied to the input bins 121, 12□, . . . , 12n. It is determined by the combination. 1Qll et al., l-, iJ
L each mold □n 131+J 321...+13n each 1, -7 j7. j? ir, t l! lJj
Logic function of IF2 circuit part 1 and each human power point 1. , I2.
....
Inの(ffi号状態によって定貫るもので、01 =
=11(11+ I2 + ”’ + In )02
=f2 (11,I2 + −、In C0n=fn
(11+I2+”’+In)の如くとなり、各出力点0
1,0□、・・、(月1の信号状態を入゛力信号から単
純に定)りることができない。従ってインサーキットテ
スタの接触ビ′ンより、実装LSIチノ:7″10の成
る人力ピン/21に=i、2.・・・、n)に特定の信
号を力えてもその信号から出力ビン1.9iの信号状聾
が一意に定するものてはなく、各出力ピン13..13
□。It is constant depending on the state of (ffi) of In, and 01 =
=11(11+I2+”'+In)02
= f2 (11, I2 + -, In C0n=fn
(11+I2+"'+In), each output point 0
1,0□,... (the signal state of month 1 cannot be determined simply from the input signal). Therefore, even if you input a specific signal to the pin/21 (=i, 2..., n) of the mounted LSI chino: 7"10 from the contact bin of the in-circuit tester, the signal will be output from the output bin 1. .9i's signal state is not uniquely determined, and each output pin 13..13
□.
・・・、13nの接翫j1.・やターンにそれぞれノ9
[望する信号を出力したい場合には、LSIチノflo
内の機能回路部1)の論理俄能を考臆したl時定の入力
信号のシーフェンスを作成して、その入力信号を入力ビ
ン121 、l 22.・・、12nに与えてやらねば
ならない。..., 13n attachment j1.・9 on each turn
[If you want to output the desired signal, use LSI Chinoflo
A sea fence of l time-determined input signals is created taking into consideration the logic capability of the functional circuit unit 1) in the input bins 121, l22. ..., I have to give it to 12n.
そこで上す己LSI f、、フ゛1θ内の入出力回路を
含む回路パターンのチェックを行なう昨、インザーキノ
トテスタの接触ビンを介し、実装LSIチップ′10の
1tll j!l信号人カビン15に、選択的に低レベ
ルの信号を印加する。これによってLSIチップ10内
のアンド・オア回路141 。Therefore, when I checked the circuit pattern including the input/output circuits in the LSI f, 1θ, I tested the 1tll j! A low-level signal is selectively applied to the signal cabinet 15. This causes an AND-OR circuit 141 in the LSI chip 10.
I42.・、14nは、機能回路部11の各入力点I、
、I2.・・・、Inの信号をそれぞれ予め対応利けさ
れた各出力点Ol+ 02 +・・・+Onにそのまま
の状r&て出力するユ′へ択モードとなる。即ち、ここ
では、0、=1゜
0□=12
On=In
となる。このように制御信号入力ビン15を低レベルに
することにより、入力点I、、I2.・・・。I42. , 14n are each input point I of the functional circuit section 11,
, I2. . . , In signals are output as they are to respective output points Ol+ 02 + . That is, here, 0,=1°0□=12 On=In. By setting the control signal input bin 15 to a low level in this way, the input points I, , I2 . ....
Inに供給された入カイへ号が仕朽止回路部Ilをパイ
ノゼスした状態で対応する出力点01,02 +・・・
。In the state where the input signal supplied to In pinoses the termination circuit section Il, the corresponding output points 01, 02 +...
.
Onより出力されるため、LSIチノチッ10を実装し
てなる印刷配線基板の回路チ、ツクは(夕めて簡素化さ
れ、容易かつ短時間で?h望の回路パターンチェ、りを
行なうことができる。Since the output is output from ON, the circuit pattern of the printed wiring board mounted with the LSI chip 10 is simplified, and the desired circuit pattern can be checked easily and in a short time. can.
尚、上記した実jifi例においては、説明の便宜上、
機能回路部1)の入力点数と出力点数とを同数(n)と
して示しているが、例えは出力点数が入力点数” (■
I+I7+”’+In)より少ないm(01+ 02
+ ”’ + Om )である際It、01ニエス
2−I2
0m = Im
として、各出力点0..o2.・・・、01n を入力
点■1゜■2.・・・、 Imに対応付け、入力点Ii
の(、Y 、p5を選択的に出力点Oiに出力する構成
とすればよく、又、これとは逆に、入力点数が出力点数
n(OH。In addition, in the above-mentioned actual jifi example, for convenience of explanation,
The number of input points and the number of output points of the functional circuit section 1) are shown as the same number (n), but for example, the number of output points is equal to the number of input points (■
I+I7+”'+In) less than m(01+02
+ ”' + Om), then it, 01 nies 2-I2 0m = Im, each output point 0..o2...., 01n corresponds to the input point ■1゜■2...., Im Attach, input point Ii
(, Y, p5 may be selectively output to the output point Oi, or conversely, if the number of input points is the number of output points n(OH).
021−・+ On )より少ないm(II + I
2 + ””+ Im)である際は、
01″=I。021−・+ On ) less than m(II + I
2 + “” + Im), then 01″=I.
0 、、 = I 2 0mニlm 0m+ 1 = I 。0,, = I2 0m 0m + 1 = I.
On = I (1,2,−、m)
として、各出力点01 + 021・・・+Onを入力
、曵II 。As On = I (1, 2, -, m), input each output point 01 + 021...+On, 曵II.
r、・・・、Imに対応付け、人力点Itの信号全選択
的に出力する(ilへ成とすればよい。It is associated with r, .
以上詳記したように本発明の半導体集積回路装(6゛、
によれば、機能回路部の各出力点より、予め対応付けさ
れた入力点の信号を選択的に出力でき、これにより上記
半導体集積回路装(1′Lを実装してなる印刷配線基板
の回路チェックを容易にしかも迅速に行なうことができ
る。As detailed above, the semiconductor integrated circuit device (6゛,
According to the above, it is possible to selectively output signals from input points associated with each other in advance from each output point of a functional circuit section, and thereby the circuit of the printed wiring board formed by mounting the above-mentioned semiconductor integrated circuit device (1'L). Checking can be done easily and quickly.
図は本発明の一実施例を示すブロック図1である。
10・・・LSIチップ、11・・・機(化回路部、1
21゜122、・・・、12n・・・入力ピン、131
,132+・・・。
13n・・・出力ピン、141+I (21・・、14
n・・・アンド・オア回路、15・・・制イ11ヤ信号
入力ビン、■、。
I21 ・・・HIrr+ ・=入力点、01 + 0
21 ・・・+ On +++ i3力点。The figure is a block diagram 1 showing one embodiment of the present invention. 10...LSI chip, 11...machine (chemical circuit section, 1
21゜122,..., 12n...Input pin, 131
,132+... 13n...Output pin, 141+I (21..., 14
n...AND OR circuit, 15...Control I 11Y signal input bin, ■. I21...HIrr+ ・=input point, 01 + 0
21 ...+ On +++ i3 emphasis.
Claims (1)
半導体集積回路装置において、前記各出力点とこの出力
点に固有の各信号導出ラインとの間に、予め対応付けさ
れ/ヒ特定の入力点信号又は対応する出力点信号を選択
的に出力する複数のゲート回路を設け、この各ゲート回
路を特定の入力ビン信号により同時選択的に切換制御す
る構造とした半導体集積回路装置。In a semiconductor integrated circuit device provided with a functional circuit section having a plurality of input points and output points, each of the output points and each signal derivation line specific to this output point are associated with each other in advance. A semiconductor integrated circuit device having a structure in which a plurality of gate circuits are provided for selectively outputting an input point signal or a corresponding output point signal, and each gate circuit is simultaneously and selectively switched and controlled by a specific input bin signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11216183A JPS604238A (en) | 1983-06-22 | 1983-06-22 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11216183A JPS604238A (en) | 1983-06-22 | 1983-06-22 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS604238A true JPS604238A (en) | 1985-01-10 |
Family
ID=14579763
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11216183A Pending JPS604238A (en) | 1983-06-22 | 1983-06-22 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS604238A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7819125B2 (en) | 2002-03-28 | 2010-10-26 | L'oreal | Case for packaging a product |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5823473A (en) * | 1981-08-06 | 1983-02-12 | Mitsubishi Electric Corp | Multiple-purpose integrated circuit |
-
1983
- 1983-06-22 JP JP11216183A patent/JPS604238A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5823473A (en) * | 1981-08-06 | 1983-02-12 | Mitsubishi Electric Corp | Multiple-purpose integrated circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7819125B2 (en) | 2002-03-28 | 2010-10-26 | L'oreal | Case for packaging a product |
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