JPS6034049A - Built-in capacitor type semiconductor device and manufacture thereof - Google Patents

Built-in capacitor type semiconductor device and manufacture thereof

Info

Publication number
JPS6034049A
JPS6034049A JP58143362A JP14336283A JPS6034049A JP S6034049 A JPS6034049 A JP S6034049A JP 58143362 A JP58143362 A JP 58143362A JP 14336283 A JP14336283 A JP 14336283A JP S6034049 A JPS6034049 A JP S6034049A
Authority
JP
Japan
Prior art keywords
lead
semiconductor chip
capacitor
mounting part
chip mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58143362A
Other languages
Japanese (ja)
Inventor
Koichi Takegawa
光一 竹川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58143362A priority Critical patent/JPS6034049A/en
Publication of JPS6034049A publication Critical patent/JPS6034049A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To produce the titled semiconductor device with highly reliable built-in capacitor by a method wherein a chip loader supporting lead is connected to an adjusting external lead while one of the other chip loader or supporting lead therof is connected to an adjusting external lead through the intermediary of a chip type capacitor. CONSTITUTION:A semiconductor chip loader supporting lead 10c is connected to an adjusting external lead 13c to be a grounding lead while a chip type capacitor loader 16c is provided on the position where the other supporting lead 10c' confronts to another adjusting external lead 12c to fix a capacitor 14c. In such a constitution, a sounded noise absorbing capacitor is inserted between the load for power supply 12c and the grounding lead 13c to prevent an erroneous operation from happening. Moreover, due to adoption of a chip type capacitor, the title device may be miniaturized and highly integrated under no influence of inductance of lead at an arbitrary capacity value improving thermal shock resistance due to thermal expansion difference from resin subject to high reliability at low cost may be realized.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明はコンデンサ内蔵型半導体装置及びその製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor device with a built-in capacitor and a method for manufacturing the same.

〔従来技術〕 従来、半導体装置を電子装置に実装する場合、半導体チ
ップ（以下ＩＣテップと記す）から発生したノイズによ
る誤動作を防止するために半導体装置の電源リードとア
ースリードとの間に個別コンデンサが挿入されていた。[Prior Art] Conventionally, when a semiconductor device is mounted on an electronic device, an individual capacitor is installed between the power lead and the ground lead of the semiconductor device in order to prevent malfunction due to noise generated from the semiconductor chip (hereinafter referred to as IC chip). had been inserted.

Ｃのような、半導体装置の外に実装するコンデンサには
、半導体装置とコンデンサ間のリード線のインダクタン
スによシ効果が十分でないこと、及びコンデン？を半導
体装置毎に実装しなくてはならないためプリント板の実
装密度の低下を引起こしていたこと等の欠点があった。For capacitors like C, which are mounted outside the semiconductor device, the inductance of the lead wire between the semiconductor device and the capacitor does not have a sufficient effect, and the capacitor is This method had drawbacks such as a reduction in the mounting density of the printed circuit board because it had to be mounted on each semiconductor device.

そこでこれら欠点を解決するために最近はコンデンサを
半導体装置に内蔵するものが幾つか試久られている。In order to solve these drawbacks, several semiconductor devices have recently been tested in which a capacitor is built into a semiconductor device.

従来のコンデンサ内蔵型半導体装置を、第１図〜第３図
によって説明すると、従来のコンデンサ内蔵を半導体装
置のうち、セラミックパッケージについては５例えば第
１図の断面図に示す如く。A conventional semiconductor device with a built-in capacitor will be explained with reference to FIGS. 1 to 3. Among conventional semiconductor devices with a built-in capacitor, a ceramic package is shown in FIG.

パッケージ１ａの半導体チップ搭載部２ａにＩＣチップ
３ａｔ−固着し、ＩＣチップの電極と外部導出リードの
内部リード部とを金（Ａｕ）またはアルミニウム（ＡＪ
　）のボンディングワイヤー４ａによシワイヤーボンデ
ィングし、内部リード部のうち電源リードとアースリー
ドに直接コンデンサ５ａのリード６ａを接続し、コンデ
ンサ５ａの上部からキャップ７８ｔかぶせ封止するもの
や、セラミックパッケージのセラミック基板積層間にコ
ンデン？を挾みこんで同様の効果を得るもの等幾つかの
方法が試みられている。The IC chip 3at- is fixed to the semiconductor chip mounting part 2a of the package 1a, and the electrodes of the IC chip and the internal lead parts of the external leads are made of gold (Au) or aluminum (AJ).
), connect the lead 6a of the capacitor 5a directly to the power supply lead and the ground lead among the internal leads, and cover and seal the cap 78t from the top of the capacitor 5a. Condenser between ceramic substrate layers? Several methods have been tried, including one that achieves a similar effect by inserting

これに対し、大量かつ安価に生産されるプラスチックパ
ッケージについては、前記セラミックパッケージにおけ
るコンデンサ内蔵方法のうち、前者については製造が困
難で量産性に乏しいことがら、また後者についてはプラ
スチックパッケージの構造上不可能であること等から、
これらの方法は採用され難く、具体的なコンデンサ内蔵
型プラスチックパッケージの例は少ない。コンデンサ内
蔵型プラスチックパッケージの一例としては、第２１平
面図と第３１断面図に示す如く、外部導出用リード８ｂ
及び半導体チップ搭載部２ｂｔ−備えたリードフレーム
９ｂについて、あらかじめ半導体チップ搭載部２ｂｔ−
中央で分離しかつ半導体チップ搭載部支持リード１０ｂ
の所定の位置で段差１１ｂｔ−設け、さらに電源リード
である外部導出用リード１２ｂｕ’アースリードである
外部導出用リード１３ｂとを半導体チップ搭載部支持リ
ード１０ｂに接続させておき１次にチップ型コンデンサ
１４ｂ”ｔ−半導体チップ搭載部２ｂに導電性接着剤等
で固着し、ＩＣチップ３ｂをチップ型コンデンサ１４ｂ
の上に固着し、ＩＣテップ３ｂの電極と内部リードとを
ワイヤボンディング用Ａｕ線４ｂによりワイヤーボンデ
ィングし、エポキシ樹脂１５ｂ等で封止し、コンデンサ
の内蔵を実現する方法がある。On the other hand, regarding plastic packages that are produced in large quantities and at low cost, among the methods for incorporating capacitors in ceramic packages, the former is difficult to manufacture and has poor mass productivity, and the latter is problematic due to the structure of the plastic package. Because it is possible, etc.
These methods are difficult to adopt, and there are few concrete examples of plastic packages with built-in capacitors. As an example of a plastic package with a built-in capacitor, as shown in the 21st plan view and the 31st sectional view, the lead 8b for leading to the outside is
Regarding the lead frame 9b equipped with the semiconductor chip mounting portion 2bt-, the semiconductor chip mounting portion 2bt-
Separated at the center and supporting leads 10b for the semiconductor chip mounting portion
A step 11bt- is provided at a predetermined position of the chip type capacitor. 14b"t - The IC chip 3b is fixed to the semiconductor chip mounting part 2b with a conductive adhesive or the like, and the IC chip 3b is attached to the chip type capacitor 14b.
There is a method in which the electrodes of the IC tip 3b and the internal leads are wire-bonded using the Au wire 4b for wire bonding, and the capacitor is sealed with an epoxy resin 15b or the like to realize a built-in capacitor.

この方法によれば、チップ型コンデンサｉＩＣチップと
同様の方法で容易に製造が可能であるという利点がある
。しかし、該チップ梨コンデンサは、その構造上ＩＣチ
ップより大きいものでなくてはならないため、ＩＣチッ
プが大きい場合、チップ型コンデンサもそれに伴なって
大きくなシ。This method has the advantage that it can be easily manufactured in the same manner as the chip type capacitor iIC chip. However, because the chip capacitor must be larger than the IC chip due to its structure, if the IC chip is large, the chip capacitor will also be large accordingly.

かつ薄いため、チップ型コンデンサの製造が困難になシ
、従って価格が高くなること及びチップ型コンデンサの
強度が十分でないこと、さらには大きなチップ型コンデ
ンサを内蔵したために、チップ型コンデンサと樹脂との
熱膨張差により半導体装置の耐熱衝撃性が著しく低下す
る等価格上及び信頼性上の大きな欠点があった。Since chip capacitors are thin and difficult to manufacture, they are expensive, chip capacitors are not strong enough, and since they contain large chip capacitors, it is difficult to make chip capacitors with resin. This has had major disadvantages in terms of cost and reliability, such as the thermal shock resistance of the semiconductor device being significantly reduced due to the difference in thermal expansion.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上記の欠点を除去し、信頼性が高く、安
価なコンデンサ内蔵賊半導体装置及びその製造方法を提
供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a highly reliable and inexpensive semiconductor device with a built-in capacitor and a method for manufacturing the same.

〔発明の構成〕[Structure of the invention]

本発明の第１の発明のコンデンサ内蔵型半導体装置は半
導体チップ搭載部、該半導体チップ搭載部に接続された
半導体チップ搭載部支持リード及び外部導出用リードを
有するリードフレームに半導体チップ並びにコンデンサ
を搭載したコンデンサ内蔵型半導体装置において、１本
の半導体チップ搭載部支持リードに隣接する少なくとも
１本の外部導出リードが半導体チップ搭載部支持リード
に接続され、半導体チップ搭載部又は少なくとも１本の
他の半導体チップ搭載部支持リードが該半導体チップ搭
載部支持リード又は半導体チップ搭載部に隣接する少な
くとも１本の外部導出用リードとチップ型コンデンサを
介して接続されることにより構成される。A semiconductor device with a built-in capacitor according to a first aspect of the present invention has a semiconductor chip and a capacitor mounted on a lead frame having a semiconductor chip mounting part, a semiconductor chip mounting part support lead connected to the semiconductor chip mounting part, and an external lead-out lead. In a semiconductor device with a built-in capacitor, at least one external lead adjacent to one semiconductor chip mounting part support lead is connected to the semiconductor chip mounting part support lead, and the semiconductor chip mounting part or at least one other semiconductor The chip mounting part support lead is connected to the semiconductor chip mounting part support lead or at least one external lead adjacent to the semiconductor chip mounting part via a chip type capacitor.

また、本発明の第２の発明のコンデンサ内蔵を半導体装
置の製造方法は、１本の半導体チップ搭載部支持リード
に瞬接する少なくとも１本の外部導出リードが半導体チ
ップ搭載部支持リードに接続され、半導体チップ搭載部
又は少なくとも１本の他の半導体チップ搭載部支持リー
ドに隣接する少なくとも１本の外部導出リードと前記半
導体チップ搭載部又は半導体チップ搭載部支持リードと
をチップ型コンデンサで接続するためのスリット又は接
続部を備えたリードフレームを準備する工程と、半導体
チップを半導体チップ搭載部に固着する工程と、少なく
とも１個のチップ型コンデンサを前記スリット又は接続
部に固着する工程と、前記半導体チップの電極と外部導
出用リードとをワイヤポンディングする工程と、樹脂封
止する工程とを含んで構成される。Further, in the method of manufacturing a semiconductor device with a built-in capacitor according to the second aspect of the present invention, at least one external lead that momentarily contacts one semiconductor chip mounting part support lead is connected to the semiconductor chip mounting part support lead, for connecting at least one external lead adjacent to the semiconductor chip mounting part or at least one other semiconductor chip mounting part support lead to the semiconductor chip mounting part or the semiconductor chip mounting part support lead using a chip type capacitor; a step of preparing a lead frame having a slit or a connection portion; a step of fixing a semiconductor chip to a semiconductor chip mounting portion; a step of fixing at least one chip-type capacitor to the slit or connection portion; and a step of fixing the semiconductor chip to the slit or connection portion. The structure includes the steps of wire bonding the electrode and the lead for external extraction, and sealing the electrode with resin.

〔実施例の説明〕[Explanation of Examples]

次に、本発明の実施例について１図面を参照して説明す
る。Next, an embodiment of the present invention will be described with reference to one drawing.

第４図、第５図は本発明の第１の実施例の説明のための
図で、第４図ｉ＃！造途中工程に於ける平面図、第５図
は樹脂封止後の第４図Ｂ−Ｂ’線の断面図である。第４
図及び第５図に示すように。4 and 5 are diagrams for explaining the first embodiment of the present invention, and FIG. 4 i#! FIG. 5 is a plan view during the manufacturing process, and a sectional view taken along line BB' in FIG. 4 after resin sealing. Fourth
As shown in FIG.

１本の半導体チップ搭載部支持リードＩＯＣに隣接する
１本の外部導出用リード１３ｃは半導体チップ搭載部支
持リードＩＯＣに接続されアースリードを形成、また他
の半導体チップ搭載部支持リードＩＯＣ’がこれに隣接
する少なくとも１本の外部導出用リード１２ｃと対向す
る位置にチップ型コンデンサ搭載部１６Ｃが設けられ、
そこにチップ型コンデンサ１４Ｃが固着されている。One external lead 13c adjacent to one semiconductor chip mounting part support lead IOC is connected to the semiconductor chip mounting part support lead IOC to form a ground lead, and the other semiconductor chip mounting part support lead IOC' is connected to this. A chip-type capacitor mounting portion 16C is provided at a position facing at least one external lead-out lead 12c adjacent to the
A chip type capacitor 14C is fixed thereto.

従って電源リードである外部導出用リード１２Ｃとアー
スリードである外部導出用リード１３ｃの間にＩＣチッ
プから発生したノイズによる誤動作を防止するためのノ
イズ吸収用コンデンサが挿入されたことになる。しかも
コンデンサはチップ型コンデンサが用いられているので
リード線のインダクタンスの影響もなく、容量も自由に
選定できる特徴があり、小型化、高密度化が達成できる
と共に小壁のためチップ型コンデンサの製作が容易であ
シ、又耐熱衝撃性も改善され信頼性が向上する。Therefore, a noise absorbing capacitor is inserted between the external lead lead 12C, which is a power supply lead, and the external lead lead 13c, which is a ground lead, to prevent malfunctions caused by noise generated from the IC chip. Moreover, since the capacitor is a chip type capacitor, there is no influence from the inductance of the lead wire, and the capacitance can be selected freely.In addition, it is possible to achieve miniaturization and high density, and because the walls are small, chip type capacitors can be manufactured. In addition, thermal shock resistance is improved and reliability is improved.

次に本発明の第１の実施例によるコンデンサ内蔵を半導
体装置の製造方法の一実施例について説明する。第４図
及び第５図に示すように％　１本の半導体チップ搭載部
支持リード１０ｃに隣接する少なくとも１本の外部導出
用リード１３Ｃが半導体チップ搭載部支持リードＩＯＣ
に接続され、少なくとも１本の他の半導体チップ搭載部
支持り−ド１００′に隣接する少なくとも１本の外部導
出用リードが対向する部分にチップ型コンデンサを搭載
するためのチップ賊コンデンサ搭載部１６Ｃ全備えたり
一ド７レーム９０を準備する。こ＼で準備するリードフ
レームは従来の構造のものも使用できるがチップ型コン
デンサの大きさにより、チップ型コンデンサ搭載部１６
（４−別に設けると好都合である。Next, an embodiment of a method for manufacturing a semiconductor device with a built-in capacitor according to the first embodiment of the present invention will be described. As shown in FIGS. 4 and 5, at least one external lead 13C adjacent to one semiconductor chip mounting part support lead 10c is connected to the semiconductor chip mounting part support lead IOC.
A chip capacitor mounting section 16C for mounting a chip capacitor on a portion connected to the semiconductor chip mounting section support board 100' and facing at least one external lead lead adjacent to at least one other semiconductor chip mounting section support board 100'. Prepare everything or prepare 1 card, 7 frames, 90. The lead frame prepared here can be of a conventional structure, but depending on the size of the chip capacitor, the chip capacitor mounting part 16
(4-It is convenient to provide it separately.

次に、リードフレーム９ｃの電源リードである外部導出
用リード１２ｃと半導体チップ搭載部支持リード１０ｃ
との間の適当な位置、本実施例ではチップ型コンデンサ
搭載部１６ｃにチップ型コンデンサ１４ｃのｑ！ｒ電極
を導電性ペーストや半田等で各々固着する。Next, the external lead 12c, which is the power supply lead of the lead frame 9c, and the semiconductor chip mounting part support lead 10c.
In this embodiment, the chip type capacitor 14c is placed at an appropriate position between the chip type capacitor mounting portion 16c and the q! The r electrodes are each fixed with conductive paste, solder, or the like.

ここで使用するチップ型コンデンサの大きさは。What is the size of the chip capacitor used here?

該コンデンサの容量が所望の値であれば、製造上生じる
制限のみで小型化が可能であり、安価で高信頼度のチッ
プ型コンデンサを使用できる。If the capacitance of the capacitor is a desired value, it is possible to downsize the capacitor with only manufacturing restrictions, and an inexpensive and highly reliable chip-type capacitor can be used.

次にＩＣテップ３ｃを半導体チップ搭載部に固着する。Next, the IC chip 3c is fixed to the semiconductor chip mounting section.

なお１本実施例ではチップ型コンデン′９−１４ｃｔｌ
−固着した後にＩＣチップ３０を固着したが固着工程を
逆にしても問題はない。In this example, a chip type capacitor '9-14ctl
- Although the IC chip 30 was fixed after fixing, there is no problem even if the fixing process is reversed.

また、ここでチップ型コンデンサ’ｔ＝ＩＣチップの下
に敷〈従来の方法では、前記チップ型コンデンサのそり
等を考慮してＩＣチップの固着方法は導電性ペーストや
半田等のソフトンルダーに限られていたが、本発明の実
施例においては固着方法に制限はな（、ＩＣチップの特
性や製造方法の都合によシ自由に選択できる利点がある
。In addition, here, the chip type capacitor 't = placed under the IC chip. In the conventional method, considering the warpage of the chip type capacitor, the method of fixing the IC chip is to use a soft adhesive such as conductive paste or solder. However, in the embodiments of the present invention, there are no restrictions on the fixing method (there is an advantage that it can be freely selected depending on the characteristics of the IC chip and the manufacturing method).

次に、ＩＣテップ３Ｃの電極と外部導出用ＩＪ−ドの内
部リードとをボンディングワイヤ４ｃによシワイヤボン
ディングする。Next, the electrodes of the IC chip 3C and the internal leads of the IJ-board for external lead-out are wire-bonded using the bonding wire 4c.

しかるのち封入樹脂例えばエポキシ樹脂１５ｃ等で封止
すれば本実施例の半導体装置が完成する。Thereafter, the semiconductor device of this embodiment is completed by sealing with a sealing resin such as epoxy resin 15c.

第６図、第７図は本発明の第２の実施例の説明のための
図で、第６図は製造途中工程に於ける平面図、第７図は
樹脂封止後の第６図Ｃ−Ｃ’線の断面図である。6 and 7 are diagrams for explaining the second embodiment of the present invention, FIG. 6 is a plan view in the middle of manufacturing process, and FIG. 7 is after resin sealing. It is a sectional view taken along the -C' line.

第６図及び第７図に示すように、１本の半導体チップ搭
載部支持リード１０ｃに隣接する１本の外部導出用リー
ド１３ｃは半導体チップ搭載部支持リード１０ｃに接続
されアースリード全形成、また他の半導体チップ搭載部
支持リードはこれに隣接する電源リードとなる外部導出
用リード１２Ｃと接続されチップ型コンデンサを接続す
るチップ型コンデンサ搭載部は半導体チップ搭載部支持
リード１００′の１部にスリン）１７Ｃを設けて形成さ
れるがチップ型コンデンサの大きさによりチップ型コン
デンサ搭載部１６Ｃを別に設けると好都合である。As shown in FIGS. 6 and 7, one external lead 13c adjacent to one semiconductor chip mounting part support lead 10c is connected to the semiconductor chip mounting part support lead 10c, and the ground lead is completely formed and The other semiconductor chip mounting part support lead is connected to the adjacent external lead 12C which is a power supply lead, and the chip type capacitor mounting part which connects the chip capacitor is attached to a part of the semiconductor chip mounting part support lead 100'. ) 17C, but depending on the size of the chip capacitor, it may be convenient to separately provide a chip capacitor mounting portion 16C.

チップ型コンデンサ１４ｃはチップ哉コンデンサ搭載部
１６ｃに固着され、その結果第１の実施例とことなシチ
ップ型コンデンサは半導体チップ搭載部支持リード部に
設けられるが第１の実施例と同様電源リードである外部
導出用リード１２ｃとアースリードである外部導出用リ
ード１３ｃの間にＩＣチップ３Ｃから発生したノイズに
よる誤動作を防止するためのノイズ吸収用のチップ型コ
ンデンサが挿入されたことになり第１の実施例と同様な
効果が得られる。The chip type capacitor 14c is fixed to the chip capacitor mounting part 16c, and as a result, the chip type capacitor, which is different from the first embodiment, is provided in the support lead part of the semiconductor chip mounting part, but it is not connected to the power supply lead as in the first embodiment. A noise-absorbing chip capacitor is inserted between a certain external lead-out lead 12c and the ground lead 13c to prevent malfunctions caused by noise generated from the IC chip 3C. Effects similar to those of the embodiment can be obtained.

次に、第２の実施例の製造方法につき説明する。Next, a manufacturing method of the second embodiment will be explained.

本杭２の実施例の製造方法は大部分第１の実施例に準す
るが、第６図、第７図に示すように、外部導出用リード
８ｃ及び半導体チップ搭載部２ｃｅ備えたリードフレー
ム９ｃについて、あらかじめ半導体チップ搭載部支持リ
ードＩＯＣ及び１００′とアースリードである外部導出
用リード１３ｃ及び電源リードである外部導出用リード
１２ｃとをそれぞれあらかじめ接続させておく。The manufacturing method of this embodiment of the pile 2 is mostly based on the first embodiment, but as shown in FIG. 6 and FIG. Regarding this, the semiconductor chip mounting portion support leads IOC and 100' are connected in advance to the external lead-out lead 13c, which is a ground lead, and the external lead-out lead 12c, which is a power lead, respectively.

次いで、電源リードまたはアースリードと接続された半
導体チップ搭載部支持リードのいずれが一方の側におい
て５本実施例では電源リード側において、接続個所と半
導体チップ搭載部との間の適当な位置、本実施例では半
導体チップ搭載部支持リード１０ｃ”ｅ切断分離し、ス
リット１７ｃｔ＝設けたものを準備する。なお、チップ
型コンデンサの大きさによっては、切断分離された両端
部にチップ型コンデンサ搭載部１６ｃ金別に設けるとよ
い。Next, either the power supply lead or the ground lead and the semiconductor chip mounting part support lead connected to the semiconductor chip mounting part are connected to one side. In the embodiment, a semiconductor chip mounting part support lead 10c"e is cut and separated, and a slit 17ct is prepared. Depending on the size of the chip capacitor, a chip capacitor mounting part 16c is cut and separated at both ends. It would be good to set it up separately for money.

次に、半導体チップ搭載部支持リードの切断分離された
両端部上又は両端部間にチップ型コンデンサ１４Ｃの各
電極を導電性ペーストや半田で各各固着する。Next, each electrode of the chip capacitor 14C is fixed on or between the cut and separated ends of the semiconductor chip mounting portion support lead using conductive paste or solder.

次に、ＩＣチップ３Ｃを半導体チップ搭載部２Ｃに固着
し、次いで、ＩＣチップの電極と外部導出用リードの内
部リードとをワイヤボンディングし、エポキシ樹脂１５
Ｃ等で封止すると本杭２の実施例は完成する。Next, the IC chip 3C is fixed to the semiconductor chip mounting part 2C, and then the electrodes of the IC chip and the internal leads of the external leads are wire-bonded, and the epoxy resin 15
After sealing with C or the like, the embodiment of the present pile 2 is completed.

なお本実施例の方法によれば、電源リード及びアースリ
ードと半導体チップ搭載部支持リードは、あらかじめ接
続されているのでリードフレームの形成が容易であり、
かつチップ型コンデンサ搭載部のスリットの位置は自由
に決定できるのでリードフレームの汎用性は向上する。According to the method of this embodiment, the power supply lead, the ground lead, and the semiconductor chip mounting part support lead are connected in advance, so it is easy to form the lead frame.
In addition, the position of the slit in the chip-type capacitor mounting portion can be freely determined, improving the versatility of the lead frame.

特にテップ唄コンデンサが会席のときは効果的である。It is especially effective when the tep-uta condenser is used for kaiseki.

その他第１の実施例で述べた効果はほぼ本実施例でも得
られることは説明するまでもない。It goes without saying that most of the other effects described in the first embodiment can also be obtained in this embodiment.

第８図は本発明の第３の実施例の製造途中工程に於ける
断面図である。FIG. 8 is a cross-sectional view of the third embodiment of the present invention during the manufacturing process.

第８図に示すように、アース側の半導体チップ搭載部支
持リード１０ｄは外部導出用リード１３ｄと接続され、
他方の半導体チップ搭載部支持リード１０ｄ′は電源リ
ードである外部導出用り−ド１２Ｃと接続され、半導体
チップ搭載部支持リードにはスリン）１７ｄｔ：有する
チップ型コンデンサ搭載部１６ｄ力ｉ設けられ、核部１
６ｄにはチップ型コン゛デ／す１４ｄが固着されており
、電源リードの外部導出用リード１２Ｃとアースリード
の外部導出用リード１３ｄの間にＩＣチップから発生し
たノイズによる誤動作全防止するためのノイズ吸収用の
チップ型コンデンサが挿入されたことになり本発明の効
果が得られる。また本実施例では半導体チップ搭載部支
持リード１０ｄ’に隣接する外部導出用リードでなく半
導体チップ搭載部２ｄとこれに隣接する外部導出用リー
ド１２ｄとの間にスリット１７ｄ’に有するチップ型コ
ンデンサ搭載部１６ｄ’ｔ−設け、ここにチップ型コン
デンサ１４ｄ’　ｋ設けたもので、チップ梨コンデンザ
１４ｄ’単独で第１．第２の実施例と同様な効果が得ら
れると共に本実施例のように組合せ匣用することにより
ｒ実用目的に合致した効果が得られる。As shown in FIG. 8, the semiconductor chip mounting part support lead 10d on the ground side is connected to the external lead 13d,
The other semiconductor chip mounting part support lead 10d' is connected to an external lead-out lead 12C which is a power supply lead, and the semiconductor chip mounting part support lead is provided with a chip type capacitor mounting part 16d having a sulin) 17dt. Core part 1
A chip type capacitor 14d is fixed to 6d, and between the power supply lead external lead 12C and the ground lead external lead 13d, there is a chip type capacitor 14d to completely prevent malfunction due to noise generated from the IC chip. Since a chip type capacitor for noise absorption is inserted, the effects of the present invention can be obtained. In addition, in this embodiment, the chip type capacitor is mounted in the slit 17d' between the semiconductor chip mounting part 2d and the adjacent external lead 12d, instead of the external lead-out lead adjacent to the semiconductor chip mounting part support lead 10d'. A chip type capacitor 14d'k is provided here, and the chip type capacitor 14d' alone is connected to the first part 16d't-. The same effects as in the second embodiment can be obtained, and by using a combination case as in this embodiment, an effect meeting the practical purpose can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明によれば、コンデンサを内蔵す
ることにより電源とアース間等のノイズ防止の効果があ
げられる。またコンデンサを半導体装置の外に実装する
必要がないので実装密度を向上させることができると共
にコンデンサのリード線によるインダクタンスの悪影響
を防ぐことができる。また従来のコンデンサ内蔵型のプ
ラスチックパッケージで生じていたコンデンサや半導体
装置の耐熱衝撃性等の信頼性の低下の問題や、半導体装
置の製造上の制限等の欠点を除去できるので、安価で信
頼性の優れたコンデンサ内蔵型半導体装置が得られる。As explained above, according to the present invention, by incorporating a capacitor, it is possible to prevent noise between the power supply and the ground. Furthermore, since there is no need to mount the capacitor outside the semiconductor device, the packaging density can be improved and the adverse effects of inductance due to the lead wire of the capacitor can be prevented. In addition, it is possible to eliminate the problem of reduced reliability such as thermal shock resistance of capacitors and semiconductor devices that occurred with conventional plastic packages with built-in capacitors, as well as the drawbacks such as manufacturing limitations of semiconductor devices, so it is inexpensive and reliable. An excellent semiconductor device with a built-in capacitor can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図〜第３図は従来のコンデンサ内蔵型半導体装置の
説明図で、第１図はセラミックパッケージの場合の断面
図、第２図はプラスチックパッケージの場合の製造途中
工程の平面図、第３図は樹脂封止後の第２図Ａ−Ａ’の
断面１１第４図〜第明の第１実施例の製造途中工程の平
面図、第５図は樹脂封止後の第４図Ｂ−Ｂ’線の断面図
、第６図は本発明の第２の実施例の製造途中工程の平面
図、第７図は樹脂封止後の第６図ｃ−ｃ’線の断面図、
第８図は本発明の第３の実施例の製造途中工程の平面図
である。 １ａ・・・・・・セラミックパッケージ、２ａ、２ｂ。 ２Ｃ１２ｄ・・・・・・半導体チップ搭載部、３ａ、３
ｂ。 ３Ｃ・・・・・・ＩＣチップ、４ａ、４ｂ、４ｃ・・・
・・・ホンディングワイヤ、５ａ・・・・・・コンデン
サ、６ａ・・・・・・コンデンサのリード、７ａ・・・
・・・キャラ７’、８ｂ。 ８Ｃ，３ｄ−・・・・・外部導出用リード、９ｂ、９Ｃ
。 ９ｄ・・・・・・リードフレーム、１０　ｂ、１０　ｃ
、１０ｃ’　１ｏｔ１・・・・・・半導体チップ搭載部
支持ＩＪ　−）゛、１１ｂ、ＩＩＣ・・・・・・段差、
１２ｂ、１２ｃ、１２ｄ・・・・・・外部導出用リード
（電源り−）”Ｌ１３ｂ。 １３ｃ、１３ｄ・・・・・・外部導出用リード（アース
１ノード）、１４ｂ、１４Ｃ，１４ｄ、１４ｄ’・・・
・・・チップ型コンデンサ、１５ｂ、１５ｃ・・・・・
・樹ｎ旨、１６ｃ、１６ｄ、ｔ６ａ’・・・・・・ナツ
プ型コ／デンサ搭載部、１７Ｃ，１７ｄ、１７ｄ’・・
・・・・スリット。 ｖ−１回 路３　訂 ／ 第４図 茅を回Figures 1 to 3 are explanatory diagrams of conventional semiconductor devices with built-in capacitors, in which Figure 1 is a cross-sectional view of a ceramic package, Figure 2 is a plan view of an intermediate manufacturing process in the case of a plastic package, and Figure 3 is an explanatory diagram of a conventional semiconductor device with a built-in capacitor. The figure is a cross section 11 of FIG. 2 A-A' after resin sealing. 6 is a plan view of the second embodiment of the present invention during the manufacturing process; FIG. 7 is a sectional view taken along the line c-c' in FIG. 6 after resin sealing;
FIG. 8 is a plan view of a manufacturing process in the third embodiment of the present invention. 1a...Ceramic package, 2a, 2b. 2C12d...Semiconductor chip mounting section, 3a, 3
b. 3C...IC chip, 4a, 4b, 4c...
...Honding wire, 5a...Capacitor, 6a...Capacitor lead, 7a...
...Character 7', 8b. 8C, 3d--Lead for external extraction, 9b, 9C
. 9d...Lead frame, 10b, 10c
, 10c' 1ot1... Semiconductor chip mounting part support IJ-)゛, 11b, IIC... Step,
12b, 12c, 12d...External lead-out lead (power supply)"L13b. 13c, 13d...External lead-out lead (earth 1 node), 14b, 14C, 14d, 14d' ...
...Chip type capacitor, 15b, 15c...
・Tree n, 16c, 16d, t6a'...Nup type co/denser mounting part, 17C, 17d, 17d'...
····slit. v-1 circuit 3 revision / Figure 4

Claims (5)

【特許請求の範囲】[Claims] （１）　半導体チップ搭載部、該半導体チップ搭載部に
接続された半導体チップ搭載部支持リード及び外部導出
用リードを有するリードフレームに半導体チップ並びに
コンデｙｔｅ搭載したコンデンサ内蔵型半導体装置にお
いて、１本の半導体チップ搭載部支持リードに隣接する
少なくとも１本の外部導出リードが半導体チップ搭載部
支持リードに接続され、半導体チップ搭載部又は少な（
とも１本の他の半導体チップ搭載部支持リードが該半導
体チップ搭載部支持リード又は半導体チップ搭載部に隣
接する少なくとも１本の外部導出用リードとチップ型コ
ンデンサを介して接続されていること全特徴とするコン
デソ廿内Ｒ削単道伏味餐−(1) In a capacitor built-in semiconductor device in which a semiconductor chip and a conductor are mounted on a lead frame having a semiconductor chip mounting part, a semiconductor chip mounting part support lead connected to the semiconductor chip mounting part, and an external lead lead, one At least one external lead adjacent to the semiconductor chip mounting part support lead is connected to the semiconductor chip mounting part support lead.
All features include the fact that one other semiconductor chip mounting part support lead is connected to the semiconductor chip mounting part support lead or at least one lead-out lead adjacent to the semiconductor chip mounting part via a chip type capacitor. Condeso Niuchi R Katando Fushimi Meal - （２）チップ型コンデンサの接続位置が半導体チップ搭
載部支持リードに設けたスリット、又は半導体チップ搭
載部支持リードと外部導出用リード間に設けたスリット
、外部導出用リードの内部リード部に設けたスリット、
又は半導体チップ搭載部と外部導出用リードの間に設け
たスリットの両端部である特許請求の範囲第（１）項記
載のコンデンサ内蔵型半導体装置。(2) The connection position of the chip capacitor is the slit provided in the semiconductor chip mounting part support lead, the slit provided between the semiconductor chip mounting part support lead and the external lead-out lead, or the slit provided in the internal lead part of the external lead-out lead. slit,
Or, the capacitor-embedded semiconductor device according to claim (1), which is both ends of a slit provided between the semiconductor chip mounting part and the external lead. （３）チップ型コンデンサの接続部分に前記コンデンサ
の搭載部が設けられている特許請求の範囲第（１１項又
は第（２）項記載のコンデンサ内蔵型半導体装置。(3) A semiconductor device with a built-in capacitor according to claim 11 or (2), wherein a mounting portion for the capacitor is provided at a connection portion of the chip capacitor. （４）１本の半導体テップ搭載部支持リードに隣接する
少なくとも１本の外部導出リードが半導体チップ搭載部
支持リードに接続され、半導体チップ搭載部又は少なく
とも１本の他の半導体チップ搭載部支持リードに隣接す
る少なくとも１本の外部導出リードと前記半導体チップ
搭載部又は半導体チップ搭載部支持リードとをチップ型
コンデンサで接続するためのスリット又は接続部を備え
たリードフレームを準備する工程と。 半導体チップを半導体チップ搭載部に固着する工程と、
少なくとも１個のチップ型コンデンサを前記スリット又
は接続部に固着する工程と、前記半導体チップの電極と
外部導出用リードとをワイヤボンディングする工程と、
樹脂封止する工程とを含むことを特徴とするコンデンサ
内蔵型半導体装置の製造方法。(4) At least one external lead adjacent to one semiconductor chip mounting part support lead is connected to the semiconductor chip mounting part support lead, and the semiconductor chip mounting part or at least one other semiconductor chip mounting part support lead is connected to the semiconductor chip mounting part support lead. preparing a lead frame having a slit or a connection portion for connecting at least one external lead adjacent to the semiconductor chip mounting portion or the semiconductor chip mounting portion support lead with a chip-type capacitor; a step of fixing the semiconductor chip to the semiconductor chip mounting part;
a step of fixing at least one chip-type capacitor to the slit or connection portion; and a step of wire-bonding the electrodes of the semiconductor chip and external leads;
1. A method for manufacturing a semiconductor device with a built-in capacitor, the method comprising the step of resin sealing. （５）リードフレームを準備する工程が、半導体チップ
搭載部又は半導体チップ搭載部支持リードに隣接する少
なくとも２本の外部導出用リードが前記半導体チップ搭
載部支持リード又は半導体チップ搭載部に接続され、少
なくとも一方の前記外部導出用リードの内部リードと半
導体チップ搭載部の間の適当な位置を分離しスリットを
設ける工程である特許請求の範囲第（４）項記載のコン
デンサ内蔵型半導体装置の製造方法。(5) In the step of preparing a lead frame, at least two external leads adjacent to the semiconductor chip mounting part or the semiconductor chip mounting part support lead are connected to the semiconductor chip mounting part support lead or the semiconductor chip mounting part, A method for manufacturing a capacitor-embedded semiconductor device according to claim (4), which comprises a step of separating and providing a slit at an appropriate position between the internal lead of at least one of the external leads and the semiconductor chip mounting portion. .
JP58143362A 1983-08-05 1983-08-05 Built-in capacitor type semiconductor device and manufacture thereof Pending JPS6034049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58143362A JPS6034049A (en) 1983-08-05 1983-08-05 Built-in capacitor type semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58143362A JPS6034049A (en) 1983-08-05 1983-08-05 Built-in capacitor type semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6034049A true JPS6034049A (en) 1985-02-21

Family

ID=15337016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58143362A Pending JPS6034049A (en) 1983-08-05 1983-08-05 Built-in capacitor type semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6034049A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61144655U (en) * 1985-02-28 1986-09-06
JPS6214748U (en) * 1985-07-11 1987-01-29
JPS6239907A (en) * 1985-08-15 1987-02-20 Matsushima Kogyo Co Ltd Piezo-oscillator
JPH0378248A (en) * 1989-08-22 1991-04-03 Seiko Instr Inc Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61144655U (en) * 1985-02-28 1986-09-06
JPS6214748U (en) * 1985-07-11 1987-01-29
JPS6239907A (en) * 1985-08-15 1987-02-20 Matsushima Kogyo Co Ltd Piezo-oscillator
JPH0378248A (en) * 1989-08-22 1991-04-03 Seiko Instr Inc Semiconductor device

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