JPS5972234A - Phase-locked oscillation circuit - Google Patents
Phase-locked oscillation circuitInfo
- Publication number
- JPS5972234A JPS5972234A JP57181275A JP18127582A JPS5972234A JP S5972234 A JPS5972234 A JP S5972234A JP 57181275 A JP57181275 A JP 57181275A JP 18127582 A JP18127582 A JP 18127582A JP S5972234 A JPS5972234 A JP S5972234A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- oscillator
- phase
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 title claims description 25
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、基準信号に位相同期した信号を発生する位相
同期発振回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked oscillator circuit that generates a signal that is phase-locked to a reference signal.
従来のこの種発振回路は、例えば第１図に示すように、
電圧制御発振器４の出力信号と入力端子１から入力する
基準信号とを位相比較器２に入力させ、位相比較器２で
内入力信号の位相比較を行ない、位相差に対応する出力
信号をループフィルタ３を通して電圧制御発振器４の制
御入力に供給する構成とさ扛ている。電圧制御発振器４
け入力電圧に応じて発振周波数が上昇または下降するか
ら、該発振器の出力信号は基準信号との位相差が少なく
なるように制御さ扛る。従って、入力基準信号に位相同
期した発振出力信号が出力端子５から出力さ扛る。A conventional oscillation circuit of this kind, for example, as shown in FIG.
The output signal of the voltage controlled oscillator 4 and the reference signal input from the input terminal 1 are input to the phase comparator 2, the phase comparator 2 compares the phases of the internal input signals, and the output signal corresponding to the phase difference is passed through the loop filter. 3 to the control input of the voltage controlled oscillator 4. Voltage controlled oscillator 4
Since the oscillation frequency increases or decreases depending on the input voltage, the output signal of the oscillator is controlled so that the phase difference with the reference signal is reduced. Therefore, an oscillation output signal whose phase is synchronized with the input reference signal is output from the output terminal 5.
上述の従来回路は、電圧制御発振器の自走周波数の長期
変動により自走周波数と基準周波数との周波数差が変動
することに基因して定常位相誤差を生じるという欠点が
ある。また、電圧制御発振器自体の位相ジッタ（発振器
の短期安定度に起因する位相変動）により出力信号にも
位相ジッタを生じるが、電圧制御発振器の位相ジンクは
一般に固定発振器のそれに比して犬であるため出力信萼
の位相ジッタが大となる欠点がある。The above-mentioned conventional circuit has the disadvantage that a steady phase error occurs due to a change in the frequency difference between the free-running frequency and the reference frequency due to long-term fluctuations in the free-running frequency of the voltage controlled oscillator. In addition, the phase jitter of the voltage controlled oscillator itself (phase fluctuations caused by the short-term stability of the oscillator) causes phase jitter in the output signal, but the phase jitter of the voltage controlled oscillator is generally smaller than that of a fixed oscillator. Therefore, there is a drawback that the phase jitter of the output signal is large.
本発明の目的は、上述の従来の欠点を解決し、短期的位
相ジッタおよび長期的位相誤差の少ない安定した位相同
期回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and to provide a stable phase-locked circuit with less short-term phase jitter and less long-term phase error.
本発明は、高安定な固定周波数発振器と、比較的低周波
の周波数可変発振器を用いて、上記両発振器の出力を合
成することにニジ所要周波数の安定した出力信号を得る
ものである。The present invention uses a highly stable fixed frequency oscillator and a relatively low frequency variable frequency oscillator, and obtains a stable output signal at a desired frequency by combining the outputs of both oscillators.
本発明の位相同期発振回路は、入力基準信号と後記周波
数変換回路の出力信号との位相比較を行なう位相比較器
と、該位相比較器の出力が小となるように第１の発振器
の発振周波数を制御する発振制御手段と、該発振制御手
段の出力にニジ発振周波数が制御さｎる前記第１の発振
器と、固定周波数を発振する第２の発振器と、前記第１
および第２の発振器の出力周波数の和または差の周波数
の信号を出力する周波数変換回路とを備えて、該周波数
変換回路の出力を前記位相比較器に入力させることを特
徴とする。The phase synchronized oscillation circuit of the present invention includes a phase comparator that performs a phase comparison between an input reference signal and an output signal of a frequency conversion circuit described below, and an oscillation frequency of a first oscillator so that the output of the phase comparator is small. oscillation control means for controlling the oscillation control means, the first oscillator whose rainbow oscillation frequency is controlled by the output of the oscillation control means, the second oscillator that oscillates at a fixed frequency, and the first oscillator.
and a frequency conversion circuit that outputs a signal having a frequency of the sum or difference of the output frequencies of the second oscillator, and the output of the frequency conversion circuit is input to the phase comparator.
なお上記発振制御回路、第１の発振器９周波数変換回路
等は各種の変形が可能であり、その一部または全部をデ
ジタル回路で構成することもできる。Note that the oscillation control circuit, the first oscillator 9 frequency conversion circuit, etc. can be modified in various ways, and part or all of them can be constructed from digital circuits.
次に、本発明について、図面を参照して詳細に説明する
。Next, the present invention will be explained in detail with reference to the drawings.
第２図は、本発明の第１の実施例を示すブロック図であ
る。本実施例においては、従来の電圧制御発振器４に代
えて、比較的低周波の電圧制御発振器６で構成さ扛る第
１の発振器と、固定周波数発振器８で構成する第２の発
振器と、上記両発振器の出力信号を乗算して両信号の和
および差の周波数の信号を出力するミキサ７および帯域
通過フィルタ９とから構成さ扛る周波数変換回路とを用
いる（図中点線で囲ま扛た部分である）。位相比較器２
．ループフィルタ３は前述の従来例と同様である。FIG. 2 is a block diagram showing a first embodiment of the present invention. In this embodiment, instead of the conventional voltage controlled oscillator 4, a first oscillator consisting of a relatively low frequency voltage controlled oscillator 6, a second oscillator consisting of a fixed frequency oscillator 8, and the above-mentioned A frequency conversion circuit consisting of a mixer 7 that multiplies the output signals of both oscillators and outputs signals of the sum and difference frequencies of both signals and a band pass filter 9 is used (the part surrounded by the dotted line in the figure) is used. ). Phase comparator 2
．． The loop filter 3 is similar to the conventional example described above.
本実施例では、固定周波数発振器８の発振周波数をｆ。In this embodiment, the oscillation frequency of the fixed frequency oscillator 8 is f.
、安定度を８゜とじ、電圧制御発振器６の発振周波数を
ｆ、安定度を８とし、基準信号の周波数をｆｃとすると
、
になるように設定される。例えば、ｆｃ＝４０メガヘル
ツに対して、ｆｏ＝３９．９９９メガヘルツ、ｆ＝１キ
ロヘルツとし、固定周波発振器８０安定度８゜は１０−
１０のものを使用する。電圧制御発振器６の安定度８は
１０−７程度である。電圧制御発振器６はループフィル
タ３の出力電圧によって周波数および位相が制御された
周波数ｆ（１キロヘルツ）の信号を出力し、ミキサ７で
固定周波数発振器８の出力する周波数ｆｏ（３９，９９
９メガヘルツ）の信号と乗算さ扛る。ミキサ７の出力に
けｆ０＋ｆ（４０メガヘルツ）の（Ｋ号トｆ。−ｆ（３
９，９９８メガヘルツ）の信号が出力さｎる。帯域通過
フィルり９Ｖｉ上記２信号のうち周波数ｆ、＋ｆ（４０
メガヘルツ）を通過させる。この場合、帯域通過フィル
タ９の出力信号の周波数安定度ｓｔは、ｆｏ＞＞ｒであ
るから、ｓｔ＝ （ｆｏ ｓｏ＋ ｆｓ）／ （ｆｏ＋
ｆ） ＊ ８ｏ −＜２）となシ、はぼ固定周波数発振
器８と同じ安定度を得ることができる。すなわち、高安
定度の位相同期信号を得ることができる効果がある。, the stability is set at 8 degrees, the oscillation frequency of the voltage controlled oscillator 6 is f, the stability is 8, and the frequency of the reference signal is fc. For example, for fc = 40 MHz, fo = 39.999 MHz, f = 1 kHz, and the fixed frequency oscillator 80 stability of 8° is 10-
Use 10 items. The stability 8 of the voltage controlled oscillator 6 is about 10-7. The voltage controlled oscillator 6 outputs a signal with a frequency f (1 kilohertz) whose frequency and phase are controlled by the output voltage of the loop filter 3, and the mixer 7 outputs a signal with a frequency fo (39,99
9 MHz) signal. The output of mixer 7 is f0 + f (40 MHz) (K to f. - f (3
A signal of 9,998 MHz) is output. Bandpass filter 9Vi Frequencies f, +f (40
MHz). In this case, the frequency stability st of the output signal of the bandpass filter 9 is fo>>r, so st= (fo so+ fs)/(fo+
f) *8o -<2), it is possible to obtain the same stability as the fixed frequency oscillator 8. That is, there is an effect that a highly stable phase synchronization signal can be obtained.
第３図は、本発明の第２の実施例を示すブロック図であ
り、第２図の電圧制御発振器６に代えてデジタル回路に
よる正弦波形信号発生器ｉｉを用い、ループフィルタ３
に代えて演算回路１０を用いたものである。正弦波形信
号発生器１１は第１の発振器であり、入力さ′ｎた周波
数ω、初期位相ψに従って、５ｉｎ（ωを十ψ）で表わ
される正弦波信号を発生するデジタル回路である。演算
回路１０は、例えば第４図に点線で囲ま：ｎたように構
成さ扛る。すなわち、位相誤差検出器１５．９０°移相
器１２．位相比較器１３９周波数誤差検出器１４、制御
回路１６から構成さｎている。９０°移相器１２によっ
て入力基準信号の位相を９０°移相させて、位相比較器
１３で帯域通過フィルタ９の出力信号との位相比較を行
ない、位相比較器１３の出力信号により周波数誤差検出
器１４で周波数誤差を検出する。位相誤差検出器１５は
、位相比較器２の出力信号に、Ｊ：り位相誤差を検出す
る。制御回路１６は、上記周波数誤差および位相誤差に
基づいて補正すべき位相および周波数を導出して正弦波
形信号発生器１１に制御信号を出力する。FIG. 3 is a block diagram showing a second embodiment of the present invention, in which a sine wave signal generator ii based on a digital circuit is used in place of the voltage controlled oscillator 6 in FIG. 2, and a loop filter 3 is used.
In this example, an arithmetic circuit 10 is used instead. The sine wave signal generator 11 is a first oscillator, and is a digital circuit that generates a sine wave signal expressed by 5 inches (ω = 10 ψ) according to the input frequency ω and initial phase ψ. The arithmetic circuit 10 is configured, for example, as shown in the dotted line in FIG. That is, phase error detector 15.90° phase shifter 12. It consists of a phase comparator 139, a frequency error detector 14, and a control circuit 16. The 90° phase shifter 12 shifts the phase of the input reference signal by 90°, the phase comparator 13 compares the phase with the output signal of the bandpass filter 9, and the output signal of the phase comparator 13 detects a frequency error. A frequency error is detected by a device 14. The phase error detector 15 detects a phase error of J in the output signal of the phase comparator 2. The control circuit 16 derives the phase and frequency to be corrected based on the frequency error and phase error, and outputs a control signal to the sine wave signal generator 11.
すなわち、本実施例では９０°移相器１２９位相比較器
１３１周波数誤差検出器１４．位相誤差検出器１５．制
御回路１６からなる演算回路ｌＯが発振制御手段を構成
している。本回路はデジタル回路に工り小型安価に提供
できる。That is, in this embodiment, a 90° phase shifter 129, a phase comparator 131, a frequency error detector 14. Phase error detector 15. An arithmetic circuit 10 consisting of a control circuit 16 constitutes an oscillation control means. This circuit is manufactured into a digital circuit and can be provided in a small size and at low cost.
第５図（ａ）および（ｂ）は、本発明の第３の実施例お
よびその変形を示すブロック図であり、それぞれ第２図
および第３図のミキサ７と帯域通過フィルタ９をイメー
ジリジェクションミキサ１７によって置き替えた周波数
変換回路を使用している。イメージリジェクションミキ
サ１７ｉ１ｔ、２つの入力信号の乗算によって両者の周
波数の和および差の関係をもつ２つの信号を生成し、そ
れらの信号のベクトル合成によって任意の一方の信号を
除去した信号として出力するミキサである。従って、第
２図、第３図のように帯域通過フィルタが必要テないか
ら小型化に有利である。FIGS. 5(a) and 5(b) are block diagrams showing a third embodiment of the present invention and a modification thereof, in which the mixer 7 and bandpass filter 9 of FIGS. 2 and 3 are replaced by image rejection. A frequency conversion circuit replaced by mixer 17 is used. The image rejection mixer 17i1t multiplies two input signals to generate two signals having a relation of the sum and difference of their frequencies, and outputs a signal from which any one signal is removed by vector synthesis of these signals. It's a mixer. Therefore, there is no need for a bandpass filter as shown in FIGS. 2 and 3, which is advantageous for miniaturization.
以上のように、本発明においては、本回路の出力信号と
入力基準信号との位相差によって比較的低周波の第１の
発振器の発振周波数を制御し、該第１の発振器の出力信
号を固定周波数を発振する第２の発振器の出力信号によ
って周波数変換することに工っで位相同期信号を出力す
るように構成したから、第１の発振器の比較的低い安定
度の悪影響が極度に軽減さ扛た高安定度の位相同期発振
出力を得ることができる効果がある。また、本回路の一
部はデジタル回路によって構成することができる力・ら
ＬＳＩ化が容易である。As described above, in the present invention, the oscillation frequency of the relatively low-frequency first oscillator is controlled by the phase difference between the output signal of the present circuit and the input reference signal, and the output signal of the first oscillator is fixed. Since the configuration is configured to output a phase synchronized signal by converting the frequency using the output signal of the second oscillator that oscillates the frequency, the adverse effects of the relatively low stability of the first oscillator are extremely reduced. This has the advantage that a highly stable phase-locked oscillation output can be obtained. In addition, a part of this circuit can be constructed by a digital circuit and can be easily integrated into an LSI.
【図面の簡単な説明】
第１図は従来の位相同期発振回路の一例を示すブロック
図、第２図は本発明の第１の実施例を示すブロック図、
第３図は本発明の第２の実施例を示すブロック図、第４
図は上記第２の実施例の演算回路の構成例を示すブロッ
ク図、第５図（ａ） 、 （ｂ）は本発明の第３の実施
例およびその変形例を示すブロック図である。
図において、■・・・入力端子、２・・・位相比較器、
３・・・ループフィルタ、４・・・電圧制御発振器、訃
・・出力端子、６・・・電圧制御発振器、７・・・ミキ
サ＼８・“・固定周波数発振器、９・・・帯域通過フィ
ルタ、１０・・・演算回路、１１・・・正弦波形信号発
生器、１２・・・９０゜移相器、１３・・・位相比較器
、１４・・・周波数誤差検出器、１５・・・位相誤差検
出器、１６・・・制御回路、１７・・・イメージリジェ
クションミキサ。
出願人 日本電信電話公社
代理人 弁理士性 １）俊 宗
′２Ｓ１図
第２図
ニｊＴ ３図
三−１”１４０[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing an example of a conventional phase-locked oscillation circuit, FIG. 2 is a block diagram showing a first embodiment of the present invention,
FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIG.
The figure is a block diagram showing an example of the configuration of the arithmetic circuit of the second embodiment, and FIGS. 5(a) and 5(b) are block diagrams showing the third embodiment of the present invention and its modifications. In the figure, ■...input terminal, 2...phase comparator,
3... Loop filter, 4... Voltage controlled oscillator, 2... Output terminal, 6... Voltage controlled oscillator, 7... Mixer \8, fixed frequency oscillator, 9... Bandpass filter , 10... Arithmetic circuit, 11... Sine waveform signal generator, 12... 90° phase shifter, 13... Phase comparator, 14... Frequency error detector, 15... Phase Error detector, 16...Control circuit, 17...Image rejection mixer. Applicant: Nippon Telegraph and Telephone Public Corporation Agent Patent attorney 1) Toshi So '2S1 Figure 2 Figure 2jT 3 Figure 3-1"140
Claims (1)
の位相比較を行なう位相比較器と、該位相比較器の出力
が小となるように第１の発振器の発振周波数を制御する
発振制御手段と、該発振制御手段の出力により発振周波
数が制御される前記第１の発振器と、固定周波数を発振
する第２の発振器と、前記第１および第２の発振器の出
力周波数の和または差の周波数の信号を出力する周波数
変換回路とを備えて、該周波数変換回路の出力を前記位
相比較器に人力させることを特徴とする位相同期発振器
。 （２、特許請求の範囲第１項記載の位相同期発振回路に
おいて、前記発振制御手段はループフィルタであり、前
記第１の発振器は電圧制御発振器であυ、前記周波数変
換回路は前記電圧制御発振器の出力と前記第２の発振器
出力とを入力するミキサと、該ミキサ出力の所要帯域を
通過させる帯域通過フィルタとから構成さｎたことを％
徴とするもの。 （３）特許請求の範囲第１項記載の位相同期発振器にお
いて、前記第１の発振器は与えらｎ７’ｃ発振周波数お
よび初期位相によって正弦波形を合成する信号発生器で
構成し、前記発振制御手段は、入力基準信号と前記族波
数変換手段の出力信号との周波数誤差を検出する周波数
誤差検出器を含み周波数誤差および位相誤差をなくすよ
うに発振周波数および初期位相を計算する演算回路によ
って構成さｎｆｃことを特徴とするもの。 （４）％許請求の範囲第１項または第３項記載の位相同
期発振回路において、前記周波数変換回路はイメージ信
号を除去出力するイメージリジェクションミキサによっ
て構成さｔ′Ｌ′ｆｃことを特徴とするもの。[Scope of Claims] (1) A phase comparator that performs a phase comparison between an input reference signal and an output signal of a frequency conversion circuit described below, and an oscillation frequency of a first oscillator so that the output of the phase comparator is small. oscillation control means for controlling, the first oscillator whose oscillation frequency is controlled by the output of the oscillation control means, a second oscillator that oscillates at a fixed frequency, and output frequencies of the first and second oscillators. A phase synchronized oscillator comprising: a frequency conversion circuit that outputs a signal having a sum or difference frequency, and the output of the frequency conversion circuit is manually input to the phase comparator. (2. In the phase-locked oscillator circuit according to claim 1, the oscillation control means is a loop filter, the first oscillator is a voltage-controlled oscillator, and the frequency conversion circuit is the voltage-controlled oscillator. and a bandpass filter that passes a required band of the mixer output.
something that is a sign. (3) In the phase-locked oscillator according to claim 1, the first oscillator is constituted by a signal generator that synthesizes a sine waveform based on a given n7'c oscillation frequency and an initial phase, and the oscillation control means The NFC includes a frequency error detector that detects a frequency error between the input reference signal and the output signal of the family wave number conversion means, and includes an arithmetic circuit that calculates the oscillation frequency and initial phase so as to eliminate the frequency error and phase error. something that is characterized by (4) In the phase-locked oscillator circuit according to claim 1 or 3, the frequency conversion circuit is constituted by an image rejection mixer that removes and outputs an image signal t'L'fc. Something to do.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57181275A JPS5972234A (en) | 1982-10-18 | 1982-10-18 | Phase-locked oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57181275A JPS5972234A (en) | 1982-10-18 | 1982-10-18 | Phase-locked oscillation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5972234A true JPS5972234A (en) | 1984-04-24 |
Family
ID=16097842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57181275A Pending JPS5972234A (en) | 1982-10-18 | 1982-10-18 | Phase-locked oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5972234A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02200009A (en) * | 1989-01-30 | 1990-08-08 | Matsushita Electric Ind Co Ltd | Phase synchronizing device |
| EP0515074A2 (en) * | 1991-05-21 | 1992-11-25 | National Semiconductor Corporation | Frequency controlled oscillator for high frequency phase-locked loop |
-
1982
- 1982-10-18 JP JP57181275A patent/JPS5972234A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02200009A (en) * | 1989-01-30 | 1990-08-08 | Matsushita Electric Ind Co Ltd | Phase synchronizing device |
| EP0515074A2 (en) * | 1991-05-21 | 1992-11-25 | National Semiconductor Corporation | Frequency controlled oscillator for high frequency phase-locked loop |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7417477B2 (en) | PLL circuit | |
| TWI633760B (en) | Signal transmitter | |
| ATE506751T1 (en) | PRESET CIRCUIT FOR A VOLTAGE CONTROLLED OSCILLATOR | |
| JPS5972234A (en) | Phase-locked oscillation circuit | |
| JP3712141B2 (en) | Phase-locked loop device | |
| JPS6059822A (en) | Frequency converting circuit | |
| JP2000004121A (en) | Oscillation modulating circuit | |
| JP3839766B2 (en) | IF demodulation module | |
| JP3248453B2 (en) | Oscillator | |
| JP3147487B2 (en) | Synchronous signal generator | |
| JPS59153333A (en) | Phase and frequency variable oscillator | |
| JPS5918757Y2 (en) | Frequency synthesizer using PLL circuit | |
| JP2001527313A (en) | Method and apparatus for reducing load pull in a phase locked loop frequency source | |
| JP5265486B2 (en) | PLL circuit | |
| JPH06326603A (en) | Pll frequency synthesizer circuit | |
| JPH02233019A (en) | Frequency synthesizer | |
| JPH10215168A (en) | Pll oscillator using vcxo | |
| JPS6076819A (en) | Radio receiver free from cross spurious | |
| JPH02206916A (en) | Clock switching type phase locked loop oscillating circuit for phase locking | |
| JPS58106918A (en) | Frequency synthesizer | |
| JPS5829010B2 (en) | frequency synthesizer | |
| JPS60100826A (en) | Local oscillator | |
| JPS61167223A (en) | Phase locked loop | |
| JPH06224753A (en) | Transmitter | |
| JPH0998084A (en) | Phase synchronizing oscillation circuit |