JPS5950617A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPS5950617A JPS5950617A JP57161464A JP16146482A JPS5950617A JP S5950617 A JPS5950617 A JP S5950617A JP 57161464 A JP57161464 A JP 57161464A JP 16146482 A JP16146482 A JP 16146482A JP S5950617 A JPS5950617 A JP S5950617A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- mixer
- output
- vco
- oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims abstract description 15
- 238000001514 detection method Methods 0.000 abstract description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000035559 beat frequency Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はVFO(Variable Frequ@n
cy 0sci=11ator ) f:周波数調整源
とする、多バンドPLL(Phase Locked
Loop )制御のVCO(VoltageContr
olled 0scillator )と、プロダクト
検波用のBFO(Beat Frequency Om
aillator )周波数を供給する回路構成を提供
するにある。[Detailed Description of the Invention] This invention is a VFO (Variable Frequency
cy0sci=11ator) f: Multi-band PLL (Phase Locked
Loop) controlled VCO (Voltage Control)
olled 0scillator) and BFO (Beat Frequency Om) for product detection.
(ailer) provides a circuit configuration for supplying the frequency.
本発明について述べる前に従来回路について説明する。Before describing the present invention, a conventional circuit will be explained.
第1図は従来回路例であって、vCO→第1のミクサリ
プ四グラマプル分周器→位相比較器→vCOのループが
PLL系を構成し、基準発振器によシ安定化されている
。この回路の周波数を大きく変えるのにはプログラマブ
ル分周器の分周比を変えるが、微細に調整するのにはV
FOによっている。VFOは自励発振器または別のPL
L制御による周波数連続可変発振器であシ、通常I M
Hzの可変範囲を取る。このVFOは水晶発振器(この
場合はBFOである)と第2のミクサで和/差の周波数
を作シ、所要周波数帯を通すBPF (Band Pa
5sFilt@r )で不要周波数を除去して、所要周
波数を第1のミクサに注入する。これによ、6、vco
はVFOの変化に従ってI MHz幅の変化を生ずるこ
とになる。FIG. 1 shows an example of a conventional circuit, in which a loop of vCO→first mixerp quadrature frequency divider→phase comparator→vCO constitutes a PLL system, which is stabilized by a reference oscillator. To greatly change the frequency of this circuit, change the division ratio of the programmable frequency divider, but to finely adjust the frequency,
By FO. VFO is a free oscillator or another PL
Continuously variable frequency oscillator with L control, usually IM
Takes a variable range of Hz. This VFO generates a sum/difference frequency using a crystal oscillator (BFO in this case) and a second mixer, and then generates a BPF (Band Pa) that passes the required frequency band.
5sFilt@r ) to remove unnecessary frequencies and inject the desired frequency into the first mixer. This is 6, vco
will result in a change in I MHz width as the VFO changes.
周波数)を、第3のミクサで第2のミクサの出力と混合
して和/差周波数を作シ、所要周波数帯のBPF’ i
通して第1のミクサに加えることにより、プログラマブ
ル分周器の作用を補強拡張して、出力1には受信機の第
1局部発振として必要な広周波数帯域のPLL制御のV
CO発振周波数が得られるものである。出力2はプロダ
クト検波にBFOとして注入する。frequency) is mixed with the output of the second mixer in a third mixer to create the sum/difference frequency, and the BPF' i of the desired frequency band is
By adding it to the first mixer through the programmable frequency divider, the effect of the programmable frequency divider is reinforced and extended, and output 1 has a wide frequency band PLL-controlled V required as the first local oscillation of the receiver.
The CO oscillation frequency can be obtained. Output 2 is injected as BFO to product detection.
ところで、第1図の回路ではVFOから出力1を作るま
でに3個のミクサを必要とする(第2のミクサは使わな
い周波帯もある)。さらにこの回路では出力1は直接に
はVCOの発振によっているので、ミクサにおける不要
周波数の発生は関係ないように見えるが、−80とか一
100dB程度のスプリアスを問題にする場合には、そ
の原因を作るミクサ段は極力減らすことが望ましいこと
は申すまでもない。By the way, the circuit shown in FIG. 1 requires three mixers to produce output 1 from the VFO (there are some frequency bands where the second mixer is not used). Furthermore, in this circuit, output 1 is directly caused by the oscillation of the VCO, so the generation of unnecessary frequencies in the mixer seems to be unrelated, but if you are concerned about spurious signals of -80 or -100 dB, you need to investigate the cause. Needless to say, it is desirable to reduce the number of mixer stages to be created as much as possible.
本発明はPLT、制御のVCOと、VCO出力を周波数
変換してプログラマブル分周器に供給する紀1のミクサ
M、と、周波数調整を行うVF’Oと固定周波数のノ4
ラメータ発振器出力とを混合する第2のミクサM2と、
第2のミクサの出力を第1のミクサに供給する回路に設
けたBPFと、前記パラメータ発振器の出力を直接また
はPLL回路の基準周波数発振器出力へとを混合する第
3のミクサM3を通した周波数を通信機の後段部ミクサ
またはプロダクト検波器に供給する回路とよ構成シ、前
記プログラマブル分周器の出力と基準発振器周波数また
はこれを分周した周波数fRとを位相比較しVCOに制
御電圧を供給する位相比較器とよシ成ることを特徴とす
るPLL回路である。The present invention consists of a PLT, a VCO for control, a mixer M that converts the frequency of the VCO output and supplies it to a programmable frequency divider, a VF'O that performs frequency adjustment, and a fixed frequency node 4.
a second mixer M2 for mixing the output of the ramometer oscillator;
A BPF provided in a circuit that supplies the output of the second mixer to the first mixer, and a third mixer M3 that mixes the output of the parameter oscillator directly or into the reference frequency oscillator output of the PLL circuit. The circuit supplies the signal to the mixer or product detector in the latter part of the communication device, and the circuit compares the phase of the output of the programmable frequency divider with the reference oscillator frequency or the frequency fR obtained by dividing the reference oscillator frequency, and supplies a control voltage to the VCO. This is a PLL circuit characterized by consisting of a phase comparator.
これを第2図の回路例について説明すると、PLL発振
回路を構成する部分については特に相違は無いが、周波
数調整用のVFO出力と固定周波数のノfラメータ発振
器出力とをミクサM2で混合して、和/差周波数のうち
必要な周波数のみをBPFを通してPT、L回路内のミ
クサM1に注入して、Vco周波数を制御している。従
ってVFOから出力1までの間にはM2とM、の2個の
ミクサが介在するのみであって、これを第1図の回路の
3個に比らべて1個を減じており、その分だけ不要周波
数の混入を減らすことが出来る。その代シ出力2に対し
てはパラメータ発振器の周波数が直接に使用できる場合
は良いが、基準周波数とパラメータ発振器周波数とをミ
クサM3で混合した周波数を用いる場合には、ミクサが
1個増加することになる。しかし、出力2は受信機の中
間周波段の後段ミクサあるいはプロダクト検波用の注入
周波数であって、中間周波の信号自体が狭帯域のフィル
タを通過して来ているので、注入周波数に若干の不要周
波数成分が含まれていても問題とはならないものである
。To explain this using the circuit example shown in Figure 2, there is no particular difference in the parts that make up the PLL oscillation circuit, but the VFO output for frequency adjustment and the output of the fixed frequency nof parameter oscillator are mixed by mixer M2. , only the necessary frequencies among the sum/difference frequencies are injected into the mixer M1 in the PT and L circuits through the BPF to control the Vco frequency. Therefore, there are only two mixers, M2 and M, between the VFO and output 1, which is one less than the three mixers in the circuit shown in Figure 1. This can reduce the amount of unnecessary frequencies mixed in. Alternatively, it is fine if the frequency of the parameter oscillator can be used directly for output 2, but if a frequency obtained by mixing the reference frequency and the parameter oscillator frequency with mixer M3 is used, the number of mixers will be increased by one. become. However, output 2 is the injection frequency for the mixer after the intermediate frequency stage of the receiver or for product detection, and since the intermediate frequency signal itself has passed through a narrow band filter, there is some unnecessary noise in the injection frequency. Even if a frequency component is included, it is not a problem.
まだ周波数が一定であるから必要ならばフィルタの適用
も容易である。Since the frequency is still constant, it is easy to apply a filter if necessary.
バンド設定のような大きい周波数変化はプログラマブル
分周器の分周比を変えて行うと前に述べたが、vCOの
発振周波数が極めて高くなると、分周器の最高動作周波
数の限界による制限を受ける。I mentioned earlier that large frequency changes such as band settings are made by changing the division ratio of the programmable frequency divider, but when the oscillation frequency of vCO becomes extremely high, it is limited by the limit of the maximum operating frequency of the frequency divider. .
またそれ以下であっても、分周比が犬きくなるほどPL
Lのループゲインが低下して、制御作用が低下する問題
があるので、広帯域の用途に対しては分周比は数倍程度
の変化範囲におさえ、ミクサM1の注入周波数を変える
のが良い。そのため第2図では複数の/4’ラメータ発
振周波数を使用している。プログラマブル分周器の分周
比とパラメータ発振周波数の両方の組合わせにより、広
帯域のPLL発振を良い状態で行わせることが可能と庁
る。Even if it is less than that, the sharper the division ratio, the higher the PL.
Since there is a problem that the loop gain of L is lowered and the control effect is lowered, for wideband applications, it is better to keep the frequency dividing ratio within a range of several times and change the injection frequency of the mixer M1. Therefore, in FIG. 2, a plurality of /4' rameter oscillation frequencies are used. It is believed that by combining both the frequency division ratio of the programmable frequency divider and the parameter oscillation frequency, it is possible to perform broadband PLL oscillation in good condition.
vCOも1個では安定にカバー出来ない場合は複数のv
COを用意して、安定動作範囲を使用することは通常行
われている通シである。If the vCO cannot be stably covered by one, use multiple vCOs.
It is common practice to provide a CO and use a stable operating range.
次に本発明回路を広帯域受信機に適用した周波数構成例
を第3図について説明する。Next, an example of a frequency configuration in which the circuit of the present invention is applied to a wideband receiver will be explained with reference to FIG.
受信周波数範囲は短波帯以下全域00〜30 MHzで
あシ、中間周波数は受信周波数を避けて47MHzに選
んである。従って受信ミクサへの注入局部周波数は47
〜77 MHzとiる。PLL発振回路の周波数はI
MHzステップで変化するのが都合が良いので位相比較
器はI MHzの基準周波数で動作する。The receiving frequency range is 00 to 30 MHz throughout the short wave band and below, and the intermediate frequency is selected to be 47 MHz, avoiding the receiving frequency. Therefore, the local frequency injected into the receive mixer is 47
~77 MHz. The frequency of the PLL oscillation circuit is I
The phase comparator operates with a reference frequency of I MHz, as it is convenient to vary in MHz steps.
プログラマブル分周器の最高入力周波数は最新のCMo
5ICの場合で30 MFrzは不可能なので20MH
z以下と設定する。VCOは47〜77 MHzを1段
でカバーするのは安定度に問題があるので、47〜62
(VCO−1)と62〜77 MHz VCO−2の
2段に分けて切替えている。The maximum input frequency of the programmable frequency divider is the latest CMo
In the case of 5IC, 30 MFrz is impossible, so 20MH
Set it to be less than or equal to z. VCO covers 47 to 77 MHz with one stage because there is a stability problem, so 47 to 62 MHz is required.
(VCO-1) and 62-77 MHz VCO-2.
VCO−1に対応して、パラメータ発振器は47MHz
を発振し、ミクサM′2でVFOの6〜5MH7と混合
して、41〜42 MFrzをBPF’を通してミクサ
M/。Corresponding to VCO-1, the parameter oscillator is 47MHz
is oscillated, mixed with 6 to 5 MH7 of VFO in mixer M'2, and 41 to 42 MFrz is passed through BPF' to mixer M/.
に注入し、vco −1の47〜62 MHzと混合す
ると、6〜20 MHzのプログラマブル分周器入力周
波数が得られる。これをI MT(zに分周するための
分周比はN=6〜20である。When injected and mixed with 47-62 MHz of vco -1, a programmable divider input frequency of 6-20 MHz is obtained. The frequency division ratio for dividing this into IMT(z) is N=6 to 20.
次にVCO−2に対応して、パラメータ発振器は62
MHzを発振し、ミクサM′2でVFOの6〜5MF(
zと混合して、56〜57■hをBPFを通してミクサ
M/1に注入し、VCO−1の62〜77M′F(zと
混合すると、6〜20 MHzのプログラマブル分周器
入力周波数が得られる。これをI MHzに分周するた
めの分周比はN−d〜20である。Next, corresponding to VCO-2, the parameter oscillator is 62
oscillates at MHz, mixer M'2 generates 6 to 5 MF of VFO (
Mixed with z, 56~57■h is injected through BPF into mixer M/1, and 62~77M'F of VCO-1 (mixed with z gives a programmable divider input frequency of 6~20 MHz. The frequency division ratio for dividing this into I MHz is N-d~20.
上記面状態において分周器入力は共に6〜20MHzで
あシ分周比もN=5〜20と同一であるからプログラマ
ブル分周器の設定はVCO−1とVCO−2とで同じこ
とを繰シ返せばよい。逆にいえば、分周器の設定が簡略
化されるようにパラメータ発振器の周波数が設定されて
いるのである。このようにvCOとBPFとパラメータ
発振器は緊密な相互関係で結ばれているので、切替は連
動で行うのが便利である。In the above state, the frequency divider inputs are both 6 to 20 MHz and the frequency division ratio is the same as N = 5 to 20, so the programmable frequency divider settings are the same for VCO-1 and VCO-2. All you have to do is return it. In other words, the frequency of the parameter oscillator is set so that the setting of the frequency divider is simplified. Since the vCO, BPF, and parameter oscillator are thus closely interconnected, it is convenient to switch them in conjunction.
プロダクト検波器の注入周波数は、パラメータ発振器が
47 M[(zのときは、そのまま利用するが、パラメ
ータ発振器が62 MHzのときはミクサM3で15
MHzと混合して47 MHzを得て、必要ならばフィ
ルタを通して注入する。ミクサM3へ注入の15 MF
(zは基準発振器を15 MHzとして利用している。The injection frequency of the product detector is 47 M[(z) when the parameter oscillator is 62 MHz, but when the parameter oscillator is 62 MHz, it is 15 MHz with mixer M3.
MHz to obtain 47 MHz and inject through a filter if necessary. 15 MF injected into mixer M3
(z uses a reference oscillator of 15 MHz.
従って、PLL回路のI MHz基準周波数は15 M
Hz Th 15分周することによって得ている。Therefore, the I MHz reference frequency of the PLL circuit is 15 M
It is obtained by dividing the frequency by 15 Hz Th.
以上の第3図における周波数関係は説明を簡略してダブ
ルコンバージ璽ンとすることが多いが、出力20周波数
も適宜変換して供給すればよいのであって、本特許を構
成する回路部分には何等の変更も必要としないのである
から、本特許の構成と特徴については以上の説明で十分
に理解し得るものである。The frequency relationship in FIG. 3 above is often simplified and described as a double convergence code, but the output 20 frequencies may also be converted and supplied as appropriate, and the circuit portion that constitutes this patent is Since no changes are required, the structure and features of this patent can be fully understood from the above explanation.
第1図は従来のPLL局部発振回路のブロックダイヤグ
ラム。第2図は本発明のPLL局部発振回路例のブロッ
クダイヤグラム。第3図は本発明のPLL局部発振回路
の周波数構成例の説明図である。
特許出願人 八重洲無線株式会社
(9)Figure 1 is a block diagram of a conventional PLL local oscillation circuit. FIG. 2 is a block diagram of an example of a PLL local oscillation circuit according to the present invention. FIG. 3 is an explanatory diagram of an example of the frequency configuration of the PLL local oscillation circuit of the present invention. Patent applicant Yaesu Musen Co., Ltd. (9)
Claims (1)
ルX分周器に供給する第1のミクサと、周波数調整を行
うVFOと固定周波数のパラメータ発振器出力とを混合
する第2のミクサと、第2のミクサの出力を第1のミク
サに供給する回路に設けたBPFと、前記パラメータ発
振器の出力を直接に、またはPLL回路の基準周波数発
振器出力とを混合する第3のミクサを通した周波数を受
信機の後段部ミクサまたはプロダクト検波器に供給する
回路とよ構成シ、前記プログラマブル分周器の出力と基
準発振周波数またはこれを分周した周波数とを位相比較
し、VCOに制御電圧を供給する位相比較器とよ構成る
ことを特徴とするPLL回路。A first mixer that converts the frequency of a PLL-controlled VCO output and supplies it to a programmable The frequency passed through a third mixer that mixes the output of the parameter oscillator directly or the reference frequency oscillator output of the PLL circuit with a BPF provided in a circuit that supplies the output of the parameter oscillator to the first mixer is output to the receiver. The circuit for supplying to the rear-stage mixer or product detector includes a phase comparator that compares the phase of the output of the programmable frequency divider with a reference oscillation frequency or a frequency obtained by dividing the reference oscillation frequency, and supplies a control voltage to the VCO. A PLL circuit characterized by a Toyo configuration.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57161464A JPS5950617A (en) | 1982-09-16 | 1982-09-16 | Pll circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57161464A JPS5950617A (en) | 1982-09-16 | 1982-09-16 | Pll circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5950617A true JPS5950617A (en) | 1984-03-23 |
JPH0345936B2 JPH0345936B2 (en) | 1991-07-12 |
Family
ID=15735594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57161464A Granted JPS5950617A (en) | 1982-09-16 | 1982-09-16 | Pll circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5950617A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54103617A (en) * | 1978-02-01 | 1979-08-15 | Torio Kk | Local oscillator |
-
1982
- 1982-09-16 JP JP57161464A patent/JPS5950617A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54103617A (en) * | 1978-02-01 | 1979-08-15 | Torio Kk | Local oscillator |
Also Published As
Publication number | Publication date |
---|---|
JPH0345936B2 (en) | 1991-07-12 |
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