JPS5922446A - Phase locked circuit - Google Patents
Phase locked circuitInfo
- Publication number
- JPS5922446A JPS5922446A JP57132395A JP13239582A JPS5922446A JP S5922446 A JPS5922446 A JP S5922446A JP 57132395 A JP57132395 A JP 57132395A JP 13239582 A JP13239582 A JP 13239582A JP S5922446 A JPS5922446 A JP S5922446A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- phase
- pass filter
- characteristic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 16
- 230000003321 amplification Effects 0.000 claims description 2
- 238000007599 discharging Methods 0.000 claims description 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 claims 3
- 239000013078 crystal Substances 0.000 abstract description 11
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- 230000004044 response Effects 0.000 description 3
- 235000016496 Panda oleosa Nutrition 0.000 description 1
- 240000000220 Panda oleosa Species 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000004043 responsiveness Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は２例えば位相比較回路と低域通過フィルタ回
路と電圧制御発振回路とで構成される位相同期回路のな
かで、その回路中に非線形電圧制御発振回路を含む位相
同期回路に関するものであ茗。DETAILED DESCRIPTION OF THE INVENTION This invention provides two phase-locked circuits that include, for example, a phase comparator circuit, a low-pass filter circuit, and a voltage-controlled oscillation circuit. It's about synchronous circuits.
従来この種の回路として、水晶発振子を発振回路に使用
したものがあった。第１図にその印加電圧対発振周波数
特性の１例を示す。同図において。Conventionally, this type of circuit has used a crystal oscillator as an oscillation circuit. FIG. 1 shows an example of the applied voltage versus oscillation frequency characteristic. In the same figure.
理想特性０擾と水晶発振特性α０との差の大きいことが
判り、まだそれが非線形発振特性を有していることも判
る。ところで位相同期回路のその他の回路は線形特性を
有しているので９回路全体としても発振回路の非線形性
に帰因する動作をすることにな９．一般的な理論が摘要
できなくなり２回路が不安定になるという問題が発生す
る。It can be seen that there is a large difference between the ideal characteristic 0 and the crystal oscillation characteristic α0, and it can also be seen that it still has nonlinear oscillation characteristics. By the way, since the other circuits of the phase locked circuit have linear characteristics, the operation of the 9 circuits as a whole is due to the nonlinearity of the oscillation circuit.9. A problem arises in that the general theory cannot be summarized and the two circuits become unstable.
このことを定性的に説明すれば、印加電圧が４Ｖ以下で
は電圧の変化分をΔＶとしてΔｆ／△Ｖが大きく従って
周波数変動あるいは位相変動（ジッター）が理論値に対
して大きい動作をし、４Ｖ以上ではΔｆ／ΔＶが小さい
ので応答速度が理論値に対して遅くなる動作をすること
になる。ところで一般的に水晶振動子を使用した位相同
期回路は高安定度を要求しており、必然的に位相同期に
必要なプル・イン時間が長いという特質を）有しており
、更に非線形性によるプル・イン時間の遅れが加算され
ることは２機器全体の緒特性を劣化させることになる。To explain this qualitatively, when the applied voltage is 4V or less, Δf/ΔV is large, and the frequency fluctuation or phase fluctuation (jitter) is large compared to the theoretical value, and 4V In the above case, since Δf/ΔV is small, the response speed will be slower than the theoretical value. By the way, phase-locked circuits using crystal oscillators generally require high stability, and inevitably have the characteristic of long pull-in times required for phase locking. Addition of the pull-in time delay degrades the overall performance of the two devices.
例えばプル・イン時間３秒で設計しているにもかかわら
ず２周波数によっては４秒あるいは５秒のプル・イン時
間を必要とすることになシ。For example, even though it is designed with a pull-in time of 3 seconds, it may require a pull-in time of 4 or 5 seconds depending on the two frequencies.
その間はその使用されている機器が正常な動作が不可能
であるということになり２機器の動作応答性に対する信
頼を失うことにｋるという重大な問題点を有することに
なる。During this time, the equipment being used will be unable to operate normally, resulting in a serious problem in that confidence in the operational responsiveness of the two equipment will be lost.
従来の水晶発振子を使用した位相同期回路は。A phase-locked circuit using a conventional crystal oscillator.
以上のように非線形要素を有しているので、一般的な理
論設計が出来ないだけではなく、その動作が発振周波数
によって大きく異なシ従って機器の応答特性が一定でな
いという欠点があった、この発明は上記のような従来の
ものの欠点を除去するだめになさ・れだもので２位相比
較回路あるいは低域通過フィルタ回路等に水晶発振回路
の非線形性を打消す機能を付加することによって、線形
動作即ち動作一定の位相同期回路を得ることを目的とし
ている。As described above, since it has nonlinear elements, it not only precludes general theoretical design, but also has the disadvantage that the operation varies greatly depending on the oscillation frequency, and therefore the response characteristics of the device are not constant. In order to eliminate the above-mentioned drawbacks of the conventional circuit, it is possible to achieve linear operation by adding a function to cancel the nonlinearity of the crystal oscillator circuit to the two-phase comparator circuit or low-pass filter circuit, etc. That is, the purpose is to obtain a phase locked circuit with constant operation.
以下、この発明の一実施例を図について説明する。第２
図において、Ｑυは従来の位相比較回路のノコギリ波の
１部を示す図、 ＣＩ！、１は本発明の波形の１部を示
す図である。An embodiment of the present invention will be described below with reference to the drawings. Second
In the figure, Qυ is a diagram showing part of the sawtooth wave of a conventional phase comparator circuit, and CI! , 1 is a diagram showing a part of the waveform of the present invention.
第１図の水晶発振特性０υの電圧を変数としたときの関
数をｆｌ １ ”’ Ｆ（ｖ） １１とすれば、第２図
の特性曲線（イ）の関数をｆ２２として、ｆ１１×ｆ２
゜＝αＶ＋βすなわちｆ２２ ＝（ａｙ＋β）／ｆ１１
カ、 第２ 図１）ｔ３（Ｄ曲線に要求される特性であ
る。この１例を示したのが特性曲線（２渇であり、直線
Ｑυは第２図の特性曲線器と第１図の特性ａ０を乗算し
た結果である。If the function when the voltage of the crystal oscillation characteristic 0υ in Fig. 1 is taken as a variable is fl 1 ''' F(v) 11, then the function of the characteristic curve (a) in Fig. 2 is f22, then f11×f2
゜=αV+β or f22 = (ay+β)/f11
2) This is the characteristic required for the t3 (D curve in Figure 1).An example of this is the characteristic curve (2), and the straight line Qυ is the characteristic curver in Figure 2 and the characteristic curve in Figure 1. This is the result of multiplying by the characteristic a0.
今までの定性的説明を実際の物理量に対応させると、従
来の位相比較回路のノコギリ波が直線Ｑυであり、水晶
発振特性の非線形性を補正する波形が曲線（２）であれ
ばよいということになる。第３図に連続したこの波形例
を示す。第３図の（２擾の波形は簡単なコンデンサの充
放電回路あるいはその他の回路で実現できる。一方低域
通過フィルタ回路に補正回路を付加する場合には、第１
４図Ａに１例を示すような非直線増幅器を使用すればよ
い。第４図Ａにおいて、電圧Ｅ１とＲ２とかソフトクラ
ンプ回路の動作変換点となっており、第４図Ｂに示すｉ
ｅＯ特性、即ちここでは３折線近似増幅器を構成し
ている。ＥｌとＲ２との値は、第２図の曲線（２）Ｋ近
似できるように設定する。尚３折線に限ることはなく、
Ｎ折線近似での構成も可能である。If we apply the qualitative explanation so far to actual physical quantities, we can say that the sawtooth wave of the conventional phase comparator circuit is a straight line Qυ, and the waveform for correcting the nonlinearity of the crystal oscillation characteristics should be curve (2). become. FIG. 3 shows a continuous example of this waveform. The waveform shown in Figure 3 (2 waves) can be realized using a simple capacitor charging/discharging circuit or other circuits.On the other hand, when adding a correction circuit to the low-pass filter circuit, the first
A non-linear amplifier, an example of which is shown in Figure 4A, may be used. In Fig. 4A, voltages E1 and R2 are the operational conversion points of the soft clamp circuit, and i as shown in Fig. 4B.
eO characteristic, that is, it constitutes a three-fold line approximation amplifier here. The values of El and R2 are set so that curve (2)K in FIG. 2 can be approximated. It should be noted that it is not limited to three-fold lines,
A configuration based on N-fold line approximation is also possible.
次に、第５図に、第３図に示すＯＲ充放電波形を使用し
た回路例の詳細を示し、第６図に第４図に示す３折線近
似増幅器を使用した回路例の詳細を示し、以下それぞれ
の回路動作について説明する。Next, FIG. 5 shows details of a circuit example using the OR charge/discharge waveform shown in FIG. 3, and FIG. 6 shows details of a circuit example using the three-fold line approximation amplifier shown in FIG. The operation of each circuit will be explained below.
第５図において、水晶を使用した電圧制御発振回路（５
■の出力信号（ａ）をＮ分周回路（６０）で分周し。In Figure 5, a voltage controlled oscillation circuit (5
The output signal (a) of (2) is divided by the N frequency divider circuit (60).
信号（ｂ）（ここではＮ’＝８と仮定）を得る。この信
号（ｂ）の１１Ｈ〃及び゛ゝＬ〃レベルに対してそれぞ
れＳＷｌをオン及びオフ動作させる。オン状態ではコン
デンサＣは、 ＋ １０ Ｖの電位に固定されオフ状態
では抵抗Ｒを通して放電電流が流れ、結果として信号（
Ｃ）を得る。この信号（ｃ）に後段回路が影響を与えな
いためにバッファ増幅器を接続し、この出力信号から外
部位相比較信号（ｆ）でＳＷ２をオン・オフ動作させて
信号（ｄ）を得る。信号（ｂ）と信号（ｆ）とを入力し
て信号（ｄ）を得る回路が位相比較回路（７０）を構成
している。この出力信号（ｄ）を低域フィルタ回路（８
０）で高周波成分を除去して、電圧制御発振回路６０）
に負帰還動作をする極性で印加する。このループで位相
同期回路が構成できる。A signal (b) (assuming N'=8 here) is obtained. SW1 is turned on and off for the 11H and ``L'' levels of this signal (b), respectively. In the on state, the capacitor C is fixed at a potential of +10 V, and in the off state, a discharge current flows through the resistor R, resulting in a signal (
C) is obtained. A buffer amplifier is connected so that the subsequent circuit does not affect this signal (c), and from this output signal, SW2 is turned on and off using an external phase comparison signal (f) to obtain signal (d). A circuit that inputs the signal (b) and the signal (f) and obtains the signal (d) constitutes a phase comparison circuit (70). This output signal (d) is passed to the low-pass filter circuit (8
0) to remove high frequency components and create a voltage controlled oscillation circuit 60).
Apply the polarity to perform negative feedback operation. A phase-locked circuit can be constructed with this loop.
次に第６図を説明する。同図において、第５図と異なる
部分について、動作説明をする。位相比較回路（９０）
では、一般的なノコギリ波発生回路をＮ分周信号（１，
）で制御して波形（ｇ）を得て、これを外部位相比較信
号（ｆ）でＥＩＷ２をオン・オフして誤差信号（ｈ）を
得る。誤差信号（ｈ）と前記信号（ｄ）とを比較して、
かなシの差があることが分る。誤差信号（ｈ）を低域フ
ィルタ回路（Ｉ Ｄｏ）の回路中Ｃ４どＲ１とで構成す
るフィルタで低域成分を抽出し、その出力信＼
号をボリュームで適当なレベルまで減衰させて増幅器の
非反転入力端子に印加する。一方２反転増幅器には折線
近似回路を接続する。Next, FIG. 6 will be explained. In this figure, the operation will be explained about the parts that are different from those in FIG. 5. Phase comparison circuit (90)
Now, we will explain how to use a general sawtooth wave generation circuit with N-divided signal (1,
) to obtain a waveform (g), which is then used to turn on and off the EIW2 using an external phase comparison signal (f) to obtain an error signal (h). Comparing the error signal (h) and the signal (d),
It can be seen that there is a difference in kana. The low frequency component of the error signal (h) is extracted using a filter consisting of C4 and R1 in the low pass filter circuit (I Do), and the output signal is attenuated to an appropriate level using a volume and then output to the amplifier. Apply to the non-inverting input terminal. On the other hand, a broken line approximation circuit is connected to the 2-inverting amplifier.
増幅器の出力が電圧Ｅ１＋ダイオードＤ１電圧（ｏ、ｅ
ｖ）よシ大きくなると利得が（ｔ ＋ Ｒ５／Ｒ４）と
なシ、電圧Ｅ２に対しても同様に利得が変化しく１十Ｒ
，ｙ ／ Ｒ４／ Ｒ５）となる。電圧’Ｆ、＋０．６
Ｖ以下では利得が１とガる。以上の３折線近似特性は、
第５図の信号（ｄ）に第６図の信号（ｈ）が近似できる
ように各電圧及び抵抗値を設定する。なお電圧Ｅ１とＥ
２との関係はＥ２〉Ｅｌである。以上の構成によって位
相同期回路が本発明の動作をする。The output of the amplifier is voltage E1 + diode D1 voltage (o, e
v) As the voltage increases, the gain becomes (t + R5/R4), and the gain similarly changes with respect to the voltage E2.
,y/R4/R5). Voltage 'F, +0.6
Below V, the gain is 1. The above three-fold line approximation characteristics are
Each voltage and resistance value is set so that the signal (h) in FIG. 6 approximates the signal (d) in FIG. Note that the voltages E1 and E
2 is E2>El. With the above configuration, the phase locked circuit operates according to the present invention.
なお、Ｎ分周回路（６０）のＮは１以上の整数であシ、
増幅器の利得あるいは＋ＩＯＶ電圧等は任意に設定可能
なパラメータである。Note that N of the N frequency divider circuit (60) must be an integer of 1 or more;
The amplifier gain, +IOV voltage, etc. are parameters that can be set arbitrarily.
また、上記実施例では位相比較回路としてノコギリ波を
使用する場合について説明しだが、これに限ることなく
一般的々デジタル位相比較回路の場合でも同様な構成が
可能である。さらにまた。Further, in the above embodiment, the case where a sawtooth wave is used as the phase comparator circuit has been described, but the present invention is not limited to this, and a similar configuration is possible in the case of a general digital phase comparator circuit. Yet again.
発振子として水晶を例にして説明したがこれに限らず、
非線形特性を有する発振子に対して同様々構成が可能で
あることは言うまでもない。Although the explanation uses a crystal as an example of an oscillator, it is not limited to this.
It goes without saying that a similar configuration is possible for an oscillator having nonlinear characteristics.
以上のように、この発明によれば電圧発振特性の非線形
特性をその逆特性で補正する構成としたので９丈の応答
動作特性が一定で、かつ位相ジツートニ・＼
りの少ない安定した位相同期回路が得られる効果がある
。As described above, according to the present invention, since the nonlinear characteristic of the voltage oscillation characteristic is corrected by its inverse characteristic, a stable phase-locked circuit with constant response operation characteristics and less phase shift and deviation can be achieved. There is an effect that can be obtained.
第１図は水晶発振特性の１例を示す印加電圧対発振周波
数特性図、第２図は補正特性の１例を示す図、第３図は
位相比較回路の電圧波形例を示す波形図、第４図Ａは非
線形増＠器の１例を示す回路図、第４図Ｂは第４図Ａに
示す増幅器の増幅特性図、第５図第６図はそれぞれこの
発明の実施例を示し、第５図Ａ、第６図Ａはその回路構
成図。
第５図Ｂ、第６図Ｂはその動作を説明するための波形図
である。
図中、６０）は電圧制御発振回路、 （６Ｏ）はＮ分周
回路、 （７０）Ｉ′ｉ位置比較回路、 （ｓｏ）は低
域フィルタ回路である。
なお２図中同一符号は同一または相当部分を示す。
代理人 葛野信−
第１図
す。−ｂｆ Ｔｏ
７．＋ａす第３図
第４図Ａ
ρ９Fig. 1 is an applied voltage vs. oscillation frequency characteristic diagram showing an example of crystal oscillation characteristics, Fig. 2 is a diagram showing an example of correction characteristics, Fig. 3 is a waveform diagram showing an example of voltage waveform of a phase comparator circuit, FIG. 4A is a circuit diagram showing an example of a nonlinear amplifier, FIG. 4B is an amplification characteristic diagram of the amplifier shown in FIG. 4A, FIG. 5 and FIG. 5A and 6A are circuit configuration diagrams thereof. FIG. 5B and FIG. 6B are waveform diagrams for explaining the operation. In the figure, 60) is a voltage controlled oscillation circuit, (6O) is an N frequency divider circuit, (70) is an I'i position comparison circuit, and (so) is a low-pass filter circuit. Note that the same reference numerals in the two figures indicate the same or corresponding parts. Agent Makoto Kuzuno - Figure 1. -bf To
7. +a Figure 3 Figure 4 A ρ9
Claims (3)
いて、線形な特性を得る送特性補正手段を設けたことを
特徴とする位相同期回路。(1) A phase-locked circuit including a non-linear voltage oscillation characteristic, characterized in that the phase-locked circuit includes transmission characteristic correction means for obtaining linear characteristics.
たことを特徴とする特許請求の範囲第１項記載の位相同
期回路。(2) The phase-locked circuit according to claim 1, wherein the means for realizing the transmission characteristics is constituted by non-linear amplification means.
波波形を利用し、かつその波形発生手段としてＯＲ充放
電回路を使用したことを特徴とする特許請求の範囲第１
項記載の位相同期回路。(3) The means for realizing the transmission characteristics utilizes a sawtooth waveform in the phase comparator circuit, and an OR charging/discharging circuit is used as the waveform generating means.
Phase-locked circuit described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57132395A JPS5922446A (en) | 1982-07-29 | 1982-07-29 | Phase locked circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57132395A JPS5922446A (en) | 1982-07-29 | 1982-07-29 | Phase locked circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5922446A true JPS5922446A (en) | 1984-02-04 |
Family
ID=15080382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57132395A Pending JPS5922446A (en) | 1982-07-29 | 1982-07-29 | Phase locked circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5922446A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6157718U (en) * | 1984-09-20 | 1986-04-18 | ||
| EP0390800A1 (en) * | 1987-11-18 | 1990-10-10 | Magellan Corp Australia | Integratable phase-locked loop. |
-
1982
- 1982-07-29 JP JP57132395A patent/JPS5922446A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6157718U (en) * | 1984-09-20 | 1986-04-18 | ||
| EP0390800A1 (en) * | 1987-11-18 | 1990-10-10 | Magellan Corp Australia | Integratable phase-locked loop. |
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